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PSMN7R0-30YL [NXP]

N-channel TrenchMOS logic level FET; N沟道的TrenchMOS逻辑电平FET
PSMN7R0-30YL
型号： PSMN7R0-30YL
厂家： NXP    NXP
描述：

N-channel TrenchMOS logic level FET
N沟道的TrenchMOS逻辑电平FET

晶体 晶体管 功率场效应晶体管 开关 脉冲
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PSMN7R0-30YL  
N-channel TrenchMOS logic level FET  
Rev. 01 — 15 October 2008  
Preliminary data sheet  
1. Product profile  
1.1 General description  
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic  
package using TrenchMOS technology. This product is designed and qualified for use in  
industrial and communications applications.  
1.2 Features and benefits  
„ High efficiency due to low switching  
„ Suitable for logic level gate drive  
and conduction losses  
sources  
1.3 Applications  
„ Class-D amplifiers  
„ DC-to-DC converter  
„ Motor control  
„ Server power supplies  
1.4 Quick reference data  
Table 1.  
Quick reference  
Symbol Parameter  
Conditions  
drain-source voltage Tj ≥ 25 °C; Tj ≤ 150 °C  
Min  
Typ  
Max Unit  
VDS  
ID  
-
-
-
-
30  
65  
V
A
drain current  
Tmb = 25 °C; VGS = 10 V;  
see Figure 1  
Ptot  
total power  
dissipation  
Tmb = 25 °C; see Figure 2  
-
-
-
51  
-
W
Dynamic characteristics  
QGD gate-drain charge  
VGS = 4.5 V; ID = 10 A;  
VDS = 12 V; see Figure 14;  
see Figure 15  
2.9  
nC  
Static characteristics  
RDSon  
drain-source  
on-state resistance  
VGS = 10 V; ID = 15 A;  
Tj = 25 °C; see Figure 12;  
see Figure 13  
-
4.7  
7
mΩ  
PSMN7R0-30YL  
NXP Semiconductors  
N-channel TrenchMOS logic level FET  
2. Pinning information  
Table 2.  
Pinning information  
Pin  
1
Symbol Description  
Simplified outline  
Graphic symbol  
S
S
S
G
D
source  
source  
source  
gate  
mb  
D
2
3
G
4
mbb076  
S
mb  
mounting base; connected to  
drain  
1
2 3 4  
SOT669  
(LFPAK)  
3. Ordering information  
Table 3.  
Ordering information  
Type number  
Package  
Name  
Description  
plastic single-ended surface-mounted package (LFPAK); 4 leads  
Version  
PSMN7R0-30YL  
LFPAK  
SOT669  
4. Limiting values  
Table 4.  
Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
Symbol  
VDS  
Parameter  
Conditions  
Min  
Max  
30  
Unit  
drain-source voltage  
drain-gate voltage  
gate-source voltage  
drain current  
Tj ≥ 25 °C; Tj ≤ 150 °C  
Tj ≥ 25 °C; Tj ≤ 150 °C; RGS = 20 kΩ  
-
V
VDGR  
VGS  
-
30  
V
-20  
20  
V
ID  
VGS = 10 V; Tmb = 100 °C; see Figure 1  
VGS = 10 V; Tmb = 25 °C; see Figure 1  
tp ≤ 10 µs; pulsed; Tmb = 25 °C; see Figure 3  
-
46  
A
-
65  
A
IDM  
Ptot  
Tstg  
Tj  
peak drain current  
-
260  
51  
A
total power dissipation Tmb = 25 °C; see Figure 2  
storage temperature  
-
W
°C  
°C  
-55  
-55  
150  
150  
junction temperature  
Source-drain diode  
IS  
source current  
peak source current  
Tmb = 25 °C  
-
-
65  
A
A
ISM  
tp ≤ 10 µs; pulsed; Tmb = 25 °C  
260  
Avalanche ruggedness  
EDS(AL)S  
non-repetitive  
VGS = 10 V; Tj(init) = 25 °C; ID = 65 A; Vsup ≤ 30 V;  
-
21  
mJ  
drain-source avalanche RGS = 50 Ω; unclamped  
energy  
PSMN7R0-30YL_1  
© NXP B.V. 2008. All rights reserved.  
Preliminary data sheet  
Rev. 01 — 15 October 2008  
2 of 13  
PSMN7R0-30YL  
NXP Semiconductors  
N-channel TrenchMOS logic level FET  
003aac720  
03aa15  
120  
80  
ID  
P
(%)  
(A)  
der  
60  
40  
20  
0
80  
40  
0
0
50  
100  
150  
200  
0
50  
100  
150  
200  
Tmb (°C)  
T
mb  
(°C)  
Fig 1. Continuous drain current as a function of  
mounting base temperature  
Fig 2. Normalized total power dissipation as a  
function of mounting base temperature  
003aac732  
103  
ID  
Limit RDSon = VDS / ID  
(A)  
102  
10  
s
μ
100  
s
μ
10  
1
DC  
1 ms  
10 ms  
100 ms  
10-1  
10-1  
1
10  
102  
VDS (V)  
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage  
PSMN7R0-30YL_1  
© NXP B.V. 2008. All rights reserved.  
Preliminary data sheet  
Rev. 01 — 15 October 2008  
3 of 13  
PSMN7R0-30YL  
NXP Semiconductors  
N-channel TrenchMOS logic level FET  
5. Thermal characteristics  
Table 5.  
Symbol  
Rth(j-mb)  
Thermal characteristics  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
thermal resistance from see Figure 4  
junction to mounting  
base  
-
1.4  
2.45  
K/W  
003aac721  
10  
Zth(j-mb)  
(K/W)  
δ = 0.5  
1
10-1  
10-2  
0.2  
0.1  
0.05  
tp  
δ =  
P
0.02  
T
t
tp  
single shot  
T
10-6  
10-5  
10-4  
10-3  
10-2  
10-1  
tp (s)  
1
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration  
PSMN7R0-30YL_1  
© NXP B.V. 2008. All rights reserved.  
Preliminary data sheet  
Rev. 01 — 15 October 2008  
4 of 13  
PSMN7R0-30YL  
NXP Semiconductors  
N-channel TrenchMOS logic level FET  
6. Characteristics  
Table 6.  
Symbol  
Characteristics  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Static characteristics  
V(BR)DSS  
drain-source  
breakdown voltage  
ID = 250 µA; VGS = 0 V; Tj = 25 °C  
ID = 250 µA; VGS = 0 V; Tj = -55 °C  
30  
27  
1.3  
-
-
V
V
V
-
-
VGS(th)  
gate-source threshold ID = 1 mA; VDS = VGS; Tj = 25 °C; see  
1.7  
2.15  
voltage  
Figure 10; see Figure 11  
ID = 1 mA; VDS = VGS; Tj = 150 °C; see  
Figure 10  
0.65  
-
-
-
-
V
V
ID = 1 mA; VDS = VGS; Tj = -55 °C; see  
Figure 10  
2.45  
IDSS  
drain leakage current  
gate leakage current  
VDS = 30 V; VGS = 0 V; Tj = 25 °C  
VDS = 30 V; VGS = 0 V; Tj = 150 °C  
VGS = 16 V; VDS = 0 V; Tj = 25 °C  
VGS = -16 V; VDS = 0 V; Tj = 25 °C  
-
-
-
-
-
-
1
µA  
µA  
nA  
nA  
mΩ  
-
100  
100  
100  
11.3  
IGSS  
-
-
RDSon  
drain-source on-state  
resistance  
VGS = 4.5 V; ID = 15 A; Tj = 25 °C; see  
Figure 12; see Figure 13  
6.7  
VGS = 10 V; ID = 15 A; Tj = 150 °C; see  
Figure 12  
-
-
-
-
12.2  
mΩ  
mΩ  
Ω
VGS = 10 V; ID = 15 A; Tj = 25 °C; see  
4.7  
0.6  
7
-
Figure 12; see Figure 13  
RG  
gate resistance  
f = 1 MHz  
Dynamic characteristics  
QG(tot)  
total gate charge  
ID = 10 A; VDS = 12 V; VGS = 4.5 V; see  
Figure 14; see Figure 15  
-
10  
-
nC  
ID = 0 A; VDS = 0 V; VGS = 10 V  
-
-
20  
22  
-
-
nC  
nC  
ID = 10 A; VDS = 12 V; VGS = 10 V; see  
Figure 14; see Figure 15  
QGS  
gate-source charge  
ID = 10 A; VDS = 12 V; VGS = 4.5 V; see  
Figure 14; see Figure 15  
-
-
3.7  
2.1  
-
-
nC  
nC  
QGS(th)  
pre-threshold  
gate-source charge  
QGS(th-pl)  
post-threshold  
-
1.6  
-
nC  
gate-source charge  
QGD  
gate-drain charge  
-
-
2.9  
2.6  
-
-
nC  
V
VGS(pl)  
gate-source plateau  
voltage  
VDS = 12 V; see Figure 14; see Figure 15  
Ciss  
Coss  
Crss  
input capacitance  
output capacitance  
VDS = 12 V; VGS = 0 V; f = 1 MHz;  
Tj = 25 °C; see Figure 16  
-
-
-
1270  
255  
-
-
-
pF  
pF  
pF  
reverse transfer  
capacitance  
145  
td(on)  
tr  
td(off)  
tf  
turn-on delay time  
rise time  
VDS = 12 V; RL = 0.5 Ω; VGS = 4.5 V;  
RG(ext) = 4.7 Ω  
-
-
-
-
24  
39  
30  
11  
-
-
-
-
ns  
ns  
ns  
ns  
turn-off delay time  
fall time  
PSMN7R0-30YL_1  
© NXP B.V. 2008. All rights reserved.  
Preliminary data sheet  
Rev. 01 — 15 October 2008  
5 of 13  
PSMN7R0-30YL  
NXP Semiconductors  
N-channel TrenchMOS logic level FET  
Table 6.  
Symbol  
Characteristics …continued  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Source-drain diode  
VSD  
source-drain voltage  
IS = 25 A; VGS = 0 V; Tj = 25 °C; see  
Figure 17  
-
0.88  
1.2  
V
trr  
reverse recovery time  
recovered charge  
IS = 20 A; dIS/dt = -100 A/µs; VGS = 0 V;  
VDS = 20 V  
-
-
30  
22  
-
-
ns  
Qr  
nC  
003aac729  
003aac728  
80  
60  
ID  
gfs  
(A)  
(S)  
60  
40  
20  
0
50  
40  
Tj = 150 °C  
25 °C  
30  
0
1
2
3
4
0
10  
20  
30  
40  
VGS (V)  
ID (A)  
Fig 5. Transfer characteristics: drain current as a  
function of gate-source voltage; typical values  
Fig 6. Forward transconductance as a function of  
drain current; typical values  
003aac727  
003aac726  
100  
14  
10  
ID  
RDSon  
(A)  
(mΩ)  
VGS (V) = 4.5  
80  
12  
10  
8
60  
3.2  
3
40  
2.8  
6
20  
2.6  
2.4  
2.2  
4
0
2
4
6
8
10  
0
2
4
6
8
10  
VGS (V)  
V
DS (V)  
Fig 7. Drain-source on-state resistance as a function  
of gate-source voltage; typical values  
Fig 8. Output characteristics: drain current as a  
function of drain-source voltage; typical values  
PSMN7R0-30YL_1  
© NXP B.V. 2008. All rights reserved.  
Preliminary data sheet  
Rev. 01 — 15 October 2008  
6 of 13  
PSMN7R0-30YL  
NXP Semiconductors  
N-channel TrenchMOS logic level FET  
003aac724  
003aab272  
3
2500  
C
(pF)  
V
GS(th)  
(V)  
Ciss  
2000  
max  
2
Crss  
1500  
1000  
500  
0
typ  
1.5  
min  
1
0.5  
0
-60  
0
2
4
6
8
10  
VGS (V)  
0
60  
120  
180  
T (°C)  
j
Fig 10. Gate-source threshold voltage as a function of  
junction temperature  
Fig 9. Input and reverse transfer capacitances as a  
function of gate-source voltage; typical values  
003aab273  
003aab271  
−3  
10  
2
a
I
D
(A)  
1.6  
−4  
−5  
−6  
10  
max  
min  
typ  
1.2  
0.8  
0.4  
0
10  
10  
-60  
0
60  
120  
180  
0
0.5  
1
1.5  
2
2.5  
(V)  
Tj (°C)  
V
GS  
Fig 11. Sub-threshold drain current as a function of  
gate-source voltage  
Fig 12. Normalized drain-source on-state resistance  
factor as a function of junction temperature  
PSMN7R0-30YL_1  
© NXP B.V. 2008. All rights reserved.  
Preliminary data sheet  
Rev. 01 — 15 October 2008  
7 of 13  
PSMN7R0-30YL  
NXP Semiconductors  
N-channel TrenchMOS logic level FET  
003aac722  
16  
V
DS  
RDSon  
3.2  
(mΩ)  
14  
I
D
12  
10  
8
V
GS(pl)  
V
GS(th)  
V
GS  
Q
GS1  
Q
GS2  
VGS (V) = 4.5  
Q
GS  
Q
GD  
6
Q
G(tot)  
10  
003aaa508  
4
Fig 14. Gate charge waveform definitions  
0
20  
40  
60  
80  
100  
ID (A)  
Fig 13. Drain-source on-state resistance as a function  
of drain current; typical values  
003aac725  
003aac723  
10  
1600  
VGS  
(V)  
Ciss  
C
(pF)  
8
VDS = 12 (V)  
1200  
800  
400  
0
Coss  
6
VDS = 19 (V)  
4
2
0
Crss  
0
5
10  
15  
20  
25  
G (nC)  
10-1  
1
10  
102  
VDS (V)  
Q
Fig 15. Gate-source voltage as a function of gate  
charge; typical values  
Fig 16. Input, output and reverse transfer capacitances  
as a function of drain-source voltage; typical  
values  
PSMN7R0-30YL_1  
© NXP B.V. 2008. All rights reserved.  
Preliminary data sheet  
Rev. 01 — 15 October 2008  
8 of 13  
PSMN7R0-30YL  
NXP Semiconductors  
N-channel TrenchMOS logic level FET  
003aac730  
80  
IS  
(A)  
60  
40  
20  
0
Tj = 150 °C  
25 °C  
0.0  
0.2  
0.4  
0.6  
0.8  
1.0  
SD (V)  
V
Fig 17. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values  
PSMN7R0-30YL_1  
© NXP B.V. 2008. All rights reserved.  
Preliminary data sheet  
Rev. 01 — 15 October 2008  
9 of 13  
PSMN7R0-30YL  
NXP Semiconductors  
N-channel TrenchMOS logic level FET  
7. Package outline  
Plastic single-ended surface-mounted package (LFPAK); 4 leads  
SOT669  
A
2
E
A
C
c
E
1
b
2
2
b
3
L
1
mounting  
base  
b
4
D
1
D
H
L
2
1
2
3
4
X
e
w
M
c
A
b
1/2 e  
A
(A )  
3
C
A
1
θ
L
detail X  
y
C
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
(1)  
D
(1)  
D
(1)  
(1)  
1
A
A
A
H
L
L
L
2
w
y
θ
UNIT  
A
b
b
b
b
c
c
E
E
1
e
1
2
3
1
2
3
4
2
max  
1.20 0.15 1.10  
1.01 0.00 0.95  
0.50 4.41 2.2 0.9 0.25 0.30 4.10  
0.35 3.62 2.0 0.7 0.19 0.24 3.80  
5.0 3.3  
4.8 3.1  
6.2 0.85 1.3 1.3  
5.8 0.40 0.8 0.8  
8°  
0°  
mm  
0.25  
4.20  
1.27  
0.25 0.1  
Note  
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
04-10-13  
06-03-16  
SOT669  
MO-235  
Fig 18. Package outline SOT669 (LFPAK)  
PSMN7R0-30YL_1  
© NXP B.V. 2008. All rights reserved.  
Preliminary data sheet  
Rev. 01 — 15 October 2008  
10 of 13  
PSMN7R0-30YL  
NXP Semiconductors  
N-channel TrenchMOS logic level FET  
8. Revision history  
Table 7.  
Revision history  
Document ID  
Release date  
Data sheet status  
Change notice  
Supersedes  
PSMN7R0-30YL_1  
20081015  
Preliminary data sheet  
-
-
PSMN7R0-30YL_1  
© NXP B.V. 2008. All rights reserved.  
Preliminary data sheet  
Rev. 01 — 15 October 2008  
11 of 13  
PSMN7R0-30YL  
NXP Semiconductors  
N-channel TrenchMOS logic level FET  
9. Legal information  
9.1 Data sheet status  
Document status [1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term 'short data sheet' is explained in section "Definitions".  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product  
status information is available on the Internet at URL http://www.nxp.com.  
Applications — Applications that are described herein for any of these  
9.2 Definitions  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Quick reference data — The Quick reference data is an extract of the  
product data given in the Limiting values and Characteristics sections of this  
document, and as such is not complete, exhaustive or legally binding.  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) may cause permanent  
damage to the device. Limiting values are stress ratings only and operation of  
the device at these or any other conditions above those given in the  
Characteristics sections of this document is not implied. Exposure to limiting  
values for extended periods may affect device reliability.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Terms and conditions of sale — NXP Semiconductors products are sold  
subject to the general terms and conditions of commercial sale, as published  
at http://www.nxp.com/profile/terms, including those pertaining to warranty,  
intellectual property rights infringement and limitation of liability, unless  
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of  
any inconsistency or conflict between information in this document and such  
terms and conditions, the latter will prevail.  
9.3 Disclaimers  
General — Information in this document is believed to be accurate and  
reliable. However, NXP Semiconductors does not give any representations or  
warranties, expressed or implied, as to the accuracy or completeness of such  
information and shall have no liability for the consequences of use of such  
information.  
No offer to sell or license — Nothing in this document may be interpreted or  
construed as an offer to sell products that is open for acceptance or the grant,  
conveyance or implication of any license under any copyrights, patents or  
other industrial or intellectual property rights.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
9.4 Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
Suitability for use — NXP Semiconductors products are not designed,  
authorized or warranted to be suitable for use in medical, military, aircraft,  
space or life support equipment, nor in applications where failure or  
malfunction of an NXP Semiconductors product can reasonably be expected  
to result in personal injury, death or severe property or environmental  
damage. NXP Semiconductors accepts no liability for inclusion and/or use of  
NXP Semiconductors products in such equipment or applications and  
therefore such inclusion and/or use is at the customer’s own risk.  
TrenchMOS — is a trademark of NXP B.V.  
10. Contact information  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
PSMN7R0-30YL_1  
© NXP B.V. 2008. All rights reserved.  
Preliminary data sheet  
Rev. 01 — 15 October 2008  
12 of 13  
PSMN7R0-30YL  
NXP Semiconductors  
N-channel TrenchMOS logic level FET  
11. Contents  
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1  
1.1  
1.2  
1.3  
1.4  
General description . . . . . . . . . . . . . . . . . . . . . .1  
Features and benefits. . . . . . . . . . . . . . . . . . . . .1  
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1  
Quick reference data . . . . . . . . . . . . . . . . . . . . .1  
2
3
4
5
6
7
8
Pinning information. . . . . . . . . . . . . . . . . . . . . . .2  
Ordering information. . . . . . . . . . . . . . . . . . . . . .2  
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2  
Thermal characteristics . . . . . . . . . . . . . . . . . . .4  
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .5  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . .10  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . .11  
9
Legal information. . . . . . . . . . . . . . . . . . . . . . . .12  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . .12  
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .12  
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .12  
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .12  
9.1  
9.2  
9.3  
9.4  
10  
Contact information. . . . . . . . . . . . . . . . . . . . . .12  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2008.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: Rev. 01 — 15 October 2008  
Document identifier: PSMN7R0-30YL_1  

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