SAA7157T-T [NXP]
IC 29 MHz, VIDEO CLOCK GENERATOR, PDSO20, Clock Generator;
| 型号： | SAA7157T-T |
| 厂家： | 
NXP |
| 描述： | IC 29 MHz, VIDEO CLOCK GENERATOR, PDSO20, Clock Generator 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总12页 (文件大小：68K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
SAA7157
Clock signal generator circuit for
digital TV systems (SCGC)
May 1992
Product specification
File under Integrated Circuits, IC02
Philips Semiconductors
Product specification
Clock signal generator circuit for digital TV
systems (SCGC)
SAA7157
FEATURES
• Clock generation suitable for digital TV systems (line-locked)
• PLL frequency multiplier to generate 4 times of input frequency
• Dividers to generate clocks LL1.5A, LL1.5B, LL3A and LL3B (4th and 2nd multiples of input frequency)
• PLL mode or VCO mode selectable
• Reset control and power fail detection
• Suitable for applications with feature box and picture memory
GENERAL DESCRIPTION
The SAA7157 generates all clock signals required for a digital TV system suitable for the SAA715x family and the
SAA7199B (DENC). The circuit operates in either the phase-locked loop mode (PLL) or voltage controlled oscillator
mode (VCO).
QUICK REFERENCE DATA
SYMBOL
VDDA
VDDD
IDDA
PARAMETER
analog supply voltage (pin 5)
MIN. TYP. MAX. UNIT
4.5
4.5
3
5.0
5.0
-
5.5
5.5
9
V
digital supply voltage (pins 8, 17)
analog supply current
V
mA
mA
IDDD
digital supply current
10
-
60
VLFCO
LFCO input voltage
(peak-to-peak value)
1
-
-
VDDA
7.25
V
fi
input frequency range
6.0
MHz
VI
input voltage LOW
input voltage HIGH
0
2.0
-
-
0.8
VDDD
V
V
VO
output voltage LOW
output voltage HIGH
0
2.6
-
-
0.6
VDDD
V
V
Tamb
operating ambient temperature range
0
-
70
°C
ORDERING INFORMATION
PACKAGE
MATERIAL
EXTENDED
TYPE NUMBER
PINS
20
PIN POSITION
DIL
CODE
SAA7157
plastic
plastic
SOT146(1)
SOT163A(2)
SAA7157T
20
mini-pack (SO20)
Note
1. SOT146-1; 1996 December 17.
2. SOT163-1; 1996 December 17.
May 1992
2
Philips Semiconductors
Product specification
Clock signal generator circuit for digital TV
systems (SCGC)
SAA7157
V
V
V
DDD1 DDD2
DDA
5
8
17
1
MS
7
10
14
20
15
LL1.5A
(LL27A)
LOOP
FILTER
VCO
MS = LOW
LL1.5B
(LL27B)
FREQUENCY
DIVIDER
1 : 2
SAA7157
LL3A
LL3B
CREF
FREQUENCY
DIVIDER
1 : 2
PHASE
DETECTOR
DELAY
PRE-FILTER
AND
PULSE
11
LFCO
POWER-ON
RESET
12
SHAPER
RESN
19
2
LFCO2
CE
16
3
4
6, 9, 13, 18
MEH452
PORD
V
V
SSD
LFCOSEL
SSA
Fig.1 Block diagram.
FUNCTIONAL DESCRIPTION
Mode select MS
The SAA7157 generates all clock signals required for a
digital TV system suitable for the SAA715x family
consisting of an 8-bit analog-to-digital converter (ADC8),
digital video multistandard decoder (DMSD2) and video
enhancement and D/A processor circuit (VEDA). Optional
extras (feature box, video memory etc.) can be driven via
external buffers, advantageous for a digital TV system
based on display standard conversion concepts.
The 6.75 MHz input signal LFCO (triangular waveform)
coming from the DMSD or LFCO2 is multiplied to 27 MHz
by the PLL (including phase detector, loop filter, VCO and
frequency divider) and output on LL1.5A (pin 7) and
LL1.5B (pin 10). The 13.5 MHz frequencies are generated
by dividers using ratio of 1:2 and are output on LL3A (pin
14) and LL3B (pin 20).
The LFCO input signal is directly connected to the VCO at
MS = HIGH. The circuit operates as an oscillator and
frequency divider. This function is not tested.
Source select LFCOSEL
Line frequency control signal (LFCO) is selected by
LFCOSEL input.
LFCOSEL = LOW:
signal from LFCO (pin 11) is selected.
LFCOSEL = HIGH:
signal from LFCO2 (pin 19) is selected.
This function is not tested.
Chip enable CE
The rectangular output signals have 50% duty factor.
Outputs with equal frequency may be connected together
externally. The clock outputs go HIGH during power-on
reset (and chip enable) to ensure that no output clock
signals are available before the PLL has locked-on.
The buffer outputs are enabled and RESN is set to HIGH
by
CE = HIGH (Fig.4).
CE = LOW sets the clock outputs HIGH and RESN output
LOW.
May 1992
3
Philips Semiconductors
Product specification
Clock signal generator circuit for digital TV
systems (SCGC)
SAA7157
CREF output
TV2 digital clock reference output signal. Clock qualifier signal to TV system with 2 times of LFCO or LFCO2 frequency.
Power-on reset
Power-on reset is activated at power-on, when the supply voltage decreases below 3.5 V (Fig.4) or when chip enable is
done. The indicator output RESN is LOW for a time determined by capacitor on pin 3. The RESN signal can be applied
to reset other circuits of this digital TV system.
The LFCO or LFCO2 input signals have to be applied before RESN becomes HIGH.
PINNING
SYMBOL
PIN DESCRIPTION
MS
1
2
mode select input (LOW = PLL mode)
CE
chip enable /reset (HIGH = outputs enabled)
power-on reset delay, dependent on external capacitor
analog ground (0 V)
PORD
VSSA
3
4
VDDA
5
analog supply voltage (+5 V)
VSSD1
LL1.5A
VDDD1
VSSD2
LL1.5B
LFCO
RESN
VSSD3
LL3A
6
digital ground 1 (0 V)
7
line-locked clock output signal 1.5A (4 times fLFCO
)
)
8
digital supply voltage 1 (+5 V)
9
digital ground 2 (0 V)
10
11
12
13
14
15
16
17
18
19
20
line-locked clock output signal 1.5B (4 times fLFCO
line-locked frequency control input signal 1
reset output (active-LOW, Fig.4)
digital ground 3 (0 V)
line-locked clock output signal 3A (2 times fLFCO
)
CREF
LFCOSEL
VDDD2
VSSD4
LFCO2
LL3B
clock reference output, qualifier signal (2 times fLFCO
LFCO source select (LOW = LFCO selected) (1)
digital supply voltage 2 (+5 V)
)
digital ground 4 (0 V)
line-locked frequency control input signal 2(1)
line-locked clock output signal 3B (2 times fLFCO
)
Note
1. MS and LFCO2 functions are not tested. LFCO2 is a multiple of horizontal frequency.
May 1992
4
Philips Semiconductors
Product specification
Clock signal generator circuit for digital TV
systems (SCGC)
SAA7157
PIN CONFIGURATION
Fig.2 Pin configuration.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); ground pins as well as supply pins together
connected.
SYMBOL
PARAMETER
MIN.
−0.5
MAX. UNIT
VDDA
VDDD
Vdiff GND
VO
analog supply voltage (pin 5)
7.0
V
digital supply voltage (pins 8 and 17)
difference voltage VDDA − VDDD
output voltage (IOM = 20 mA)
−0.5
7.0
V
-
±100
VDDD
1.1
mV
V
−0.5
Ptot
total power dissipation (DIL20)
storage temperature range
0
W
°C
°C
V
Tstg
−65
150
70
Tamb
VESD
operating ambient temperature range
electrostatic handling(1) for all pins
0
-
tbf
Notes
1. Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
recommended to take normal handling precautions appropriate to “Handling MOS devices”.
May 1992
5
Philips Semiconductors
Product specification
Clock signal generator circuit for digital TV
systems (SCGC)
SAA7157
CHARACTERISTICS
VDDA = 4.5 to 5.5 V; VDDD = 4.5 to 5.5 V; fLFCO = 6.0 to 7.25 MHz and Tamb = 0 to 70 °C unless otherwise specified.
SYMBOL
VDDA
VDDD
IDDA
PARAMETER
CONDITIONS
MIN.
4.5
TYP.
5.0
MAX.
5.5
UNIT
analog supply voltage (pin 5)
digital supply voltage (pins 8 and 17)
analog supply current (pin 5)
digital supply current (I8 + I17)
power-on reset threshold voltage
V
V
4.5
3
5.0
−
5.5
9
mA
mA
V
IDDD
note 1
Fig.4
10
−
−
60
−
Vreset
3.5
Input LFCO (pin 11)
V11
Vi
DC input voltage
0
−
−
−
−
VDDA
VDDA
7.25
10
V
input signal (peak-to-peak value)
input frequency range
1
V
fLFCO
C11
6.0
−
MHz
pF
input capacitance
Inputs MS, CE, LFCOSEL and LFCO2 (pins 1, 2, 16 and 19); note 3
VIL
input voltage LOW
0
−
−
−
−
−
−
0.8
VDDD
7.25
150
10
V
VIH
input voltage HIGH
2.0
6.0
50
−
V
fLFCO2
ILI
input frequency range for LFCO2
input leakage current
MHz
µA
µA
pF
LFCOSEL
others
CI
input capacitance
−
5
Output RESN (pin 12)
VOL
VOH
td
output voltage LOW
IO L = 2 mA
0
−
−
−
0.4
V
output voltage HIGH
RESN delay time
IOH = −0.5 mA
C3 = 0.1 µF; Fig.4
2.4
20
VDDD
200
V
ms
Output CREF (pin 15)
VOL
VOH
fCREF
CL
output voltage LOW
IO L = 2 mA
IOH = −0.5 mA
Fig.3
0
−
0.6
V
output voltage HIGH
output frequency CREF
output load capacitance
set-up time
2.4
−
−
VDDD
V
2 fLFCO(2)
MHz
pF
ns
ns
15
12
4
−
−
−
40
−
tSU
Fig.3; note 1
Fig.3; note 1
tHD
hold time
−
May 1992
6
Philips Semiconductors
Product specification
Clock signal generator circuit for digital TV
systems (SCGC)
SAA7157
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Output signals LL1.5A, LL1.5B, LL3A and LL3B (pins 7, 10, 14, and 20); note 3
VOL
VOH
tcomp
fLL
output voltage LOW
output voltage HIGH
composite rise time
IO L = 2 mA
0
-
-
-
0.6
V
V
IOH = −0.5 mA
2.6
VDDD
8
Fig.3; notes 1 and 2 -
ns
output frequency LL1.5A
output frequency LL1.5B
output frequency LL3A
output frequency LL3B
rise and fall times
Fig.3
-
-
-
-
-
4 fLFCO(2)
4 fLFCO(2)
2 fLFCO(2)
2 fLFCO(2)
-
MHz
MHz
MHz
MHz
ns
tr, tf
tLL
note 1; Fig.3
5
duty factor LL1.5A, LL1.5B, LL3A
and LL3B (mean values)
note 1; Fig.3;
at 1.5 V level
43
50
57
%
Notes
1. fLFCO = 7.0 MHz and output load 40 pF (Fig.3). VSSA and VSSD short connected together.
2. tcomp is the rise time from LOW of all clocks to HIGH of all clocks (Fig.3) including rise time, skew and jitter
components. Measurements taken between 0.6 V and 2.6 V. Skew between two LLx clocks will not deviate more
than ±2 ns if output loads are matched within 20%.
3. MS and LFCO2 functions not tested.
2.4 V
0.6 V
CREF
t
t
t
SU
t
HD
HD
t
LL1.5
t
LL1.5H
LL1.5L
2.6 V
1.5 V
0.6 V
LL1.5A
LL1.5B
t
t
f
r
t
LL3
t
t
LL3L
LL3H
2.6 V
1.5 V
0.6 V
LL3A
LL3B
t
t
f
t
r
comp
MEH456
Fig.3 Output timing.
7
May 1992
Philips Semiconductors
Product specification
Clock signal generator circuit for digital TV
systems (SCGC)
SAA7157
+3.5 V
V
V
DDA
DDD
0 V
oscillation disturbed
power-on
LFCO
RESN
oscillation
t
t
d
d
normal
operation
normal
operation
LL1.5A
LL1.5B
LL3A
LL3B
MEH457
PLL lock-on
power failure
starts a new
clock HIGH
during
reset procedure
internal reset
reset time
Fig.4 Reset procedure.
V
V
DDD
DDD
7
10
14
15
20
1
2
16
19
LL1.5A
LL1.5B
LL3A
LL3B
CREF
MS
CE
LFCOSEL
LFCO2
V
V
V
SSD
SSD
DDD
11
12
LFCO
RESN
V
MEH468
SSD
Fig.5 Internal circuit.
8
May 1992
Philips Semiconductors
Product specification
Clock signal generator circuit for digital TV
systems (SCGC)
SAA7157
PACKAGE OUTLINE
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
M
H
20
11
pin 1 index
E
1
10
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
(1)
(1)
Z
1
2
UNIT
mm
b
b
c
D
E
e
e
1
L
M
M
H
w
1
E
max.
min.
max.
max.
1.73
1.30
0.53
0.38
0.36
0.23
26.92
26.54
6.40
6.22
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.10
7.62
0.30
0.254
0.01
2.0
0.068
0.051
0.021
0.015
0.014
0.009
1.060
1.045
0.25
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.020
0.13
0.078
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
92-11-17
95-05-24
SOT146-1
SC603
May 1992
9
Philips Semiconductors
Product specification
Clock signal generator circuit for digital TV
systems (SCGC)
SAA7157
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
y
H
E
v
M
A
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.30
0.10
2.45
2.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
mm
2.65
0.25
0.01
1.27
0.050
1.4
0.25 0.25
0.01
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.51
0.014 0.009 0.49
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches 0.10
0.055
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
95-01-24
97-05-22
SOT163-1
075E04
MS-013AC
May 1992
10
Philips Semiconductors
Product specification
Clock signal generator circuit for digital TV
systems (SCGC)
SAA7157
method. Typical reflow temperatures range from
215 to 250 °C.
SOLDERING
Introduction
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
WAVE SOLDERING
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
• The longitudinal axis of the package footprint must be
DIP
parallel to the solder flow.
• The package footprint must incorporate solder thieves at
the downstream end.
SOLDERING BY DIPPING OR BY WAVE
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg max). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
REPAIRING SOLDERED JOINTS
REPAIRING SOLDERED JOINTS
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
SO
REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
May 1992
11
Philips Semiconductors
Product specification
Clock signal generator circuit for digital TV
systems (SCGC)
SAA7157
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
May 1992
12
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