SAA7160E_技术文档

SAA7160

PCI Express based audio and video bridge

Rev. 01 — 25 February 2008

Product data sheet

1. General description

The SAA7160E and the SAA7160ET are PCI Express based audio and video capture

bridges. Both devices provide ports for capturing video streams, transport streams,

program streams and audio streams with audio functionality like I²S-bus inputs. The

bridges provide audio and video capture function as required for PCI Express applications

like Microsoft ‘multimedia center’.

The target is to cover a range of performance applications like personal video recording

and PC TV cards.

The SAA7160E and the SAA7160ET are highly integrated circuits for TV insertion inside

PC systems. Additional high-speed programming ports enable high integrated system

solutions for multimedia applications.

2. Features

2.1 PCI Express interface SAA7160E and SAA7160ET

I Compliant to PCI Express Base Speciﬁcation 1.0a

I Native PCI Express

N 64-bit address support

N MSI and INT_A message support

I The PCI Express circuit supports isochronous data trafﬁc intended for uninterrupted

transfer of streaming data like video streaming

N x1 PCI Express endpoint device (2.5 Gbit/s)

N Low jitter and bit error rate

I Type 0 conﬁguration space header

N Single BAR; conﬁgurable address range of 17 bits, 18 bits, 19 bits or 20 bits

dependent on application requirements

I DMA write support

N 12 DMA write channels for AV streaming

N Managing up to 8 software buffers per DMA channel

N Buffer size of 2 MB extendable to 4 MB (e.g. HDTV)

N Round-robin arbitration between DMAs

Support overﬂow recovery if PCI Express bandwidth is not granted in the required

amount

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

I DMA read support

N Autonomous address translation on PCI Express bus

N One DMA read channel for reading from page table(s) in system memory

I PCI Express capabilities

N 128 B write packet size and 64 B read packet size

N MSI support

N INT_A emulation

2.2 Digital interfaces SAA7160E

I Digital video input ports of 60 pins usable for maximum clock rates up to 75 MHz

N Six independent standard TV (ITU-R BT.656) 8-bit or 10-bit wide input streams

(27 MHz)

or

N Two standard TV 20-bit wide input streams

or

N Four TS or PS 8-bit wide input streams (13.5 MHz to 54 MHz) and two independent

standard TV (ITU-R BT.656) 8-bit or 10-bit wide input streams

or

N One HDTV 20-bit wide input stream (75 MHz)

2.3 Digital interfaces SAA7160ET

I Digital video input ports of 20 pins usable for maximum clock rates up to 75 MHz

N Two independent standard TV (ITU-R BT.656) 8-bit or 10-bit wide input streams

(27 MHz)

or

N Two TS or PS 8-bit wide input streams (13.5 MHz to 54 MHz)

or

N One TS or PS 8-bit wide input stream (13.5 MHz to 54 MHz) and one independent

standard TV (ITU-R BT.656) 8-bit or 10-bit wide input stream

or

N One HDTV 20-bit wide input stream (75 MHz)

2.4 Digital peripheral audio interfaces SAA7160E and SAA7160ET

I Two independent I²S-bus input channels supporting 32 kHz, 44.1 kHz or 48 kHz

2.5 Peripheral programming ports SAA7160E

I Two I²C-bus interfaces

N I²C-bus master port to program other peripheral devices

N Support register access with 100 kHz and 400 kHz bit rate

N I²C-bus slave port, usable to support a programming interface for application

systems

I One SPI master interface for controlling external peripherals

I PHI; this is an 16-bit wide interface for fast access to microcontroller

N Supports 8-bit data and 16-bit address interface

SAA7160_1

Product data sheet

Rev. 01 — 25 February 2008

2 of 57

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

I 28 GPIO pins for general I/O purposes, e.g. usable for interrupt input and chip select

functions

2.6 Peripheral programming ports SAA7160ET

I Two I²C-bus interfaces

N I²C-bus master port to program other peripheral devices

N Support register access with 100 kHz and 400 kHz bit rate

N I²C-bus slave port, usable to support a programming interface for application

systems

I One SPI master interface for controlling external peripherals

I 13 GPIO pins for general I/O purposes, e.g. usable for interrupt input and chip select

functions

2.7 General features SAA7160E and SAA7160ET

I Boundary scan test circuit according to ‘IEEE Std. 1149.1’

3. Ordering information

Table 1.

Ordering information

Type number Package

Name

Description

Version

SAA7160E

LBGA196 plastic low proﬁle ball grid array package; 196 balls; body 15 × 15 × 1 mm

TFBGA88 plastic thin ﬁne-pitch ball grid array package; 88 balls; body 7 × 7 × 0.8 mm

SOT879-1

SOT951-1

SAA7160ET

SAA7160_1

Product data sheet

Rev. 01 — 25 February 2008

3 of 57

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

4. Block diagram

transceiver

clock

receiver

PHY

(physical)

CGU

CONFIG

SPACE

GREG

PCIe CORE

MMU

GPIO

PHI

GPIO

BUFFER

AND

CONCENTRATOR

PHI

SPI

ARBITER

SPI

MSI

SDA_A

SCL_A

2

I C_A

DMA

2

I C_B

SCL_B

SDA_B

BOOT

AV INPUT

(2 × VI, 4 × FGPI, 2 × AI)

DCSN

2

port 1

port 3

port 5

I S-bus

port B

2

I S-bus

port A

port 2 port 4

port 6

001aag982

Fig 1. Block diagram of SAA7160

SAA7160_1

Product data sheet

Rev. 01 — 25 February 2008

4 of 57

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

5. Pinning information

5.1 SAA7160E package LBGA196

5.1.1 Pinning

SAA7160E

ball A1

index area

2

4

6

8

10

12

14

1

3

5

7

9

11

13

A

B

C

D

E

F

G

H

J

K

L

M

N

P

008aaa085

Transparent top view

Fig 2. Pin conﬁguration for LBGA196

1

2

3

4

5

6

7

8

9

10

11

12

13

14

P6_VS

_SOP

P1_4

P1_5

P1_6

P1_7

P1_CLK

P5_3

P4_HS

P5_6

P4_CLK

P4_4

P5_CLK

P5_HS

P4_1

P4_0

P6_HS

A

B

C

P4_VS

_SOP

P1_1

P1_2

P1_3

P1_0

P1_HS

P5_2

P5_5

P4_7

P5_0

P4_5

P5_4

P5_7

P5_1

P4_6

P4_2

P6_0

P6_VAL

P6_1

P6_CLK

P6_2

P2_VS

_SOP

P1_VS

_SOP

P5_VS

_SOP

P2_HS

P4_3

P2_CLK

P2_5

P2_7

P2_4

D

E

P2_6

P2_3

PHI_7

PHI_8

PHI_RDY_0 PHI_RDN

PHI_WRN

GPIO_17

PHI_15

GPIO_16 PHI_RDY_1

P6_3

P6_4

P6_6

P6_5

P6_7

V

DDDI1

(1V25)

DDDE3

(3V3)

DDDE3

(3V3)

PHI_14

PHI_12

PHI_13

PHI_10

PHI_6

P5_VAL

V

DDDI1

(1V25)

F

G

H

J

P2_2

P2_1

P2_0

PHI_4

PHI_5

PHI_3

PHI_1

PHI_0

GPIO_0

V

PHI_11

PHI_9

P4_VAL

P2_VAL

P1_VAL

SS

V

DDDE1

(3V3)

DDDE2

(3V3)

V

I2S_SCK_B I2S_SD1_B I2S_WS_B

P3_VS

I2S_SD1_A

I2S_WS_A I2S_SD0_A

SS

V

(1V25)

DDDE1

(3V3)

DDDI2

P3_VAL

P3_HS

P3_6

I2S_SD0_B

V

PHI_ALE PHI_RDY_3 P1_2_VS I2S_SCK_A

SS

_SOP

V

/

PHI_RDY_2 P1_2_HS

DDDI(1V25)

TEST

P3_CLK

P3_7

PHI_2

P4_5_VS

GPIO_3

GPIO_5

P1_2_FRE

P4_5_FRE

GPIO_2

SS

V

DDDI2

(1V25)

DDD(PCI0)

(1V0)

DDD(PCI1)

(1V0)

DDD(PCI0)

(1V25)

DDDE2

(3V3)

K

L

P3_5

P3_2

P3_4

GPIO_6

TEST1

P4_5_HS

GPIO_13

V

DDA(PCI0)

(3V3)

DDA(PCI1)

(3V3)

DDD(PCI1)

(1V25)

P3_3

P3_1

GPIO_29

GPIO_26

GPIO_21

GPIO_10

M

N

P

P3_0

SCL_A

SDA_A

SCL_B

SDA_B

TCK

TMS

TDO

TDI

TRSTN

GPIO_1

PCI_PVT

PCI_RESN

BOOT_1

BOOT_0

SPI_SL_MA GPIO_28

SPI_MA_SL GPIO_23

GPIO_18

GPIO_20

GPIO_22

GPIO_14

GPIO_15

GPIO_19

GPIO_9

GPIO_11

GPIO_12

GPIO_4

GPIO_7

PCI_REF

CLKP

PCI_REF

CLKN

V

SS

PCI_PER

_P0

PCI_PER

_N0

PCI_PET

_P0

PCI_PET

_N0

V

SS

GPIO_27

SPI_CLK

GPIO_8

008aaa087

Fig 3. Pin conﬁguration (LBGA196 top view) for SAA7160E

SAA7160_1

Product data sheet

Rev. 01 — 25 February 2008

5 of 57

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

5.1.2 Pin description

Table 2.

Symbol

SCL_A

Description of functional pins

N1

P1

Type^[1]Description

IO

I²C-bus clock of ﬁrst I²C-bus interface

I²C-bus data of ﬁrst I²C-bus interface

SDA_A

I2S_SD0_A

G14 IO

I²S-bus port A: digital audio input signal for

• I2S_SD serial data line of Inter IC Sound bus serial interconnect format

I²S-bus port A: digital audio input signal for

I2S_WS_A

I2S_SCK_A

I2S_SD1_A

P1_0

G13 IO

• I2S_WS word select line of Inter IC Sound bus serial interconnect format

I²S-bus port A: digital audio input signal for

H14

G12

C3

I

• I2S_SCK bit clock of Inter IC Sound bus serial interconnect format

I²S-bus port A: digital audio input signal for

I

• I2S_SD serial data line of Inter IC Sound bus serial interconnect format

1. digital input signal of VIP_1, FGPI_2 or FGPI_3 for parallel video data modes

ID

–

STV YUV[7:0] bit 0

STV YUV[9:0] bit 2

HDTV Y[9:0] bit 2

2. digital input signal of FGPI_2 or FGPI_3 for parallel

–

transport stream data of TS1[7:0] bit 0

program stream data of PS1[7:0] bit 0

P1_1

P1_2

P1_3

B1

B2

B3

ID

1. digital input signal of VIP_1, FGPI_2 or FGPI_3 for parallel video data modes

–

STV YUV[7:0] bit 1

STV YUV[9:0] bit 3

HDTV Y[9:0] bit 3

2. digital input signal of FGPI_2 or FGPI_3 for parallel

–

transport stream data of TS1[7:0] bit 1

program stream data of PS1[7:0] bit 1

1. digital input signal of VIP_1, FGPI_2 or FGPI_3 for parallel video data modes

–

STV YUV[7:0] bit 2

STV YUV[9:0] bit 4

HDTV Y[9:0] bit 4

2. digital input signal of FGPI_2 or FGPI_3 for parallel

–

transport stream data of TS1[7:0] bit 2

program stream data of PS1[7:0] bit 2

1. digital input signal of VIP_1, FGPI_2 or FGPI_3 for parallel video data modes

–

STV YUV[7:0] bit 3

STV YUV[9:0] bit 5

HDTV Y[9:0] bit 5

2. digital input signal of FGPI_2 or FGPI_3 for parallel

–

transport stream data of TS1[7:0] bit 3

program stream data of PS1[7:0] bit 3

SAA7160_1

Product data sheet

Rev. 01 — 25 February 2008

6 of 57

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

Table 2.

Symbol

P1_4

Description of functional pins …continued

Type^[1]Description

A1

ID

1. digital input signal of VIP_1, FGPI_2 or FGPI_3 for parallel video data modes

–

STV YUV[7:0] bit 4

STV YUV[9:0] bit 6

HDTV Y[9:0] bit 6

2. digital input signal of FGPI_2 or FGPI_3 for parallel

–

transport stream data of TS1[7:0] bit 4

program stream data of PS1[7:0] bit 4

P1_5

P1_6

P1_7

A2

A3

A4

A5

1. digital input signal of VIP_1, FGPI_2 or FGPI_3 for parallel video data modes

–

STV YUV[7:0] bit 5

STV YUV[9:0] bit 7

HDTV Y[9:0] bit 7

2. digital input signal of FGPI_2 or FGPI_3 for parallel

–

transport stream data of TS1[7:0] bit 5

program stream data of PS1[7:0] bit 5

1. digital input signal of VIP_1, FGPI_2 or FGPI_3 for parallel video data modes

–

STV YUV[7:0] bit 6

STV YUV[9:0] bit 8

HDTV Y[9:0] bit 8

2. digital input signal of FGPI_2 or FGPI_3 for parallel

–

transport stream data of TS1[7:0] bit 6

program stream data of PS1[7:0] bit 6

1. digital input signal of VIP_1, FGPI_2 or FGPI_3 for parallel video data modes

–

STV YUV[7:0] bit 7

STV YUV[9:0] bit 9

HDTV Y[9:0] bit 9

2. digital input signal of FGPI_2 or FGPI_3 for parallel

–

transport stream data of TS1[7:0] bit 7

program stream data of PS1[7:0] bit 7

P1_CLK

P1_HS

1. digital input signal of FGPI_2 or FGPI_3 for parallel

–

transport stream clock of TS1

program stream clock of PS1

2. digital input signal of VIP_1, FGPI_2 or FGPI_3 for

clock signal of parallel video data

–

B4

ID

digital input signal of VIP_1, FGPI_2 or FGPI_3 for

• horizontal synchronization reference in 8-bit STV mode

• parallel video data mode STV YUV[9:0] bit 0

• parallel video data mode HDTV Y[9:0] bit 0

horizontal synchronization reference for HD stream from video port 1 and port 2

vertical synchronization reference for HD stream from video port 1 and port 2

ﬁeld indication reference for HD stream from video port 1 and port 2

P1_2_HS

P1_2_VS

P1_2_FRE

J12

H13 ID

J14 ID

SAA7160_1

Product data sheet

Rev. 01 — 25 February 2008

7 of 57

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

Table 2.

Description of functional pins …continued

Symbol

Type^[1]Description

P1_VS_SOP

C4

ID

1. digital input signal of VIP_1, FGPI_2 or FGPI_3 for

–

parallel video data mode STV YUV[9:0] bit 1

parallel video data mode HDTV Y[9:0] bit 1

vertical synchronization reference in 8-bit STV mode

2. digital input signal ‘start of package’ of FGPI_2 or FGPI_3 for parallel

–

program stream data of PS1

transport stream data of TS1

P1_VAL

P2_0

F14

F3

ID

digital input control signal ‘valid data’ of FGPI_2 or FGPI_3 for parallel

• transport stream data of TS1

• program stream data of PS1

If this pin is unused it is necessary to connect the pin to 3.3 V supply voltage.

1. digital input signal of VIP_1, FGPI_2 or FGPI_3 for parallel video data modes

–

STV YUV[7:0] bit 0

STV YUV[9:0] bit 2

HDTV UV[9:0] bit 2

2. digital input signal of FGPI_2 or FGPI_3 for parallel

–

transport stream data of TS2[7:0] bit 0

program stream data of PS2[7:0] bit 0

P2_1

P2_2

P2_3

F2

F1

E3

ID

1. digital input signal of VIP_1, FGPI_2 or FGPI_3 for parallel video data modes

–

STV YUV[7:0] bit 1

STV YUV[9:0] bit 3

HDTV UV[9:0] bit 3

2. digital input signal of FGPI_2 or FGPI_3 for parallel

–

transport stream data of TS2[7:0] bit 1

program stream data of PS2[7:0] bit 1

1. digital input signal of VIP_1, FGPI_2 or FGPI_3 for parallel video data modes

–

STV YUV[7:0] bit 2

STV YUV[9:0] bit 4

HDTV UV[9:0] bit 4

2. digital input signal of FGPI_2 or FGPI_3 for parallel

–

transport stream data of TS2[7:0] bit 2

program stream data of PS2[7:0] bit 2

1. digital input signal of VIP_1, FGPI_2 or FGPI_3 for parallel video data modes

–

STV YUV[7:0] bit 3

STV YUV[9:0] bit 5

HDTV UV[9:0] bit 5

2. digital input signal of FGPI_2 or FGPI_3 for parallel

–

transport stream data of TS2[7:0] bit 3

program stream data of PS2[7:0] bit 3

SAA7160_1

Product data sheet

Rev. 01 — 25 February 2008

8 of 57

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

Table 2.

Symbol

P2_4

Description of functional pins …continued

Type^[1]Description

E2

ID

1. digital input signal of VIP_1, FGPI_2 or FGPI_3 for parallel video data modes

–

STV YUV[7:0] bit 4

STV YUV[9:0] bit 6

HDTV UV[9:0] bit 6

2. digital input signal of FGPI_2 or FGPI_3 for parallel

–

transport stream data of TS2[7:0] bit 4

program stream data of PS2[7:0] bit 4

P2_5

P2_6

P2_7

E1

D3

D2

1. digital input signal of VIP_1, FGPI_2 or FGPI_3 for parallel video data modes

–

STV YUV[7:0] bit 5

STV YUV[9:0] bit 7

HDTV UV[9:0] bit 7

2. digital input signal of FGPI_2 or FGPI_3 for parallel

–

transport stream data of TS2[7:0] bit 5

program stream data of PS2[7:0] bit 5

1. digital input signal of VIP_1, FGPI_2 or FGPI_3 for parallel video data modes

–

STV YUV[7:0] bit 6

STV YUV[9:0] bit 8

HDTV UV[9:0] bit 8

2. digital input signal of FGPI_2 or FGPI_3 for parallel

–

transport stream data of TS2[7:0] bit 6

program stream data of PS2[7:0] bit 6

1. digital input signal of VIP_1, FGPI_2 or FGPI_3 for parallel video data modes

–

STV YUV[7:0] bit 7

STV YUV[9:0] bit 9

HDTV UV[9:0] bit 9

2. digital input signal of FGPI_2 or FGPI_3 for parallel

–

transport stream data of TS2[7:0] bit 7

program stream data of PS2[7:0] bit 7

P2_CLK

P2_HS

D1

C1

ID

1. digital input signal of FGPI_2 or FGPI_3 for parallel

–

transport stream clock of TS2

program stream clock of PS2

2. digital input signal of VIP_1, FGPI_2 or FGPI_3 for

clock signal of parallel video data

digital input signal of VIP_1, FGPI_2 or FGPI_3 for

• horizontal synchronization of digital video port

• parallel video data mode STV YUV[9:0] bit 0

• parallel video data mode HDTV UV[9:0] bit 0

SAA7160_1

Product data sheet

Rev. 01 — 25 February 2008

9 of 57

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

Table 2.

Description of functional pins …continued

Symbol

Type^[1]Description

P2_VS_SOP

C2

ID

1. digital input signal of VIP_1, FGPI_2 or FGPI_3 for

–

parallel video data mode STV YUV[9:0] bit 1

parallel video data mode HDTV UV[9:0] bit 1

vertical synchronization reference in 8-bit STV mode

2. digital input signal ‘start of package’ of FGPI_2 or FGPI_3 for parallel

–

transport stream data of TS2

program stream data of PS2

P2_VAL

P3_0

F13

M1

ID

digital input control signal ‘valid data’ of FGPI_2 or FGPI_3 for parallel

• transport stream data of TS2

• program stream data of PS2

If this pin is unused it is necessary to connect the pin to 3.3 V supply voltage.

1. digital input signal of VIP_1, FGPI_2 or FGPI_3 for parallel video data modes

–

STV YUV[7:0] bit 0

STV YUV[9:0] bit 2

HDTV UV[9:0] bit 2

2. digital input signal of FGPI_2 or FGPI_3 for parallel

–

transport stream data of TS3[7:0] bit 0

program stream data of PS3[7:0] bit 0

P3_1

P3_2

P3_3

L3

L2

L1

ID

1. digital input signal of VIP_1, FGPI_2 or FGPI_3 for parallel video data modes

–

STV YUV[7:0] bit 1

STV YUV[9:0] bit 3

HDTV UV[9:0] bit 3

2. digital input signal of FGPI_2 or FGPI_3 for parallel

–

transport stream data of TS3[7:0] bit 1

program stream data of PS3[7:0] bit 1

1. digital input signal of VIP_1, FGPI_2 or FGPI_3 for parallel video data modes

–

STV YUV[7:0] bit 2

STV YUV[9:0] bit 4

HDTV UV[9:0] bit 4

2. digital input signal of FGPI_2 or FGPI_3 for parallel

–

transport stream data of TS3[7:0] bit 2

program stream data of PS3[7:0] bit 2

1. digital input signal of VIP_1, FGPI_2 or FGPI_3 for parallel video data modes

–

STV YUV[7:0] bit 3

STV YUV[9:0] bit 5

HDTV UV[9:0] bit 5

2. digital input signal of FGPI_2 or FGPI_3 for parallel

–

transport stream data of TS3[7:0] bit 3

program stream data of PS3[7:0] bit 3

SAA7160_1

Product data sheet

Rev. 01 — 25 February 2008

10 of 57

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

Table 2.

Symbol

P3_4

Description of functional pins …continued

Type^[1]Description

K3

ID

1. digital input signal of VIP_1, FGPI_2 or FGPI_3 for parallel video data modes

–

STV YUV[7:0] bit 4

STV YUV[9:0] bit 6

HDTV UV[9:0] bit 6

2. digital input signal of FGPI_2 or FGPI_3 for parallel

–

transport stream data of TS3[7:0] bit 4

program stream data of PS3[7:0] bit 4

P3_5

P3_6

P3_7

K2

K1

J3

1. digital input signal of VIP_1, FGPI_2 or FGPI_3 for parallel video data modes

–

STV YUV[7:0] bit 5

STV YUV[9:0] bit 7

HDTV UV[9:0] bit 7

2. digital input signal of FGPI_2 or FGPI_3 for parallel

–

transport stream data of TS3[7:0] bit 5

program stream data of PS3[7:0] bit 5

1. digital input signal of VIP_1, FGPI_2 or FGPI_3 for parallel video data modes

–

STV YUV[7:0] bit 6

STV YUV[9:0] bit 8

HDTV UV[9:0] bit 8

2. digital input signal of FGPI_2 or FGPI_3 for parallel

–

transport stream data of TS3[7:0] bit 6

program stream data of PS3[7:0] bit 6

1. digital input signal of VIP_1, FGPI_2 or FGPI_3 for parallel video data modes

–

STV YUV[7:0] bit 7

STV YUV[9:0] bit 9

HDTV UV[9:0] bit 9

2. digital input signal of FGPI_2 or FGPI_3 for parallel

–

transport stream data of TS3[7:0] bit 7

program stream data of PS3[7:0] bit 7

P3_CLK

P3_HS

J2

J1

ID

1. digital input signal of FGPI_2 or FGPI_3 for parallel

–

transport stream clock of TS3

program stream clock of PS3

2. digital input signal of VIP_1, FGPI_2 or FGPI_3 for

clock signal of parallel video data

–

digital input signal of VIP_1, FGPI_2 or FGPI_3 for

• parallel video data mode STV YUV[9:0] bit 0

• parallel video data mode HDTV UV[9:0] bit 0

• horizontal synchronization reference in 8-bit STV mode

SAA7160_1

Product data sheet

Rev. 01 — 25 February 2008

11 of 57

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

Table 2.

Description of functional pins …continued

Symbol

Type^[1]Description

P3_VS_SOP

H2

ID

1. digital input signal of VIP_1, FGPI_2 or FGPI_3 for

–

parallel video data mode STV YUV[9:0] bit 1

parallel video data mode HDTV UV[9:0] bit 1

vertical synchronization reference in 8-bit STV mode

2. digital input signal ‘start of package’ of FGPI_2 or FGPI_3 for parallel

–

transport stream data of TS3

program stream data of PS3

P3_VAL

P4_0

H1

ID

digital input control signal ‘valid data’ of FGPI_2 or FGPI_3 for parallel

• transport stream data of TS3

• program stream data of PS3

If this pin is unused it is necessary to connect the pin to 3.3 V supply voltage.

A12

1. digital input signal of VIP_0, FGPI_0 or FGPI_1 for parallel video data modes

–

STV YUV[7:0] bit 0

STV YUV[9:0] bit 2

HDTV Y[9:0] bit 2

2. digital input signal of FGPI_0 or FGPI_1 for parallel

–

transport stream data of TS4[7:0] bit 0

program stream data of PS4[7:0] bit 0

P4_1

P4_2

P4_3

A11

ID

1. digital input signal of VIP_0, FGPI_0 or FGPI_1 for parallel video data modes

–

STV YUV[7:0] bit 1

STV YUV[9:0] bit 3

HDTV Y[9:0] bit 3

2. digital input signal of FGPI_0 or FGPI_1 for parallel

–

transport stream data of TS4[7:0] bit 1

program stream data of PS4[7:0] bit 1

B12

ID

1. digital input signal of VIP_0, FGPI_0 or FGPI_1 for parallel video data modes

–

STV YUV[7:0] bit 2

STV YUV[9:0] bit 4

HDTV Y[9:0] bit 4

2. digital input signal of FGPI_0 or FGPI_1 for parallel

–

transport stream data of TS4[7:0] bit 2

program stream data of PS4[7:0] bit 2

C11 ID

1. digital input signal of VIP_0, FGPI_0 or FGPI_1 for parallel video data modes

–

STV YUV[7:0] bit 3

STV YUV[9:0] bit 5

HDTV Y[9:0] bit 5

2. digital input signal of FGPI_0 or FGPI_1 for parallel

–

transport stream data of TS4[7:0] bit 3

program stream data of PS4[7:0] bit 3

SAA7160_1

Product data sheet

Rev. 01 — 25 February 2008

12 of 57

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

Table 2.

Symbol

P4_4

Description of functional pins …continued

Type^[1]Description

A8

ID

1. digital input signal of VIP_0, FGPI_0 or FGPI_1 for parallel video data modes

–

STV YUV[7:0] bit 4

STV YUV[9:0] bit 6

HDTV Y[9:0] bit 6

2. digital input signal of FGPI_0 or FGPI_1 for parallel

–

transport stream data of TS4[7:0] bit 4

program stream data of PS4[7:0] bit 4

P4_5

P4_6

P4_7

B8

1. digital input signal of VIP_0, FGPI_0 or FGPI_1 for parallel video data modes

–

STV YUV[7:0] bit 5

STV YUV[9:0] bit 7

HDTV Y[9:0] bit 7

2. digital input signal of FGPI_0 or FGPI_1 for parallel

–

transport stream data of TS4[7:0] bit 5

program stream data of PS4[7:0] bit 5

B10

1. digital input signal of VIP_0, FGPI_0 or FGPI_1 for parallel video data modes

–

STV YUV[7:0] bit 6

STV YUV[9:0] bit 8

HDTV Y[9:0] bit 8

2. digital input signal of FGPI_0 or FGPI_1 for parallel

–

transport stream data of TS4[7:0] bit 6

program stream data of PS4[7:0] bit 6

B7

1. digital input signal of VIP_0, FGPI_0 or FGPI_1 for parallel video data modes

–

STV YUV[7:0] bit 7

STV YUV[9:0] bit 9

HDTV Y[9:0] bit 9

2. digital input signal of FGPI_0 or FGPI_1 for parallel

–

transport stream data of TS4[7:0] bit 7

program stream data of PS4[7:0] bit 7

P4_CLK

P4_HS

A7

B6

ID

1. digital input signal of FGPI_0 or FGPI_1 for parallel

–

transport stream clock of TS4

program stream clock of PS4

2. digital input signal of VIP_0, FGPI_0 or FGPI_1 for

clock signal of parallel video data

–

digital input signal of VIP_0, FGPI_0 or FGPI_1 for

• horizontal synchronization reference in 8-bit STV mode

• parallel video data mode STV YUV[9:0] bit 0

• parallel video data mode HDTV Y[9:0] bit 0

P4_5_HS

P4_5_VS

P4_5_FRE

K12

J13

K14

ID

horizontal synchronization reference for HD stream from video port 4 and port 5

vertical synchronization reference for HD stream from video port 4 and port 5

ﬁeld indication reference for HD stream from video port 4 and port 5

SAA7160_1

Product data sheet

Rev. 01 — 25 February 2008

13 of 57

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

Table 2.

Description of functional pins …continued

Symbol

Type^[1]Description

P4_VS_SOP

B11

ID

1. digital input signal of VIP_0, FGPI_0 or FGPI_1 for

–

parallel video data mode STV YUV[9:0] bit 1

parallel video data mode HDTV Y[9:0] bit 1

vertical synchronization reference in 8-bit STV mode

2. digital input signal ‘start of package’ of FGPI_0 or FGPI_1 for parallel

–

transport stream data of TS4

program stream data of PS4

P4_VAL

P5_0

F12

C7

ID

digital input control signal ‘valid data’ of FGPI_0 or FGPI_1 for parallel

• transport stream data of TS4

• program stream data of PS4

If this pin is unused it is necessary to connect the pin to 3.3 V supply voltage.

1. digital input signal of VIP_0, FGPI_0 or FGPI_1 for parallel video data modes

–

STV YUV[7:0] bit 0

STV YUV[9:0] bit 2

HDTV UV[9:0] bit 2

2. digital input signal of FGPI_0 or FGPI_1 for parallel

–

transport stream data of TS5[7:0] bit 0

program stream data of PS5[7:0] bit 0

P5_1

P5_2

P5_3

C9

B5

A6

ID

1. digital input signal of VIP_0, FGPI_0 or FGPI_1 for parallel video data modes

–

STV YUV[7:0] bit 1

STV YUV[9:0] bit 3

HDTV UV[9:0] bit 3

2. digital input signal of FGPI_0 or FGPI_1 for parallel

–

transport stream data of TS5[7:0] bit 1

program stream data of PS5[7:0] bit 1

1. digital input signal of VIP_0, FGPI_0 or FGPI_1 for parallel video data modes

–

STV YUV[7:0] bit 2

STV YUV[9:0] bit 4

HDTV UV[9:0] bit 4

2. digital input signal of FGPI_0 or FGPI_1 for parallel

–

transport stream data of TS5[7:0] bit 2

program stream data of PS5[7:0] bit 2

1. digital input signal of VIP_0, FGPI_0 or FGPI_1 for parallel video data modes

–

STV YUV[7:0] bit 3

STV YUV[9:0] bit 5

HDTV UV[9:0] bit 5

2. digital input signal of FGPI_0 or FGPI_1 for parallel

–

transport stream data of TS5[7:0] bit 3

program stream data of PS5[7:0] bit 3

SAA7160_1

Product data sheet

Rev. 01 — 25 February 2008

14 of 57

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

Table 2.

Symbol

P5_4

Description of functional pins …continued

Type^[1]Description

C8

ID

1. digital input signal of VIP_0, FGPI_0 or FGPI_1 for parallel video data modes

–

STV YUV[7:0] bit 4

STV YUV[9:0] bit 6

HDTV UV[9:0] bit 6

2. digital input signal of FGPI_0 or FGPI_1 for parallel

–

transport stream data of TS5[7:0] bit 4

program stream data of PS5[7:0] bit 4

P5_5

P5_6

P5_7

C5

C6

B9

1. digital input signal of VIP_0, FGPI_0 or FGPI_1 for parallel video data modes

–

STV YUV[7:0] bit 5

STV YUV[9:0] bit 7

HDTV UV[9:0] bit 7

2. digital input signal of FGPI_0 or FGPI_1 for parallel

–

transport stream data of TS5[7:0] bit 5

program stream data of PS5[7:0] bit 5

1. digital input signal of VIP_0, FGPI_0 or FGPI_1 for parallel video data modes

–

STV YUV[7:0] bit 6

STV YUV[9:0] bit 8

HDTV UV[9:0] bit 8

2. digital input signal of FGPI_0 or FGPI_1 for parallel

–

transport stream data of TS5[7:0] bit 6

program stream data of PS5[7:0] bit 6

1. digital input signal of VIP_0, FGPI_0 or FGPI_1 for parallel video data modes

–

STV YUV[7:0] bit 7

STV YUV[9:0] bit 9

HDTV UV[9:0] bit 9

2. digital input signal of FGPI_0 or FGPI_1 for parallel

–

transport stream data of TS5[7:0] bit 7

program stream data of PS5[7:0] bit 7

P5_CLK

P5_HS

A9

ID

1. digital input signal of FGPI_0 or FGPI_1 for parallel

–

transport stream clock for port TS5

program stream clock for port PS5

2. digital input signal of VIP_0, FGPI_0 or FGPI_1 for

clock signal of parallel video data

–

A10

digital input signal of VIP_0, FGPI_0 or FGPI_1 for

• horizontal synchronization reference in 8-bit STV mode

• parallel video data mode STV YUV[9:0] bit 0

• parallel video data mode HDTV UV[9:0] bit 0

SAA7160_1

Product data sheet

Rev. 01 — 25 February 2008

15 of 57

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

Table 2.

Description of functional pins …continued

Type^[1]Description

C10 ID 1. digital input signal of VIP_0, FGPI_0 or FGPI_1 for

Symbol

P5_VS_SOP

–

parallel video data mode STV YUV[9:0] bit 1

parallel video data mode HDTV UV[9:0] bit 1

vertical synchronization reference in 8-bit STV mode

2. digital input signal ‘start of package’ of FGPI_0 or FGPI_1 for parallel

–

transport stream data of TS5

program stream data of PS5

P5_VAL

P6_0

E12

ID

digital input control signal ‘valid data’ of FGPI_0 or FGPI_1 for parallel

• transport stream data of TS5

• program stream data of PS5

If this pin is unused it is necessary to connect the pin to 3.3 V supply voltage.

C12 ID

C13 ID

C14 ID

D12 ID

1. digital input signal of VIP_0, FGPI_0 or FGPI_1 for parallel video data modes

–

STV YUV[7:0] bit 0

STV YUV[9:0] bit 2

HDTV UV[9:0] bit 2

2. digital input signal of FGPI_0 or FGPI_1 for parallel

–

transport stream data of TS6[7:0] bit 0

program stream data of PS6[7:0] bit 0

P6_1

P6_2

P6_3

1. digital input signal of VIP_0, FGPI_0 or FGPI_1 for parallel video data modes

–

STV YUV[7:0] bit 1

STV YUV[9:0] bit 3

HDTV UV[9:0] bit 3

2. digital input signal of FGPI_0 or FGPI_1 for parallel

–

transport stream data of TS6[7:0] bit 1

program stream data of PS6[7:0] bit 1

1. digital input signal of VIP_0, FGPI_0 or FGPI_1 for parallel video data modes

–

STV YUV[7:0] bit 2

STV YUV[9:0] bit 4

HDTV UV[9:0] bit 4

2. digital input signal of FGPI_0 or FGPI_1 for parallel

–

transport stream data of TS6[7:0] bit 2

program stream data of PS6[7:0] bit 2

1. digital input signal of VIP_0, FGPI_0 or FGPI_1 for parallel video data modes

–

STV YUV[7:0] bit 3

STV YUV[9:0] bit 5

HDTV UV[9:0] bit 5

2. digital input signal of FGPI_0 or FGPI_1 for parallel

–

transport stream data of TS6[7:0] bit 3

program stream data of PS6[7:0] bit 3

SAA7160_1

Product data sheet

Rev. 01 — 25 February 2008

16 of 57

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

Table 2.

Symbol

P6_4

Description of functional pins …continued

Type^[1]Description

D13 ID

1. digital input signal of VIP_0, FGPI_0 or FGPI_1 for parallel video data modes

–

STV YUV[7:0] bit 4

STV YUV[9:0] bit 6

HDTV UV[9:0] bit 6

2. digital input signal of FGPI_0 or FGPI_1 for parallel

–

transport stream data of TS6[7:0] bit 4

program stream data of PS6[7:0] bit 4

P6_5

P6_6

P6_7

D14 ID

1. digital input signal of VIP_0, FGPI_0 or FGPI_1 for parallel video data modes

–

STV YUV[7:0] bit 5

STV YUV[9:0] bit 7

HDTV UV[9:0] bit 7

2. digital input signal of FGPI_0 or FGPI_1 for parallel

–

transport stream data of TS6[7:0] bit 5

program stream data of PS6[7:0] bit 5

E13

ID

1. digital input signal of VIP_0, FGPI_0 or FGPI_1 for parallel video data modes

–

STV YUV[7:0] bit 6

STV YUV[9:0] bit 8

HDTV UV[9:0] bit 8

2. digital input signal of FGPI_0 or FGPI_1 for parallel

–

transport stream data of TS6[7:0] bit 6

program stream data of PS6[7:0] bit 6

E14

ID

1. digital input signal of VIP_0, FGPI_0 or FGPI_1 for parallel video data modes

–

STV YUV[7:0] bit 7

STV YUV[9:0] bit 9

HDTV UV[9:0] bit 9

2. digital input signal of FGPI_0 or FGPI_1 for parallel

–

transport stream data of TS6[7:0] bit 7

program stream data of PS6[7:0] bit 7

P6_CLK

P6_HS

B14

A14

ID

1. digital input signal of FGPI_0 or FGPI_1 for parallel

–

transport stream clock of TS6

program stream clock of PS6

2. digital input signal of VIP_0, FGPI_0 or FGPI_1 for

clock signal for parallel video data modes

–

digital input signal of VIP_0, FGPI_0 or FGPI_1 for

• parallel video data mode STV YUV[9:0] bit 0

• parallel video data mode HDTV UV[9:0] bit 0

• horizontal synchronization reference in 8-bit STV mode

SAA7160_1

Product data sheet

Rev. 01 — 25 February 2008

17 of 57

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

Table 2.

Description of functional pins …continued

Symbol

Type^[1]Description

P6_VS_SOP

A13

ID 1. digital input signal of VIP_0, FGPI_0 or FGPI_1 for

–

parallel video data mode STV YUV[9:0] bit 1

parallel video data mode HDTV UV[9:0] bit 1

vertical synchronization reference in 8-bit STV mode

2. digital input signal ‘start of package’ of FGPI_0 or FGPI_1 for parallel

–

transport stream data of TS6

program stream data of PS6

P6_VAL

B13

ID

digital input control signal ‘valid data’ of FGPI_0 or FGPI_1 for parallel

• transport stream data of TS6

• program stream data of PS6

If this pin is unused it is necessary to connect the pin to 3.3 V supply voltage.

GPIO_0

GPIO_1

GPIO_2

GPIO_3

GPIO_4

GPIO_5

GPIO_6

GPIO_7

GPIO_8

GPIO_9

L4

IOU

GPIO: programming control port signal for

• general purpose input/output port 0

• external interrupt 0; interrupt edge sensitive with programmable edge polarity

M5

L14

K13

GPIO: programming control port signal for

• general purpose input/output port 1

• external interrupt 1; interrupt edge sensitive with programmable edge polarity

GPIO: programming control port signal for

• general purpose input/output port 2

• external interrupt 2; interrupt edge sensitive with programmable edge polarity

GPIO: programming control port signal for

• general purpose input/output port 3

• external interrupt 3; interrupt edge sensitive with programmable edge polarity

M14 IOU

GPIO: programming control port signal for

• general purpose input/output port 4

• external interrupt 4; interrupt edge sensitive with programmable edge polarity

L13

K10

IOU

GPIO: programming control port signal for

• general purpose input/output port 5

• external interrupt 5; interrupt edge sensitive with programmable edge polarity

GPIO: programming control port signal for

• general purpose input/output port 6

• external interrupt 6; interrupt edge sensitive with programmable edge polarity

N14 IOU

GPIO: programming control port signal for

• general purpose input/output port 7

• external interrupt 7; interrupt edge sensitive with programmable edge polarity

P14

IOU

GPIO: programming control port signal for

• general purpose input/output port 8

• external interrupt 8; interrupt edge sensitive with programmable edge polarity

M13 IOU

GPIO: programming control port signal for

• general purpose input/output port 9

• external interrupt 9; interrupt edge sensitive with programmable edge polarity

SAA7160_1

Product data sheet

Rev. 01 — 25 February 2008

18 of 57

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

Table 2.

Symbol

GPIO_10

Description of functional pins …continued

Type^[1]Description

IOU GPIO: programming control port signal for

• general purpose input/output port 10

L11

• external interrupt 10; interrupt edge sensitive with programmable edge polarity

GPIO_11

GPIO_12

GPIO_13

GPIO_14

GPIO_15

GPIO_16

GPIO_17

GPIO_18

GPIO_19

GPIO_20

GPIO_21

GPIO_22

GPIO_23

N13 IOU

GPIO: programming control port signal for

• general purpose input/output port 11

• external interrupt 11; interrupt edge sensitive with programmable edge polarity

P13

L12

IOU

GPIO: programming control port signal for

• general purpose input/output port 12

• external interrupt 12; interrupt edge sensitive with programmable edge polarity

GPIO: programming control port signal for

• general purpose input/output port 13

• external interrupt 13; interrupt edge sensitive with programmable edge polarity

M12 IOU

N12 IOU

D10 IOU

GPIO: programming control port signal for

• general purpose input/output port 14

• external interrupt 14; interrupt edge sensitive with programmable edge polarity

GPIO: programming control port signal for

• general purpose input/output port 15

• external interrupt 15; interrupt edge sensitive with programmable edge polarity

GPIO: programming control port signal for

• general purpose input/output port 16

• PHI chip select to other external devices (active LOW)

D9

IOU

GPIO: programming control port signal for

• general purpose input/output port 17

• PHI chip select to other external devices (active LOW)

M11 IOU

GPIO: programming control port signal for

• general purpose input/output port 18

• PHI chip select to other external devices (active LOW)

P12

IOU

GPIO: programming control port signal for

• general purpose input/output port 19

• PHI chip select to other external devices (active LOW)

N11 IOU

GPIO: programming control port signal for

• general purpose input/output port 20

• PHI chip select to other external devices (active LOW)

L10

P11

IOU

GPIO: programming control port signal for

• general purpose input/output port 21

• PHI chip select to other external devices (active LOW)

GPIO: programming control port signal for

• general purpose input/output port 22

• PHI chip select to other external devices (active LOW)

N10 IOU

GPIO: programming control port signal for

• general purpose input/output port 23

• PHI chip select to other external devices (active LOW)

SAA7160_1

Product data sheet

Rev. 01 — 25 February 2008

19 of 57

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

Table 2.

Symbol

GPIO_26

Description of functional pins …continued

Type^[1]Description

L9

IOU

GPIO: programming control port signal for

• general purpose input/output port 26

GPIO_27

GPIO_28

GPIO_29

BOOT_0

P10

IOU

GPIO: programming control port signal for

• general purpose input/output port 27

GPIO: programming control port signal for

• general purpose input/output port 28

GPIO: programming control port signal for

• general purpose input/output port 29

GPIO: programming control port signal for

• general purpose input/output port 30

• boot mode GPIO_[31:30] bit 0

M10 IOU

L8

IOU

N8

BOOT_1

PHI_0

PHI_1

PHI_2

PHI_3

PHI_4

PHI_5

PHI_6

PHI_7

PHI_8

M8

K4

J4

IOU

IO

GPIO: programming control port signal for

• general purpose input/output port 31

• boot mode GPIO_[31:30] bit 1

PHI signal for

• data input/output port bit 0

• Intel microcontroller multiplexed address output or data input port bit 0

PHI signal for

• data input/output port bit 1

• Intel microcontroller multiplexed address output or data input port bit 1

J5

PHI signal for

• data input/output port bit 2

• Intel microcontroller multiplexed address output or data input port bit 2

H4

F4

PHI signal for

• data input/output port bit 3

• Intel microcontroller multiplexed address output or data input port bit 3

PHI signal for

• data input/output port bit 4

• Intel microcontroller multiplexed address output or data input port bit 4

G4

E11

D4

D5

PHI signal for

• data input/output port bit 5

• Intel microcontroller multiplexed address output or data input port bit 5

PHI signal for

• data input/output port bit 6

• Intel microcontroller multiplexed address output or data input port bit 6

PHI signal for

• data input/output port bit 7

• Intel microcontroller multiplexed address output or data input port bit 7

PHI signal for

• data input/output port bit 8

• Intel microcontroller multiplexed address output or data input port bit 8

SAA7160_1

Product data sheet

Rev. 01 — 25 February 2008

20 of 57

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

Table 2.

Symbol

PHI_9

Description of functional pins …continued

Type^[1]Description

G11 IO

PHI signal for

• data input/output port bit 9

• Intel microcontroller multiplexed address output or data input port bit 9

PHI_10

PHI_11

PHI_12

PHI_13

PHI_14

PHI_15

F10

F11

E5

IO

PHI signal for

• data input/output port bit 10

• Intel microcontroller address output port bit 10

PHI signal for

• data input/output port bit 11

• Intel microcontroller address output port bit 11

PHI signal for

• data input/output port bit 12

• Intel microcontroller address output port bit 12

E10

E4

PHI signal for

• data input/output port bit 13

• Intel microcontroller address output port bit 13

PHI signal for

• data input/output port bit 14

• Intel microcontroller address output port bit 14

E9

PHI signal for

• data input/output port bit 15

• Intel microcontroller address output port bit 15

PHI_WRN

PHI_RDN

D8

D7

D6

IOU

PHI signal for

• data write cycle indicator ‘WRN’ (active LOW)

PHI signal for

• data read cycle indicator ‘RDN’ (active LOW)

PHI signal for

PHI_RDY_0

PHI_RDY_1

PHI_RDY_2

PHI_RDY_3

PHI_ALE

• PHI, parallel host port ready/wait indicator ‘phi_rdy_0’

PHI signal for

D11 IOU

• ready/wait indicator ‘phi_rdy_1’

PHI signal for

J11

IOD

• external parallel host port ready/wait indicator ‘phi_rdy_2’

PHI signal for

H12 IOD

H11 IOD

• external parallel host port ready/wait indicator ‘phi_rdy_3’

PHI signal for

• output address latch enable; latches the LOW byte of the address

PCI Express differential receive data input 0 (positive)

PCI Express differential receive data input 0 (negative)

PCI Express differential transmit data output 0 (positive)

PCI Express differential transmit data output 0 (negative)

PCI Express clock 100 MHz differential input (positive)

PCI Express clock 100 MHz differential input (negative)

PCI_PER_P0

PCI_PER_N0

PCI_PET_P0

PCI_PET_N0

PCI_REFCLKP

PCI_REFCLKN

P4

P5

P6

P7

N6

N7

AI

AO

AI

SAA7160_1

Product data sheet

Rev. 01 — 25 February 2008

21 of 57

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

Table 2.

Symbol

PCI_PVT

Description of functional pins …continued

Type^[1]Description

M6

AI

this signal is used to create a compensation signal internally which will adjust the I/O

pads’ characteristics as PVT drifts; connect 33 Ω resistor to V_{DDD(PCI0)(1V0)}

PCI_RESN

TRSTN

TCK

M7

M4

P2

ID

system reset (active LOW)

IU

JTAG test reset input: drive HIGH for JTAG mode, drive LOW for normal operation

JTAG test clock input

IU

TMS

M3

N3

P3

IU

JTAG test mode select

TDO

O

JTAG test serial data output

TDI

IU

JTAG test serial data input

SPI_CLK

SPI_MA_SL

SPI_SL_MA

TEST1

P9

IU

SPI clock

N9

M9

K11

M2

N2

H3

IOU

ID

SPI; transfer serial data from master to slave (slave data input or master data output)

SPI; transfer serial data from slave to master (master data input or slave data output)

enable test mode 1; must be connected to V_SS

I²C-bus clock of second I²C-bus interface (interface can be used for boot EEPROM)

I²C-bus data of second I²C-bus interface (interface can be used for boot EEPROM)

I²S-bus port B: digital audio input signal for

SCL_B

IO

SDA_B

I2S_SD0_B

• I2S_SD serial data line of Inter IC Sound bus serial interconnect format

I²S-bus port B: digital audio input signal for

I2S_SD1_B

I2S_WS_B

I2S_SCK_B

G2

G3

G1

IO

I

• I2S_SD serial data line of Inter IC Sound bus serial interconnect format

I²S-bus port B: digital audio input signal for

• I2S_WS word select line of Inter IC Sound bus serial interconnect format

I²S-bus port B: digital audio input signal for

• I2S_SCK bit clock of Inter IC Sound bus serial interconnect format

[1] The pin types are deﬁned in Table 3.

Table 3.

Type

AI

Pin type description

Description

analog input

AO

I

analog output

digital input

ID

input with pull-down

IO

digital input and output

IOD

IOU

IU

input and output with pull-down

input and output with internal pull-up

input with internal pull-up

digital output

O

SAA7160_1

Product data sheet

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22 of 57

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

Table 4.

Symbol

Supply pins

Description

3.3 V IO supply voltage

V_DDDE1(3V3)

V_DDDE2(3V3)

V_DDDE3(3V3)

G5, H5

digital extend supply voltage 1 (3.3 V)

digital extend supply voltage 2 (3.3 V)

digital extend supply voltage 3 (3.3 V)

G10, K8

E7, E8

3.3 V analog supply voltage

V_{DDA(PCI0)(3V3)}

V_{DDA(PCI1)(3V3)}

L5

L6

PCI Express 0 analog supply voltage (3.3 V)

PCI Express 1 analog supply voltage (3.3 V)

1.0 V IO supply voltage

V_{DDD(PCI0)(1V0)}

V_{DDD(PCI1)(1V0)}

K5

K6

PCI Express 0 digital supply voltage (1.0 V)

PCI Express 1 digital supply voltage (1.0 V)

1.25 V core supply voltage

V_DDDI1(1V25)

E6, F5

H10, K9

J10

digital internal supply voltage 1 (1.25 V)

digital internal supply voltage 2 (1.25 V)

V_DDDI2(1V25)

V_DDDI(1V25)/TEST

digital internal supply voltage (1.25 V) and power start-up test

input; must be connected to 1.25 V

V_{DDD(PCI0)(1V25)}

V_{DDD(PCI1)(1V25)}

K7

L7

PCI Express 0 digital supply voltage (1.25 V)

PCI Express 1 digital supply voltage (1.25 V)

Ground supply voltage

V_SS

G6, G7, G8, G9, H6, H7, H8, H9, J6, ground supply voltage

J7, J8, J9, F6, F7, F8, F9, N4, N5, P8

SAA7160_1

Product data sheet

Rev. 01 — 25 February 2008

23 of 57

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

5.2 SAA7160ET package TFBGA88

5.2.1 Pinning

ball A1

index area

SAA7160ET

1

2 3 4 5 6 7 8 9 10 11 12 13

A

B

C

D

E

F

G

H

J

K

L

M

N

008aaa086

Transparent top view

Fig 4. Pin conﬁguration for TFBGA88

1

2

3

4

5

6

7

8

9

10

11

12

13

P2_VS

_SOP

P6_VS

_SOP

A

B

C

D

E

F

P2_HS

P2_CLK

P6_VAL

P6_CLK

P6_HS

P6_6

P6_3

P6_1

P6_0

I2S_SCK_A I2S_SD0_A I2S_SD1_A

V

DDDE1

(3V3)

DDDE3

(3V3)

P2_7

V

SS

V

SS

P6_7

V

P6_5

P6_4

P6_2

V

SS

I2S_WS_A

GPIO_17

GPIO_16

P2_VAL

GPIO_2

SS

V

DDDI

(1V25)

DDDI

(1V25)

P2_6

P2_5

P2_4

P2_2

V

DDDI

V

DDDE2

(3V3)

(1V25)

V

SS

P2_3

TEST1

GPIO_3

GPIO_5

V

SS

GPIO_4

G

H

J

P2_1

I2S_SD1_B

P2_0

I2S_WS_B

GPIO_6

V

DDDE1

V

SS

GPIO_14

I2S_SCK_B

(3V3)

V

DDDI

DDDI(1V25)/

TEST

K

L

I2S_SD0_B

SDA_A

SCL_B

(1V25)

SCL_A

GPIO_15

GPIO_26

GPIO_20

V

DDD(PCI)

(1V0)

PCI_PVT

PCI_RESN

V

TRSTN

TCK

TDI

TDO

BOOT_1

TMS

M

N

SDA_B

V

SS

V

PCI_PET

_P0

PCI_PET

_N0

V

PCI_REF

CLKP

PCI_REF

CLKN

PCI_PER

_P0

PCI_PER

_N0

DDA(PCI)

(3V3)

DDD(PCI)

SPI_CLK SPI_MA_SL SPI_SL_MA BOOT_0

008aaa088

(1V25)

Fig 5. Pin conﬁguration (TFBGA88 top view) for SAA7160ET

SAA7160_1

Product data sheet

Rev. 01 — 25 February 2008

24 of 57

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

5.2.2 Pin description

Table 5.

Symbol

SCL_A

Description of functional pins

L2

Type^[1]Description

IO

I²C-bus clock of ﬁrst I²C-bus interface

SDA_A

L1

I²C-bus data of ﬁrst I²C-bus interface

I2S_SD0_A

A12

I²S-bus port A: digital audio input signal for

• I2S_SD serial data line of Inter IC Sound bus serial interconnect format

I²S-bus port A: digital audio input signal for

I2S_WS_A

I2S_SCK_A

I2S_SD1_A

P2_0

B13

A11

A13

H2

IO

I

• I2S_WS word select line of Inter IC Sound bus serial interconnect format

I²S-bus port A: digital audio input signal for

• I2S_SCK bit clock of Inter IC Sound bus serial interconnect format

I²S-bus port A: digital audio input signal for

IO

ID

• I2S_SD serial data line of Inter IC Sound bus serial interconnect format

1. digital input signal of VIP_1, FGPI_2 or FGPI_3 for parallel video data modes

–

STV YUV[7:0] bit 0

STV YUV[9:0] bit 2

HDTV UV[9:0] bit 2

2. digital input signal of FGPI_2 or FGPI_3 for parallel

–

transport stream data of TS2[7:0] bit 0

program stream data of PS2[7:0] bit 0

P2_1

P2_2

P2_3

G1

F1

E2

ID

1. digital input signal of VIP_1, FGPI_2 or FGPI_3 for parallel video data modes

–

STV YUV[7:0] bit 1

STV YUV[9:0] bit 3

HDTV UV[9:0] bit 3

2. digital input signal of FGPI_2 or FGPI_3 for parallel

–

transport stream data of TS2[7:0] bit 1

program stream data of PS2[7:0] bit 1

1. digital input signal of VIP_1, FGPI_2 or FGPI_3 for parallel video data modes

–

STV YUV[7:0] bit 2

STV YUV[9:0] bit 4

HDTV UV[9:0] bit 4

2. digital input signal of FGPI_2 or FGPI_3 for parallel

–

transport stream data of TS2[7:0] bit 2

program stream data of PS2[7:0] bit 2

1. digital input signal of VIP_1, FGPI_2 or FGPI_3 for parallel video data modes

–

STV YUV[7:0] bit 3

STV YUV[9:0] bit 5

HDTV UV[9:0] bit 5

2. digital input signal of FGPI_2 or FGPI_3 for parallel

–

transport stream data of TS2[7:0] bit 3

program stream data of PS2[7:0] bit 3

SAA7160_1

Product data sheet

Rev. 01 — 25 February 2008

25 of 57

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

Table 5.

Symbol

P2_4

Description of functional pins …continued

Type^[1]Description

E1

ID

1. digital input signal of VIP_1, FGPI_2 or FGPI_3 for parallel video data modes

–

STV YUV[7:0] bit 4

STV YUV[9:0] bit 6

HDTV UV[9:0] bit 6

2. digital input signal of FGPI_2 or FGPI_3 for parallel

–

transport stream data of TS2[7:0] bit 4

program stream data of PS2[7:0] bit 4

P2_5

P2_6

P2_7

D1

C1

B1

1. digital input signal of VIP_1, FGPI_2 or FGPI_3 for parallel video data modes

–

STV YUV[7:0] bit 5

STV YUV[9:0] bit 7

HDTV UV[9:0] bit 7

2. digital input signal of FGPI_2 or FGPI_3 for parallel

–

transport stream data of TS2[7:0] bit 5

program stream data of PS2[7:0] bit 5

1. digital input signal of VIP_1, FGPI_2 or FGPI_3 for parallel video data modes

–

STV YUV[7:0] bit 6

STV YUV[9:0] bit 8

HDTV UV[9:0] bit 8

2. digital input signal of FGPI_2 or FGPI_3 for parallel

–

transport stream data of TS2[7:0] bit 6

program stream data of PS2[7:0] bit 6

1. digital input signal of VIP_1, FGPI_2 or FGPI_3 for parallel video data modes

–

STV YUV[7:0] bit 7

STV YUV[9:0] bit 9

HDTV UV[9:0] bit 9

2. digital input signal of FGPI_2 or FGPI_3 for parallel

–

transport stream data of TS2[7:0] bit 7

program stream data of PS2[7:0] bit 7

P2_CLK

P2_HS

A3

A2

ID

1. digital input signal of FGPI_2 or FGPI_3 for parallel

–

transport stream clock of TS2

program stream clock of PS2

2. digital input signal of VIP_1, FGPI_2 or FGPI_3 for

clock signal of parallel video data

digital input signal of VIP_1, FGPI_2 or FGPI_3 for

• horizontal synchronization of digital video port

• parallel video data mode STV YUV[9:0] bit 0

• parallel video data mode HDTV UV[9:0] bit 0

SAA7160_1

Product data sheet

Rev. 01 — 25 February 2008

26 of 57

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

Table 5.

Description of functional pins …continued

Symbol

Type^[1]Description

P2_VS_SOP

A1

ID

1. digital input signal of VIP_1, FGPI_2 or FGPI_3 for

–

parallel video data mode STV YUV[9:0] bit 1

parallel video data mode HDTV UV[9:0] bit 1

vertical synchronization reference in 8-bit STV mode

2. digital input signal ‘start of package’ of FGPI_2 or FGPI_3 for parallel

–

transport stream data of TS2

program stream data of PS2

P2_VAL

P6_0

E13

A10

ID

digital input control signal ‘valid data’ of FGPI_2 or FGPI_3 for parallel

• transport stream data of TS2

• program stream data of PS2

If this pin is unused it is necessary to connect the pin to 3.3 V supply voltage.

1. digital input signal of VIP_0, FGPI_0 or FGPI_1 for parallel video data modes

–

STV YUV[7:0] bit 0

STV YUV[9:0] bit 2

HDTV Y[9:0] bit 2

2. digital input signal of FGPI_0 or FGPI_1 for parallel

–

transport stream data of TS6[7:0] bit 0

program stream data of PS6[7:0] bit 0

P6_1

P6_2

P6_3

A9

ID

1. digital input signal of VIP_0, FGPI_0 or FGPI_1 for parallel video data modes

–

STV YUV[7:0] bit 1

STV YUV[9:0] bit 3

HDTV Y[9:0] bit 3

2. digital input signal of FGPI_0 or FGPI_1 for parallel

–

transport stream data of TS6[7:0] bit 1

program stream data of PS6[7:0] bit 1

B11

1. digital input signal of VIP_0, FGPI_0 or FGPI_1 for parallel video data modes

–

STV YUV[7:0] bit 2

STV YUV[9:0] bit 4

HDTV Y[9:0] bit 4

2. digital input signal of FGPI_0 or FGPI_1 for parallel

–

transport stream data of TS6[7:0] bit 2

program stream data of PS6[7:0] bit 2

A8

1. digital input signal of VIP_0, FGPI_0 or FGPI_1 for parallel video data modes

–

STV YUV[7:0] bit 3

STV YUV[9:0] bit 5

HDTV Y[9:0] bit 5

2. digital input signal of FGPI_0 or FGPI_1 for parallel

–

transport stream data of TS6[7:0] bit 3

program stream data of PS6[7:0] bit 3

SAA7160_1

Product data sheet

Rev. 01 — 25 February 2008

27 of 57

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

Table 5.

Symbol

P6_4

Description of functional pins …continued

Type^[1]Description

B10

ID

1. digital input signal of VIP_0, FGPI_0 or FGPI_1 for parallel video data modes

–

STV YUV[7:0] bit 4

STV YUV[9:0] bit 6

HDTV Y[9:0] bit 6

2. digital input signal of FGPI_0 or FGPI_1 for parallel

–

transport stream data of TS6[7:0] bit 4

program stream data of PS6[7:0] bit 4

P6_5

P6_6

P6_7

B9

A7

B7

1. digital input signal of VIP_0, FGPI_0 or FGPI_1 for parallel video data modes

–

STV YUV[7:0] bit 5

STV YUV[9:0] bit 7

HDTV Y[9:0] bit 7

2. digital input signal of FGPI_0 or FGPI_1 for parallel

–

transport stream data of TS6[7:0] bit 5

program stream data of PS6[7:0] bit 5

1. digital input signal of VIP_0, FGPI_0 or FGPI_1 for parallel video data modes

–

STV YUV[7:0] bit 6

STV YUV[9:0] bit 8

HDTV Y[9:0] bit 8

2. digital input signal of FGPI_0 or FGPI_1 for parallel

–

transport stream data of TS6[7:0] bit 6

program stream data of PS6[7:0] bit 6

1. digital input signal of VIP_0, FGPI_0 or FGPI_1 for parallel video data modes

–

STV YUV[7:0] bit 7

STV YUV[9:0] bit 9

HDTV Y[9:0] bit 9

2. digital input signal of FGPI_0 or FGPI_1 for parallel

–

transport stream data of TS6[7:0] bit 7

program stream data of PS6[7:0] bit 7

P6_CLK

P6_HS

A6

B6

ID

1. digital input signal of FGPI_0 or FGPI_1 for parallel

–

transport stream clock of TS6

program stream clock of PS6

2. digital input signal of VIP_0, FGPI_0 or FGPI_1 for

clock signal for parallel video data modes

–

digital input signal of VIP_0, FGPI_0 or FGPI_1 for

• parallel video data mode STV YUV[9:0] bit 0

• parallel video data mode HDTV Y[9:0] bit 0

• horizontal synchronization reference in 8-bit STV mode

SAA7160_1

Product data sheet

Rev. 01 — 25 February 2008

28 of 57

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

Table 5.

Description of functional pins …continued

Symbol

Type^[1]Description

P6_VS_SOP

A5

ID

1. digital input signal of VIP_0, FGPI_0 or FGPI_1 for

–

parallel video data mode STV YUV[9:0] bit 1

parallel video data mode HDTV Y[9:0] bit 1

vertical synchronization reference in 8-bit STV mode

2. digital input signal ‘start of package’ of FGPI_0 or FGPI_1 for parallel

–

transport stream data of TS6

program stream data of PS6

P6_VAL

A4

ID

digital input control signal ‘valid data’ of FGPI_0 or FGPI_1 for parallel

• transport stream data of TS6

• program stream data of PS6

If this pin is unused it is necessary to connect the pin to 3.3 V supply voltage.

GPIO_2

GPIO_3

GPIO_4

GPIO_5

GPIO_6

GPIO_14

GPIO_15

GPIO_16

GPIO_17

GPIO_20

GPIO_26

F13

IOU

GPIO: programming control port signal for

• general purpose input/output port 2

• external interrupt 2; interrupt edge sensitive with programmable edge polarity

G12 IOU

G13 IOU

H12 IOU

H13 IOU

GPIO: programming control port signal for

• general purpose input/output port 3

• external interrupt 3; interrupt edge sensitive with programmable edge polarity

GPIO: programming control port signal for

• general purpose input/output port 4

• external interrupt 4; interrupt edge sensitive with programmable edge polarity

GPIO: programming control port signal for

• general purpose input/output port 5

• external interrupt 5; interrupt edge sensitive with programmable edge polarity

GPIO: programming control port signal for

• general purpose input/output port 6

• external interrupt 6; interrupt edge sensitive with programmable edge polarity

J13

L12

IOU

GPIO: programming control port signal for

• general purpose input/output port 14

• external interrupt 14; interrupt edge sensitive with programmable edge polarity

GPIO: programming control port signal for

• general purpose input/output port 15

• external interrupt 15; interrupt edge sensitive with programmable edge polarity

D13 IOU

C13 IOU

M13 IOU

GPIO: programming control port signal for

• general purpose input/output port 16

• PHI chip select to other external devices (active LOW)

GPIO: programming control port signal for

• general purpose input/output port 17

• PHI chip select to other external devices (active LOW)

GPIO: programming control port signal for

• general purpose input/output port 20

• PHI chip select to other external devices (active LOW)

L13

IOU

GPIO: programming control port signal for

• general purpose input/output port 26

SAA7160_1

Product data sheet

Rev. 01 — 25 February 2008

29 of 57

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

Table 5.

Symbol

BOOT_0

Description of functional pins …continued

Type^[1]Description

N13 IOU

GPIO: programming control port signal for

• general purpose input/output port 30

• boot mode GPIO_[31:30] bit 0

BOOT_1

M11 IOU

GPIO: programming control port signal for

• general purpose input/output port 31

• boot mode GPIO_[31:30] bit 1

PCI_PER_P0

PCI_PER_N0

PCI_PET_P0

PCI_PET_N0

PCI_REFCLKP

PCI_REFCLKN

PCI_PVT

N1

N2

N4

N5

N7

N8

M5

AI

PCI Express differential receive data input 0 (positive)

PCI Express differential receive data input 0 (negative)

PCI Express differential transmit data output 0 (positive)

PCI Express differential transmit data output 0 (negative)

PCI Express clock 100 MHz differential input (positive)

PCI Express clock 100 MHz differential input (negative)

AI

AO

AI

this signal is used to create a compensation signal internally which will adjust the IO

pads’ characteristics as PVT drifts; connect 33 Ω resistor to V_{DDD(PCI)(1V25)}

PCI_RESN

TRSTN

TCK

M6

M8

M9

ID

IU

system reset (active LOW)

JTAG test reset input: drive HIGH for normal operation

JTAG test clock input

TMS

M12 IU

JTAG test mode select

TDO

M10

N9

O

JTAG test serial data output

TDI

IU

JTAG test serial data input

SPI_CLK

SPI_MA_SL

SPI_SL_MA

TEST1

N10 IU

SPI clock

N11 IOU

N12 IOU

SPI; transfer serial data from master to slave (slave data input or master data output)

SPI; transfer serial data from slave to master (master data input or slave data output)

enable test mode 1; must be connected to V_SS

I²C-bus clock of second I²C-bus interface (interface can be used for boot EEPROM)

I²C-bus data of second I²C-bus interface (interface can be used for boot EEPROM)

I²S-bus port B: digital audio input signal for

F12

K2

ID

IO

SCL_B

SDA_B

I2S_SD0_B

M1

K1

• I2S_SD serial data line of Inter IC Sound bus serial interconnect format

I²S-bus port B: digital audio input signal for

I2S_SD1_B

I2S_WS_B

I2S_SCK_B

G2

H1

J1

IO

I

• I2S_SD serial data line of Inter IC Sound bus serial interconnect format

I²S-bus port B: digital audio input signal for

• I2S_WS word select line of Inter IC Sound bus serial interconnect format

I²S-bus port B: digital audio input signal for

• I2S_SCK bit clock of Inter IC Sound bus serial interconnect format

[1] The pin types are deﬁned in Table 3.

SAA7160_1

Product data sheet

Rev. 01 — 25 February 2008

30 of 57

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

Table 6.

Symbol

Supply pins

Description

3.3 V IO supply voltage

V_DDDE1(3V3)

V_DDDE2(3V3)

V_DDDE3(3V3)

B2, J2

digital extend supply voltage 1 (3.3 V)

digital extend supply voltage 2 (3.3 V)

digital extend supply voltage 3 (3.3 V)

D12

B5

3.3 V analog supply voltage

V_{DDA(PCI)(3V3)}N3

1.0 V IO supply voltage

V_{DDD(PCI)(1V0)}M4

1.25 V core supply voltage

PCI Express analog supply voltage (3.3 V)

PCI Express digital supply voltage (1.0 V)

digital internal supply voltage (1.25 V)

V_DDDI(1V25)

C2, C12, D2, K12

V_DDDI(1V25)/TEST

K13

digital internal supply voltage (1.25 V) and power

start-up test input; must be connected to 1.25 V

V_{DDD(PCI)(1V25)}

N6

PCI Express digital supply voltage (1.25 V)

Ground supply voltage

V_SS

B3, B4, B8, B12, E12, F2, J12, M2, M3, M7 ground supply voltage

6. Functional description

6.1 DVI

The video input processing is responsible for capturing and processing the different video

input streams. After capturing and processing the data streams, the VIP transfers the data

via multiple DMA channels to the PCI Express bus. The processor supports data tagging

to indicate to the system when a certain amount of data (e.g. a video frame) has been

transferred to the PCI Express core. Figure 6 shows the functional block diagram of the

VIP. The video input module contains the following submodules:

• 2 × VIP, used for SD or HD video capture (YUV 4 : 2 : 2)

• 4 × FGPI, used for SD video capture (YUV 4 : 2 : 2) or TS/PS

Features:

• Independent digital video inputs in YUV (8-bit or 10-bit)

The DVI interface supports the following signal formats as inputs.

• STV: ITU-R BT.656, ITU-R BT.601, VIP (VESA)

• Progressive: ITU-R BT.1358, SMPTE 293M-1996 (480p)

• HDTV: SMPTE 274-1998 (1080i, 4, 5), SMPTE 296M-1997 (720p)

SAA7160_1

Product data sheet

Rev. 01 — 25 February 2008

31 of 57

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

DIGITAL VIDEO INPUT

PORT 1

DIGITAL VIDEO

INPUT INTERFACE

10

VIP

1

port 1

port 2

port 3

port 4

port 5

port 6

PORT 2

DIGITAL VIDEO

INPUT INTERFACE

FGPI

3

FGPI

2

PORT 3

DIGITAL VIDEO

INPUT INTERFACE

DEVICE

TRANSACTION

LEVEL

PROTOCOL

PORT 4

DIGITAL VIDEO

INPUT INTERFACE

VIP

0

PORT 5

DIGITAL VIDEO

INPUT INTERFACE

FGPI

0

FGPI

1

PORT 6

DIGITAL VIDEO

INPUT INTERFACE

001aag989

Fig 6. DVI system

The input modules can be used in different combinations. The SAA7160E supports up to

a maximum of six simultaneous streams (e.g. six SD video streams, or four TS/PS

streams, or a combination of both). HD support is limited to one stream.

The SAA7160ET supports up to two simultaneous streams (e.g. two SD video streams,

two TS/PS streams, or a combination of both) and one HD stream.

In order to support all the possible use cases, six 10-bit wide input ports (port 1, port 2,

port 3, port 4, port 5, port 6) are required. The SAA7160E supports all six ports. The

SAA7160ET supports two ports only (port 2 and port 6).

Table 7 describes the combination of the video input modes.

The routing of the video input ports to the video input processors is implemented by a

multiplexer. The multiplexer is implemented such that each video input port drives VIP or

FGPI. The HD support is wired to two internal ports for VIP 0 and VIP 1 respectively.

The video input multiplexer takes care of routing the video input ports to the VIP and the

FGPI. The video input multiplexer includes one multiplexer for routing the VIP to the video

input processor and another one for routing the input ports to the FGPI.

Each 10-bit wide video input port can be used for capturing a single SD or TS/PS stream,

or two ports can be combined to capture an HD stream. Dependent on the stream type,

the port bits may serve a different purpose. Input streams can be either 8-bit or 10-bit

wide, and in case of 8-bit wide input streams the two LSBs of the video input port may be

used for the horizontal and vertical synchronization signals (href and vref).

SAA7160_1

Product data sheet

Rev. 01 — 25 February 2008

32 of 57

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

6.1.1 DMA byte alignment

The DMA byte alignment module implements the byte address alignment for each of the

DMA channels coming from the AV input modules. The module addresses alignment with

byte granularity in an entire 4 kB page.

The main features are:

• Byte address alignment for DTL-MMSD streams

– Address alignment within 4 kB page (0 B to 4095 B)

• Support for multiple buffering

– Maximum 8 memory buffers (8 address offset registers per DMA channel)

• Support for 12 DMA channels

– 2 × 3 VIP (data width is 64 bit)

– 4 × 1 FGPI

– 2 × 1 AI

Based on the current buffer number the module selects the correct address offset register.

It implements 8 address offset registers per DMA channel to support multiple buffering.

The memory buffer handling supports up to 8 buffers per DMA channel. The (byte)

address alignment for the different buffers is the same, and hence the module implements

8 address offset registers per DMA channel such that each buffer can have a different

address alignment.

6.2 Message signal interrupt

The MSI logic is responsible for generating the MSI messages. MSI is a native feature in

PCI Express that enables a device to request a service by writing an interrupt event. The

write transaction address speciﬁes the MSI message destination and the write transaction

data speciﬁes the message including a message ID.

The main features of the MSI logic are:

• MSI capability

– 32 different messages

– Programmable ID in MSI message data ﬁeld

– Programmable MSI message address ﬁeld

• Programmable MSI delay timer

• Support for the following interrupt sources:

– DMA channel acknowledge interrupts (12 ×)

– DMA channel overﬂow interrupts (12 ×)

– AV interrupts (8 ×)

– I²C-bus interrupts (2 ×)

– External interrupts from GPIO (16 ×)

– All interrupts edge sensitive with programmable edge polarity

• Support for interrupt masking (i.e. enable/disable)

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• Support for INT_A emulation

During device conﬁguration, system software reads the capability list of the logic core to

ﬁnd out whether it supports MSI, and if yes how many different MSI messages it is

requesting. Using the multiple message feature allows a PCI Express device to give

different MSI messages a unique message ID.

The maximum number of requested MSI messages is 32 and must be aligned to a power

of two (1, 2, 4, 8, 16 or 32). The PCI Express core will be conﬁgured for 32 requested

messages (i.e. before device conﬁguration). After reading the capability list, system

software initializes the following parameters:

• MME ﬁeld

Deﬁnes the number of granted messages, which is either all 32 or a subset of the

number of requested messages.

• MSI message destination address

Deﬁnes the (physical) message destination address for MSI messages.

• MSI message data

Deﬁnes the message data for MSI messages.

to/from

DCSN

to/from

DCSN

INT_A EMULATION

0

1

0

1

MSI MESSAGE TC

MSI MESSAGE ID

MSI DELAY

TIMER

to

core

DTL-MMSD

INITIATOR

40

MSI MESSAGE TC

MSI MESSAGE ID

ROUND-ROBIN ARBITRATION

EXTERNAL INTERRUPT

CONTROL

INTERNAL INTERRUPT CONTROL

from

GPIO

from

I C-bus

from

AV input

from

MMU

from

clock unit

2

001aag987

Fig 7. Block diagram MSI

MSI messages can be generated for one of the following events:

• DMA channel interrupts

Two types of DMA channel interrupts are available:

– Acknowledge interrupt

Indicates a tagged write data element (last data element of a buffer) in the

corresponding DMA channel.

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– Overﬂow interrupt

Indicates that a buffer overﬂow has occurred in the corresponding DMA channel. It

should be noted that overﬂow interrupts are only generated for the AV DMA

channels (i.e. DMA channel 1 to 12).

• Unmapped TC interrupt

The unmapped TC interrupt indicates the MMU dropped data packet with unmapped

TC.

• AV interrupts

An AV interrupt indicates an interrupt event in the associated AV input (i.e. VIP, FGPI

or AI). An AV interrupt remains asserted HIGH until the interrupt status has been

cleared.

• External interrupts from GPIO

External interrupts are assumed to be edge sensitive with programmable edge

polarity (i.e. rising and falling edge). Furthermore, external interrupts are assumed to

be asynchronous to the MSI clock domain and are synchronized internally before they

are actually being used. This imposes the constraint that an external interrupt must be

kept asserted for at least three MSI clock cycles to ensure proper synchronization.

In the event of simultaneous interrupts only one interrupt request can be served at the

same time.

6.3 Memory management unit

The MMUs’ main task is to translate the virtual, logical addresses of the DMA data packet

into the physical addresses that are used by the operating system. The virtual address

space is 32 bit, while the physical address space is 64 bit.

The main features of the MMU are:

• Logical to physical address mapping

– 32-bit logical address

– 64-bit physical address: for legacy systems with 32-bit addressing, can be selected

for MMU physical address requirements

– Support for 12 DMA channels

• Support for multiple buffering

– Managing address transfer for 8 buffer DMA handling

– Maximum 8 memory buffers => 8 page table addresses per DMA channel =>

12 × 8 PTA

• Support for buffer sizes larger than 2 MB

• Support pre-fetching from page table to reduce latency

– 8 page table entries for 64-bit addressing

The virtual to physical address mapping is deﬁned by the operating system using

so-called page tables. A page table is a 4 kB space in system memory. Each entry in a

page table contains the physical base address for 4 kB page of contiguous memory.

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PCI Express based audio and video bridge

PHY

PCIe CORE

PACKET BUILDING

7

0

PTE[0]

TC

programming

3

64

PTE[15]

ADDER

TRANSLATION

7

24

0

PTA[0]

DMA index

address

data

PTA[15]

DMA ENGINE

streaming

001aag986

Fig 8. Block diagram MMU

Once the address mapping has been completed the data packet is forwarded to the

PCI Express core. The routing of the data packet is dependent on the trafﬁc class of the

data packet.

6.3.1 Logical to physical address mapping

The logical to physical address mapping is deﬁned by page tables. A page table is 4 kB

large and 4 kB aligned space in system memory. Each entry in a page table contains the

physical base address for 4 kB of contiguous memory (i.e. one page). With 64-bit

addressing each page table contains 4096 / 8 = 512 entries. Hence, one 4 kB page table

deﬁnes the virtual to physical addressing mapping for a memory buffer with a maximum

size of 2 MB.

The incoming data packet originates from one out of 12 DMA channels. For each DMA

channel at least one PTA is needed. Although the MMU allows to enable only one buffer

per DMA channel. In order to prevent potential audio and/or video artifacts when host SW

and AV input module are accessing the same buffer space in system memory, a minimum

of two buffers (i.e. double buffering) is required. In order to select the correct PTA the

MMU needs to know from which stream channel the data packet originates.

Based on the DMA channel number and buffer number, the MMU knows which page table

to use.

6.3.2 Multiple buffer support

The SW is able to support up to 8 buffers per DMA channel. Hence, the MMU is able to

support up to 8 PTAs per DMA channel.

Based on the DMA channel number the MMU knows which set of PTAs’ to use. The

correct PTA within a set of eight of PTAs is selected using the current memory buffer

number.

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When switching from current memory buffer to the next memory buffer, the entire set of

pre-fetched page table entries needs to be updated. If we were to update the set of

pre-fetched page table entries based on the memory buffer number that is encoded in the

virtual DMA address. The MMU takes some time to fetch the new page table entries from

system memory.

6.3.3 Large buffer support

The MMU supports up to 16 virtual DMA channel numbers while only 12 physical DMA

channels are implemented. Hence, even in a scenario with all 12 DMA channels used,

and 3 DMA channel numbers are available for supporting buffers that are larger than

2 MB.

6.4 Programming and controlling parts

The SAA7160E can be separated into 6 programming controlling parts. The SAA7160ET

supports 5 programming controlling parts.

• PCI Express interface

• PHI (not in SAA7160ET)

• SPI

• GPIO interface

• I²C-bus interfaces

• IRQ

6.4.1 PCI Express interface

The PCI Express subsystem is separated in the PHY (electrical layer) and the PCI

Express core circuit.

The function of the PHY is to connect a chip with another chip. A data link can be

established when two PHYs are connected to each other through a cable or a metal trace

on a PCB. The PHY includes a receiver and transmitter interface.

The main function of the PHY is to convert digital data into electrical signals and vice

versa.

The SAA7160 features a native PCI Express single lane (× 1) link compliant to

PCI Express Base Speciﬁcation 1.0a.

The PCI Express link consists of a differential input and a differential output pair. The data

rate of these signals is 2.5 Gbit/s (× 1 conﬁguration).

6.4.1.1 Receiving data

Incoming data enters the chip at the pins PCI_PER_N0 and PCI_PER_P0. The receiver

converts these signals from small amplitude differential signals into rail-to-rail digital

signals.

6.4.1.2 Transmitting data

The PHY transmits 8-bit data. This data is encoded using an 8-bit to 10-bit encoding

algorithm. The 2-bits overhead of the 8-bit to 10-bit encoding ensures the serial data will

be balanced and has a minimum frequency of data changes (needed for recovery).

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The parallel-to-serial converter serializes the 10-bits data into serial data streams. These

data streams are latched into the transmitter, where they are converted into small

amplitude differential signals. The transmitter has built-in de-emphasis for a larger eye

opening in the received data.

6.4.1.3 Clocking

The pins PCI_REFCLKN and PCI_REFCLKP are 100 MHz external reference clock

inputs that the PHY uses to generate the 250 MHz data clock and the internal bit rate

clock. This clock may have spread spectrum modulation that matches a system reference

clock.

6.4.2 PHI

The PHI supports the next generation of multimedia platforms with modern

microcontrollers or other peripheral devices, like e.g. MPG encoder.

The PHI interface provides the following features to control the external peripheral

devices:

• Bidirectional 16-bit wide address/data bus

• Support read/write function

• Support wait states, handshake handling with RDY signals

The interface supports two kinds of operating modes. The PHI operating mode deﬁnes

how address and data will be mapped onto the 16-bit PHI address/data bus.

• SRAM mode (address and data multiplexed)

In the SRAM mode address and read/write data are transferred across the 16-bit PHI

address/data bus. The transfer are 32-bit data with 16-bit address.

– 32-bit data read from 16-bit address (1 × address cycle + 2 × data cycle)

– 32-bit data write to 16-bit address (1 × address cycle + 2 × data cycle)

• FIFO mode (data only)

For FIFO based devices the SAA7160E supports the FIFO mode in which only data is

transferred across the 16-bit PHI address/data bus. In the FIFO mode each transfer

consists of two data cycles.

– 32-bit data read (2 × data cycle)

– 32-bit data write (2 × data cycle)

6.4.3 SPI

The SPI operates in a master mode. The interface is compliant with the Motorola SPI

speciﬁcation. This interface can be used in an application where a master, slave or

combined master and slave SPI is required.

The SPI master mode interface can access external SPI slave interfaces. Each external

slave interface has its own slave device select input signal via the GPIO pin. This signal

must be driven LOW to indicate to the slave interface that it is currently selected. The

corresponding GPIO signal must be asserted LOW before data transaction begins and

stays LOW for duration of the transfer. The main features of the master SPI are:

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• Synchronous serial full duplex communication

– 32 bit is the maximum data bit rate of ¹⁄₈of the input clock

• Compliant with Motorola SPI speciﬁcation

• Maximum data bit rate is ¹⁄₈of the input clock rate

The SPI is a serial full duplex interface. It is designed to be able to handle multiple

masters and slaves being connected to a given instantiation of the interface. Only a single

master and a single slave can communicate on the interface during a given data transfer.

During a data transfer the master always sends a byte of data to the slave and the slave

always sends a byte of data to the master.

SPI_CLK

SPI CLOCK

GENERATION

SPI

REGISTER

INTERFACE

SPI_CLK

SPI_MA_SL

SPI_SL_MA

OUTPUT

ENABLE

LOGIC

SPI STATE

CONTROL

SPI interrupt

SPI SHIFT

REGISTER

SPI_SL_MA

SPI_MA_SL

001aag988

Fig 9. Block diagram SPI

6.4.4 GPIO interface

The GPIO interface of the SAA7160E provides 32 GPIOs and of the SAA7160ET provides

13 GPIOs. A set of registers is available to control the function of the GPIOs.

The following table describes the application purposes of the GPIO pins.

• GPIO_[15:1]: interrupts from other external devices

• GPIO_[23:16]: chip select to other external devices

• GPIO_[29:26]: general purpose

• BOOT_0 and BOOT_1: boot mode. The boot mode pins can be used as application

GPIO pins after 500 µs (after power-up). The boot mode has been latched.

6.4.5 I²C-bus interface

Both types SAA7160E and SAA7160ET support two I²C-bus master interfaces. All

interfaces are developed according the ‘fast mode’ I²C-bus speciﬁcation extension (data

rate up to 400 kbit/s). The pins for the different I²C-bus interfaces are:

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• Pins SCL_A and SDA_A: pins for ﬁrst master/slave and second master/slave I²C-bus

interfaces

• Pins SCL_B and SDA_B: pins for third and fourth master/slave I²C-bus interfaces,

provide for external boot EEPROM

The external boot EEPROM will be connected to the pins SDA_B and SCL_B. This

interface allows only to support multiple masters on the I²C-bus after the boot sequence is

completed.

The main features of the I²C-bus interfaces are:

• I²C-bus multiple master programmable via internal conﬁguration bus

• I²C-bus slave to access programmable control bytes

• Programmable I²C-bus sequencer to ease and accelerate I²C-bus sequence

generated by the I²C-bus master

• Free programmable slave address

• Bidirectional data transfer between masters and slaves

• Multiple master I²C-bus (no central master)

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the I²C-bus

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial I²C-bus

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer

The two I²C-bus multiple master interface circuits provide serial interfaces which meets

the I²C-bus speciﬁcation and support all transfer modes from and to the I²C-bus.

The I²C-busses support the following functionality:

• The normal mode (100 kHz) and the fast mode (400 kHz)

• Interrupt generation on received or sent byte

• It has four modes of operation: master transmitter, master receiver, slave transmitter

and slave receiver

The I²C-bus is a multiple master bus. More than one master I²C-bus device can be

connected to the bus and it is possible to have data transfers at the same time. A collision

detect scheme is used to arbitrate between the multiple masters and select a single

master of the bus at any given time. If two or more masters try to put information onto the

bus, the ﬁrst to produce a logic 1 when the other produces a logic 0 will detect the collision

and back-off transferring information on the bus.

The clock signals during arbitration are a synchronized through combination of the clocks

generated by the I²C-bus master circuits via the SCL lines. Two wires, SDA (serial data)

and SCL (serial clock) carry information between the devices connected to the I²C-bus.

Each device can operate as either a transmitter or receiver and as a master or a slave,

depending on the function of the device. A master is the device which initiates a data

transfer on the bus and generates the clock signals to permit that transfer.

SAA7160_1

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Any device addressed by a master is considered a slave. Generation of clock signals on

the I²C-bus is always the responsibility of the master device; each master generates its

own clock signals when transferring data on the bus. Bus clock signals from a master can

only be altered when they are stretched by a slow-slave device holding down the clock line

or by another master when arbitration occurs.

CLOCK GENERATOR

2

SDA_A

global I C-bus

SCL_A

data I C-bus control

IN

2

I C-BUS

2

IRQ

INTERFACE 2

CORE 1

OUT

2

I C-bus configuration

CLOCK GENERATOR

2

SDA_B

global I C-bus

SCL_B

data I C-bus control

IN

2

I C-BUS

2

IRQ

INTERFACE 1

CORE 0

OUT

2

I C-bus configuration

BOOT EEPROM

001aag990

Fig 10. I²C-bus structure overview

6.5 I²S-bus input interface

The SAA7160 has two independent audio slave interface circuits for serial input of digital

audio data streams. The audio interface circuits are based on the I²S-bus standard but

can be conﬁgured to several data and timing formats (with respect to framing, bit clock

and synchronization).

List of key features:

2

• Supports I S-bus, LSB and MSB justiﬁed formats

• Sample size up to 32 bit

• Standard stereo I²S-bus (MSB ﬁrst, 1-bit delay from word select, left and right data in

a frame)

• LSB ﬁrst with 1-bit to 32-bits data per channel

• Raw sample mode where the serial data for each active serial channel is sampled at

each sampling clock edge along with the word-select signal

Each of the slave I²S-bus interfaces consists two data lines, a word select line and a serial

clock line. The word select line distinguishes between the left and the right channel

information of the data lines. It is possible to sample up to 32 bits per channel, and there

are 4 channels on each module available.

The following block diagram shows the structure of the different I²S-bus interfaces.

SAA7160_1

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PCI Express based audio and video bridge

CLOCK GENERATOR

I2S_WS_A

I2S_SCK_A

I2S_SD0_A

I2S_SD1_A

2

data I S-bus control

2

I S-BUS INPUT

I S-BUS

IN

IRQ

INTERFACE 0

CORE 0

2

I S-bus configuration

CLOCK GENERATOR

I2S_WS_B

I2S_SCK_B

I2S_SD0_B

I2S_SD1_B

2

data I S-bus control

2

I S-BUS INPUT

I S-BUS

IN

IRQ

INTERFACE 1

CORE 1

2

I S-bus configuration

001aag991

Fig 11. I²S-bus structure overview

Since the transmitter and receiver have the same clock signal for data transmission, the

transmitter as the master, has to generate the bit clock, word-select signal and data.

The serial data inputs are sampled under the serial clock and the word-select signal will

be converted into parallel words of 32 bits width.

7. Limiting values

Table 8.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). All ground pins connected together and all

corresponding supply pins connected together.

Symbol

Parameter

Conditions

Min

Max

+4.5

+1.7

Unit

V

V_{DDA(PCI0)(3V3)}

V_{DDA(PCI1)(3V3)}

V_{DDA(PCI)(3V3)}

V_DDDE1(3V3)

V_DDDE2(3V3)

V_DDDE3(3V3)

V_DDDI1(1V25)

V_DDDI2(1V25)

V_DDDI(1V25)

PCI Express 0 analog supply voltage (3.3 V)

PCI Express 1 analog supply voltage (3.3 V)

PCI Express analog supply voltage (3.3 V)

digital extend supply voltage 1 (3.3 V)

digital extend supply voltage 2 (3.3 V)

digital extend supply voltage 3 (3.3 V)

digital internal supply voltage 1 (1.25 V)

digital internal supply voltage 2 (1.25 V)

digital internal supply voltage (1.25 V)

−0.5

V

includes

V

pin V_DDDI(1V25)/TEST

V_{DDD(PCI0)(1V25)}PCI Express 0 digital supply voltage (1.25 V)

V_{DDD(PCI1)(1V25)}PCI Express 1 digital supply voltage (1.25 V)

−0.5

0.85

−0.5

−40

+1.7

1.15

V

V_{DDD(PCI)(1V25)}

V_{DDD(PCI0)(1V0)}

V_{DDD(PCI1)(1V0)}

V_{DDD(PCI)(1V0)}

V_i

PCI Express digital supply voltage (1.25 V)

PCI Express 0 digital supply voltage (1.0 V)

PCI Express 1 digital supply voltage (1.0 V)

PCI Express digital supply voltage (1.0 V)

input voltage

V_DD+ 0.5 V

T_stg

storage temperature

+125

°C

SAA7160_1

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SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

Table 8.

Limiting values …continued

In accordance with the Absolute Maximum Rating System (IEC 60134). All ground pins connected together and all

corresponding supply pins connected together.

Symbol

T_amb

Parameter

Conditions

Min

Max

70

Unit

°C

V

ambient temperature

electrostatic discharge voltage

0

-

[1]

[2]

V_esd

human body model

±2000

±500

charged-device model

-

V

[1] Class 2 according to JESD22-A114.

[2] Class III according to JESD22-C101.

8. Thermal characteristics

Table 9.

Symbol

R_th(j-a)

Thermal characteristics

Parameter

Conditions

in free air

Typ

Unit

thermal resistance from junction to ambient

[1]

SAA7160E

SAA7160ET

36

63

K/W

[1] The overall R_th(j-a)value can vary depending on the board layout. To minimize the effective R_th(j-a)all power and ground pins must be

connected to the power and ground layers directly. Please do not use any solder-stop varnish under the chip. In addition the usage of

soldering glue with a high thermal conductance after curing is recommended.

9. Characteristics

Table 10. Characteristics

V_DDDE1(3V3)= V_DDDE2(3V3)= V_DDDE3(3V3)= 3.0 V to 3.6 V; V_DDDI1(1V25)= V_DDDI2(1V25)= V_DDDI(1V25)= V_{DDD(PCI0)(1V25)}

=

V_{DDD(PCI1)(1V25)}= V_{DDD(PCI)(1V25)}= 1.2 V to 1.3 V; V_{DDA(PCI0)(3V3)}= V_{DDA(PCI1)(3V3)}= V_{DDA(PCI)(3V3)}= 3.0 V to 3.6 V;

V_{DDD(PCI0)(1V0)}= V_{DDD(PCI1)(1V0)}= V_{DDD(PCI)(1V0)}= 0.9 V to 1.1 V; T_amb= 25 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ Max

Unit

Supplies

V_DDDE1(3V3)

digital extend supply

voltage 1 (3.3 V)

3.0

1.2

3.3 3.6

1.25 1.3

V

V_DDDE2(3V3)

V_DDDE3(3V3)

V_DDDI1(1V25)

V_DDDI2(1V25)

V_DDDI(1V25)

digital extend supply

voltage 2 (3.3 V)

digital extend supply

voltage 3 (3.3 V)

digital internal supply

voltage 1 (1.25 V)

digital internal supply

voltage 2 (1.25 V)

digital internal supply

voltage (1.25 V)

includes pin

V_DDDI(1V25)/TEST

V_{DDD(PCI0)(1V25)}PCI Express 0 digital

supply voltage (1.25 V)

V_{DDD(PCI1)(1V25)}PCI Express 1 digital

supply voltage (1.25 V)

V_{DDD(PCI)(1V25)}PCI Express digital

supply voltage (1.25 V)

SAA7160_1

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PCI Express based audio and video bridge

Table 10. Characteristics …continued

V_DDDE1(3V3)= V_DDDE2(3V3)= V_DDDE3(3V3)= 3.0 V to 3.6 V; V_DDDI1(1V25)= V_DDDI2(1V25)= V_DDDI(1V25)= V_{DDD(PCI0)(1V25)}

_{DDD(PCI1)(1V25)}= V_{DDD(PCI)(1V25)}= 1.2 V to 1.3 V; V_{DDA(PCI0)(3V3)}= V_{DDA(PCI1)(3V3)}= V_{DDA(PCI)(3V3)}= 3.0 V to 3.6 V;

_{DDD(PCI0)(1V0)}= V_{DDD(PCI1)(1V0)}= V_{DDD(PCI)(1V0)}= 0.9 V to 1.1 V; T_amb= 25 °C; unless otherwise speciﬁed.

=

V

Symbol

V_{DDD(PCI0)(1V0)}PCI Express 0 digital

supply voltage (1.0 V)

Parameter

Conditions

Min

0.95

Typ Max

1.0 1.05

Unit

V

V_{DDD(PCI1)(1V0)}PCI Express 1 digital

supply voltage (1.0 V)

0.95

3.1

1.0 1.05

3.3 3.5

V

V_{DDD(PCI)(1V0)}

PCI Express digital

supply voltage (1.0 V)

V_{DDA(PCI0)(3V3)}PCI Express 0 analog

supply voltage (3.3 V)

V_{DDA(PCI1)(3V3)}PCI Express 1 analog

supply voltage (3.3 V)

3.1

V_{DDA(PCI)(3V3)}

PCI Express analog

supply voltage (3.3 V)

3.1

Power dissipation

P_tottotal power dissipation

power management states

D0 for typical application

-

330

240

-

mW

D0 after reset (not

initialized)

Digital inputs (pins P1_[9:0], P1_CLK, P1_VAL, P1_HS, P1_VS_SOP, P2_[9:0], P2_CLK, P2_VS_SOP, P2_HS,

P2_VAL, P3_[9:0], P3_CLK, P3_HS, P3_VS_SOP, P3_VAL, P4_[9:0], P4_CLK, P4_VS_SOP, P4_HS, P4_VAL, P5_[9:0],

P5_CLK, P5_VAL, P5_VS_SOP, P5_HS, P6_[9:0], P6_CLK, P6_HS, P6_VS_SOP, P6_VAL, SAA7160E: GPIO_[31:26]

and GPIO_[23:0] and SAA7160ET: GPIO_31, GPIO_30, GPIO_26, GPIO_20, GPIO_[17:14] and GPIO_[6:2])

V_IL

V_IH

LOW-level input voltage

−0.5

-

+0.8

3.6

V

HIGH-level input voltage minimum extend supply

2.4

voltage V_DDDE1(3V3)

,

V_DDDE2(3V3)and V_DDDE3(3V3)

I_LI

C_i

input leakage current

input capacitance

-

10

4

µA

I/O at high-impedance

pF

Digital outputs (SAA7160E: pins GPIO_[31:26] and GPIO_[23:0]; SAA7160ET: pins GPIO_31, GPIO_30, GPIO_26,

GPIO_20, GPIO_[17:14] and GPIO_[6:2])^[1]

V_OL

LOW-level output voltage for clocks

I_OL= 3.6 mA

for clocks

I_OH= −4.5 mA

-

0.4

-

V

-

[2]

V_OH

HIGH-level output

voltage

V

_DDD− 0.4

V

-

I²C-bus interface; compatible to 3.3 V and 5 V signalling (pins SDA_A, SCL_A, SDA_B and SCL_B)

f_bit

bit rate

0

-

400

kbit/s

V

[3]

V_IL

V_IH

V_OL

LOW-level input voltage

HIGH-level input voltage

LOW-level output voltage I_sink(o)= 3 mA

−0.5

+0.3V_CC(I2C-bus)

0.7V_CC(I2C-bus)

-

V_CC(I2C-bus)+ 0.5 V

0.4

V

PCI Express interface (pins PCI_PER_P0, PCI_PER_N0, PCI_PET_P0, PCI_PET_N0, PCI_REFCLKP and

PCI_REFCLKN)

f_clk(ref)

reference clock

frequency

reference clock spread

spectrum: −0.5 % to +0 %

99.97

100 100.03

MHz

kHz

f_mod

modulation frequency

30

- 33

SAA7160_1

Product data sheet

Rev. 01 — 25 February 2008

45 of 57

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

Table 10. Characteristics …continued

V_DDDE1(3V3)= V_DDDE2(3V3)= V_DDDE3(3V3)= 3.0 V to 3.6 V; V_DDDI1(1V25)= V_DDDI2(1V25)= V_DDDI(1V25)= V_{DDD(PCI0)(1V25)}

_{DDD(PCI1)(1V25)}= V_{DDD(PCI)(1V25)}= 1.2 V to 1.3 V; V_{DDA(PCI0)(3V3)}= V_{DDA(PCI1)(3V3)}= V_{DDA(PCI)(3V3)}= 3.0 V to 3.6 V;

_{DDD(PCI0)(1V0)}= V_{DDD(PCI1)(1V0)}= V_{DDD(PCI)(1V0)}= 0.9 V to 1.1 V; T_amb= 25 °C; unless otherwise speciﬁed.

=

V

Symbol Parameter Conditions Min Typ Max

R_term

Unit

[4]

termination resistance

input voltage

pins PCI_REFCLKP and

PCI_REFCLKN

-

50

-

Ω

V_i

pins PCI_REFCLKP and

PCI_REFCLKN

differential

50

100

0

-

mV

V

single-ended

-

[5]

V_I(cm)

common-mode input

voltage

differential;

0.6

pins PCI_REFCLKP and

PCI_REFCLKN

f_bit(RX)

f_bit(TX)

receiver bit rate

-

2.5

-

Gbit/s

UI

transmitter bit rate

-

t_{TX_JITTER_MAX}maximum transmitter

jitter time

0.3

t_jit(RX)

t_r(tx)

receiver jitter time

transmit rise time

transmit fall time

-

0.6

100

-

UI

ps

µs

-

t_f(tx)

-

t_{lock(PLL)(tx)}

transmit PLL lock time

50

PHI bus inputs and outputs (pins PHI_WRN, PHI_RDN, PHI_RDY_[3:0] and PHI_ALE, PHI_[15:0]

t_v(Q)

data output valid time

PHI_RDN to PHI output

data, PHI_RDY_[3:0]

-

15

10

-

ns

PHI chip select NOT to PHI

output data, PHI_RDY_[3:0]

-

t_{PHI_RDN(min)}

t_su(i)

minimum PHI_RDN time PHI_RDN to PHI output

data, PHI_RDY_[3:0]

3

5

0

input set-up time

PHI_WRN to PHI output

data

-

t_{PHI_WRN(min)}

Digital inputs

minimum PHI_WRN time output data changed; PHI

output data to PHI_WRN

-

Clock input timing (pins P1_CLK, P2_CLK, P3_CLK, P4_CLK, P5_CLK and P6_CLK)

T_cy

cycle time

HD1 = 75 MHz;

13

-

75

ns

HD0 = 54 MHz;

STV = 13.5 MHz or 27 MHz

δ

t_r

t_f

duty factor

rise time

fall time

for t_LLCH/ t_LLC

40

-

50

-

60

4

%

ns

-

4

Data and control input signals on P1, P2, P3, P4, P5 and P6 ports with respect to P1_CLK, P2_CLK, P3_CLK, P4_CLK,

P5_CLK and P6_CLK

t_su(D)

t_h(D)

data input set-up time

data input hold time

3

0

-

ns

SAA7160_1

Product data sheet

Rev. 01 — 25 February 2008

46 of 57

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

Table 10. Characteristics …continued

V_DDDE1(3V3)= V_DDDE2(3V3)= V_DDDE3(3V3)= 3.0 V to 3.6 V; V_DDDI1(1V25)= V_DDDI2(1V25)= V_DDDI(1V25)= V_{DDD(PCI0)(1V25)}

_{DDD(PCI1)(1V25)}= V_{DDD(PCI)(1V25)}= 1.2 V to 1.3 V; V_{DDA(PCI0)(3V3)}= V_{DDA(PCI1)(3V3)}= V_{DDA(PCI)(3V3)}= 3.0 V to 3.6 V;

_{DDD(PCI0)(1V0)}= V_{DDD(PCI1)(1V0)}= V_{DDD(PCI)(1V0)}= 0.9 V to 1.1 V; T_amb= 25 °C; unless otherwise speciﬁed.

=

V

Symbol Parameter Conditions Min Typ Max

Unit

TS capture inputs with parallel transport streaming of the ports P1, P2, P3, P4, P5 and P6

Clock input signal (pins P1_CLK, P2_CLK, P3_CLK, P4_CLK, P5_CLK and P6_CLK)

T_cy

δ

cycle time

duty factor

rise time

fall time

-

333

-

ns

%

40

-

60

4

[2]

t_r

20 % V_DDDto 80 % V_DDD

80 % V_DDDto 20 % V_DDD

ns

t_f

-

4

Data and control input signals on TS ports with respect to P1_CLK, P2_CLK, P3_CLK, P4_CLK, P5_CLK and P6_CLK

t_su(D)

t_h(D)

data input set-up time

data input hold time

3

0

-

ns

[1] The levels must be measured with load circuits; 1.2 kΩ at 3 V (TTL load); C_L= 50 pF.

[2] V_DDD= V_DDDE1(3V3)or V_DDDE2(3V3)or V_DDDE3(3V3)

.

[3] V_CC(I2C-bus)is the extended pull-up voltage of the I²C-bus (3.3 V or 5 V bus).

[4] This reduces the mother board reference clock amplitude.

[5] The SAA7160 can handle a crossover voltage of pins PCI_REFCLKP and PCI_REFCLKN in the same range.

SAA7160_1

Product data sheet

Rev. 01 — 25 February 2008

47 of 57

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

10. Application information

PC

NORTH BRIDGE

"ROOT PORT"

SYSTEM

MEMORY

CPU

2

PCIe by 1

I C-bus

EEPROM

SAA7160

AUDIO, VIDEO, TRANSPORT STREAM

BRIDGE TO PCI EXPRESS

port 1

ITU

port 2

port 5

port 4

ITU

2

I S-bus

TS

I C-bus TS

I S-bus

AV

DTV

analog AV baseband

CVBS, YC, RGB,

analog AV baseband

CVBS, YC, RGB,

DECODER

SAA7136

DECODER

SAA7136

CHANNEL

DECODER

CHANNEL

DECODER

Y-P -P , audio input

B

R

B

R

low IF

IF

low

IF

TUNER

2

I S-bus

ITU, RGB

I S-bus

ITU, RGB

001aah353

Fig 12. Application example for SAA7160

SAA7160_1

Product data sheet

Rev. 01 — 25 February 2008

48 of 57

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

11. Test information

11.1 Boundary scan test

The SAA7160E and the SAA7160ET have built-in logic and 5 dedicated pins to support

boundary scan testing, which allows board testing without special hardware (nails). The

SAA7160E and the SAA7160ET follow the “IEEE Std. 1149.1 - Standard Test Access Port

and Boundary-Scan Architecture” set by the Joint Test Action Group (JTAG) chaired by

NXP.

The 5 special pins are Test Mode Select (TMS), Test Clock (TCK), Test Reset (TRSTN),

Test Data Input (TDI) and Test Data Output (TDO).

The Boundary Scan Test (BST) functions BYPASS, EXTEST, SAMPLE, CLAMP and

IDCODE are all supported; see Table 11. Details about the JTAG BST-TEST can be found

in the speciﬁcation “IEEE Std. 1149.1”. Two ﬁles containing the detailed Boundary Scan

Description Language (BSDL) of the SAA7160E and the SAA7160ET are available on

request.

Table 11. BST instructions supported by the SAA7160E and the SAA7160ET

Instruction Description

BYPASS

EXTEST

SAMPLE

This mandatory instruction provides a minimum length serial path (1 bit) between

TDI and TDO when no test operation of the component is required.

This mandatory instruction allows testing of off-chip circuitry and board level

interconnections.

This mandatory instruction can be used to take a sample of the inputs during

normal operation of the component. It can also be used to preload data values into

the latched outputs of the boundary scan register.

CLAMP

This optional instruction is useful for testing when not all ICs have BST. This

instruction addresses the bypass register while the boundary scan register is in

external test mode.

IDCODE

This optional instruction will provide information on the components manufacturer,

part number and version number.

11.1.1 Initialization of boundary scan circuit

The Test Access Port (TAP) controller of an IC should be in the reset state

(TEST_LOGIC_RESET) when the IC is in functional mode. This reset state also forces

the instruction register into a functional instruction such as IDCODE or BYPASS.

To solve the power-up reset, the standard speciﬁes that the TAP controller will be forced

asynchronously to the TEST_LOGIC_RESET state by setting the TRSTN pin LOW.

SAA7160_1

Product data sheet

Rev. 01 — 25 February 2008

49 of 57

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

12. Package outline

LBGA196: plastic low profile ball grid array package; 196 balls; body 15 x 15 x 1 mm

SOT879-1

A

B

D

ball A1

index area

A

2

A

1

E

detail X

C

e

1

y

e

1/2 e

v

M

b

C

A

B

C

1

w M

P

N

L

e

M

K

H

F

J

e

2

G

E

C

A

1/2 e

D

B

ball A1

index area

1

3

5

7

9

11

13

2

4

6

8

10

12

14

X

5

10 mm

0

scale

DIMENSIONS (mm are the original dimensions)

A

UNIT

A

b

e

2

y

D

E

v

w

y

1

2

1

max.

0.45

0.35

1.1

0.9

0.55 15.2 15.2

0.45 14.8 14.8

mm 1.55

0.12 0.35

1

13

0.25

0.1

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

- - -

05-03-08

05-04-19

SOT879-1

- - -

MO-192

Fig 13. Package outline SOT879-1 (LBGA196)

SAA7160_1

Product data sheet

Rev. 01 — 25 February 2008

50 of 57

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

TFBGA88: plastic thin fine-pitch ball grid array package; 88 balls; body 7 x 7 x 0.8 mm

SOT951-1

B

A

D

ball A1

index area

A

2

A

E

A

1

detail X

e

1

C

M

v

C A

C

B

e

b

y

C

1

w

N

M

L

e

K

J

H

G

F

e

2

E

D

C

B

A

ball A1

index area

1

2

3

4

5

6

7

8

9

10 11 12 13

X

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

UNIT

A

1

A

2

b

D

E

e

1

e

2

v

w

y

1

max

0.25 0.85 0.35

0.15 0.75 0.25

7.1

6.9

7.1

6.9

mm

1.1

0.5

6

0.15 0.05 0.08

0.1

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

06-05-26

06-08-25

SOT951-1

- - -

MO-195

- - -

Fig 14. Package outline SOT951-1 (TFBGA88)

SAA7160_1

Product data sheet

Rev. 01 — 25 February 2008

51 of 57

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

13. Soldering

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow

soldering description”.

13.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

13.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

• Board speciﬁcations, including the board ﬁnish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus PbSn soldering

13.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath speciﬁcations, including temperature and impurities

SAA7160_1

Product data sheet

Rev. 01 — 25 February 2008

52 of 57

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

13.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 15) than a PbSn process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 12 and 13

Table 12. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

220

< 2.5

≥ 2.5

220

Table 13. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 15.

SAA7160_1

Product data sheet

Rev. 01 — 25 February 2008

53 of 57

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 15. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

14. Abbreviations

Table 14. Abbreviations

Acronym

AI

Description

Analog Input

AV

Audio Video

BAR

Base Address Register

Boundary Scan Description Language

Boundary Scan Test

BSDL

BST

CGU

CPU

Clock Generation Unit

Central Processing Unit

Device Control Status Network

Direct Memory Access

Device Transaction Level protocol

Digital TV

DCSN

DMA

DTL

DTV

DVI

Digital Video Input

EEPROM

FGPI

FIFO

GPIO

GREG

HD

Electrically Erasable Programmable Read-Only Memory

Fast General Purpose Input

First In First Out

General Purpose Input/Output

Global REGister

High Deﬁnition

HDTV

High Deﬁnition TV

SAA7160_1

Product data sheet

Rev. 01 — 25 February 2008

54 of 57

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

Table 14. Abbreviations …continued

Acronym

Description

ID

IDentiﬁcation

IF

Intermediate Frequency

Interrupt ReQuest

Joint Test Action Group

Least Signiﬁcant Bit

Multiple Message Enable

IRQ

JTAG

LSB

MME

MMSD

MMU

MSB

MSI

PC

Memory-Mapped Streaming Data

Memory Management Unit

Most Signiﬁcant Bit

Message Signal Interrupt

Personal Computer

Printed-Circuit Board

Peripheral Component Interconnect

PCI Express

PCB

PCI

PCIe

PHI

PHY

PLL

PS

Parallel Host port Interface

PHYsical interface

Phase-Locked Loop

Program Stream

PTA

PTE

PVT

SD

Page Table Address

Page Table Entry

Process Voltage Temperature

Standard Deﬁnition

Serial Peripheral Interface

Static Random Access Memory

Standard TV

SPI

SRAM

STV

SW

SoftWare

TC

Trafﬁc Class

TS

Transport Stream

TTL

VC

Transistor-Transistor-Logic

Virtual Channel

VI

Video Input

VIP

Video Input Port

15. Revision history

Table 15. Revision history

Document ID

Release date

20080225

Data sheet status

Change notice

Supersedes

SAA7160_1

Product data sheet

-

SAA7160_1

Product data sheet

Rev. 01 — 25 February 2008

55 of 57

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

16. Legal information

16.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Applications — Applications that are described herein for any of these

16.2 Deﬁnitions

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

16.3 Disclaimers

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

16.4 Licenses

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

ICs with JPEG functionality

Purchase of an NXP Semiconductors IC with JPEG functionality does not

convey an implied license under any patent right to use this IC in any JPEG

application, e.g. a digital still picture camera. A license under the JPEG

patent of Koninklijke Philips Electronics N.V. needs to be obtained via

Philips Intellectual Property and Standards (www.ip.philips.com), e-mail:

info.licensing@philips.com.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

16.5 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I²C-bus — logo is a trademark of NXP B.V.

17. Contact information

For additional information, please visit: http://www.nxp.com

For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

SAA7160_1

Product data sheet

Rev. 01 — 25 February 2008

56 of 57

SAA7160

NXP Semiconductors

PCI Express based audio and video bridge

18. Contents

1

General description . . . . . . . . . . . . . . . . . . . . . . 1

13

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Introduction to soldering. . . . . . . . . . . . . . . . . 52

Wave and reﬂow soldering . . . . . . . . . . . . . . . 52

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 52

Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 53

13.1

13.2

13.3

13.4

2

2.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

PCI Express interface SAA7160E and

SAA7160ET . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Digital interfaces SAA7160E. . . . . . . . . . . . . . . 2

Digital interfaces SAA7160ET . . . . . . . . . . . . . 2

Digital peripheral audio interfaces SAA7160E

and SAA7160ET. . . . . . . . . . . . . . . . . . . . . . . . 2

Peripheral programming ports SAA7160E . . . . 2

Peripheral programming ports SAA7160ET . . . 3

General features SAA7160E and SAA7160ET. 3

2.2

2.3

2.4

14

15

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 54

Revision history . . . . . . . . . . . . . . . . . . . . . . . 55

16

Legal information . . . . . . . . . . . . . . . . . . . . . . 56

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 56

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 56

2.5

2.6

2.7

16.1

16.2

16.3

16.4

16.5

3

4

Ordering information. . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

5

5.1

5.1.1

5.1.2

5.2

5.2.1

5.2.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

SAA7160E package LBGA196. . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

SAA7160ET package TFBGA88 . . . . . . . . . . 24

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Pin description . . . . . . . . . . . . . . . . . . . . . . . . 25

17

18

Contact information . . . . . . . . . . . . . . . . . . . . 56

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6

6.1

6.1.1

6.2

6.3

Functional description . . . . . . . . . . . . . . . . . . 31

DVI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

DMA byte alignment . . . . . . . . . . . . . . . . . . . . 34

Message signal interrupt . . . . . . . . . . . . . . . . 34

Memory management unit . . . . . . . . . . . . . . . 36

Logical to physical address mapping . . . . . . . 37

Multiple buffer support . . . . . . . . . . . . . . . . . . 37

Large buffer support . . . . . . . . . . . . . . . . . . . . 38

Programming and controlling parts. . . . . . . . . 38

PCI Express interface. . . . . . . . . . . . . . . . . . . 38

Receiving data . . . . . . . . . . . . . . . . . . . . . . . . 38

Transmitting data . . . . . . . . . . . . . . . . . . . . . . 38

Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

PHI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

GPIO interface . . . . . . . . . . . . . . . . . . . . . . . . 40

I²C-bus interface. . . . . . . . . . . . . . . . . . . . . . . 40

I²S-bus input interface . . . . . . . . . . . . . . . . . . 42

6.3.1

6.3.2

6.3.3

6.4

6.4.1

6.4.1.1

6.4.1.2

6.4.1.3

6.4.2

6.4.3

6.4.4

6.4.5

6.5

7

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 43

Thermal characteristics. . . . . . . . . . . . . . . . . . 44

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 44

Application information. . . . . . . . . . . . . . . . . . 48

8

9

10

11

11.1

11.1.1

Test information. . . . . . . . . . . . . . . . . . . . . . . . 49

Boundary scan test. . . . . . . . . . . . . . . . . . . . . 49

Initialization of boundary scan circuit . . . . . . . 49

12

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 50

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 25 February 2008

Document identifier: SAA7160_1


型号：	SAA7160E
厂家：	NXP
描述：	PCI Express based audio and video bridge 基于PCI Express技术的音频和视频的桥梁 PC
文件：	总57页 (文件大小：246K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SAA7160E [NXP]

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