SAA7162E_技术文档

SAA7162E

PCI Express based dual channel multistandard audio and

video decoder

Rev. 02 — 13 August 2007

Product short data sheet

1. General description

The SAA7162E is a dual channel multistandard audio and video TV decoder with digital

IF demodulator and PCI Express interface. It provides 10-bit ADC, enhanced PAL/NTSC

comb ﬁltering, a versatile VBI data processing, more sophisticated scaling algorithms,

support of high deﬁnition component video, picture improvement processing, more

robustness with VCR type signals, increased audio functionality like SPDIF input/output,

I²S-bus input/output and an integrated audio sample rate converter from 32 kHz to

44.1 kHz or 48 kHz.

The SAA7162E is a highly integrated circuit for e.g. TV insertion inside PC systems. The

multistandard TV decoder covered all video color standards like PAL, NTSC and SECAM

and sound standards like dual FM, NICAM, BTSC and EIAJ. Additional to the TV decoder

function a digital IF demodulator, an FM radio decoder, standard interfaces for digital

video and audio, remote control receiver and transmission processing and a high-speed

programming port allows high integrated system solutions for multimedia application.

2. Features

2.1 Analog video acquisition

I Twenty analog inputs; allowing multiple combinations of

N Dual channel CVBS

N Dual channel S-video

N Dual channel Y/C

N One channel RGB or Y-P_B-P_R(progressive or interlaced); able to handle standard

deﬁnition signals as well as HD0

N Dual channel low IF from an NXP Silicon Tuner

I One channel RGB or Y-P_B-P_Rcomponent input according to

N 480i and 576i (standard deﬁnition and interlaced)

N 480p and 576p (HD0 and double scan rate) at two-fold over sampling (54 MHz)

I Software controlled gain adjustment for Y-P_B-P_Rcomponent inputs

I One channel 3-level input pins for one fully equipped D-terminal applications

I Eight video processing channels with automatic signal clamping and signal amplifying

adjustment to a high quality 10-bit CMOS analog-to-digital converter results in a

four-fold ITU-R BT.656 oversampled (54 MHz) video signal

I AGC for the selected CVBS or S-video channel, or manually adjustable gain for all

video signal types

SAA7162E

NXP Semiconductors

PCI Express based dual channel audio and video decoder

I Two channels with buffered analog outputs providing CVBS/S-video signal selected

from any input

I Two channels with differential analog CVBS and SSIF outputs from the integrated

digital video IF demodulator

2.2 Digital IF demodulator

I Two separate digital IF demodulators

N Worldwide multistandard analog TV IF demodulator (M/N, B/G/H, D/K, I and

L/L-accent standard)

N FM radio pre-processing, internal selectivity for FM stereo application

N Alignment-free application

N Noise shaped IF AGC output signal

N Easy programming of IF processing by TV or FM radio standard selection

2.3 Dual channel video signal processing and decoding

I Luminance and chrominance signal processing for PAL BGDHIN, combination PAL N,

PAL M, NTSC M, NTSC Japan, NTSC 4.43 and SECAM

I High-performance super-adaptive NTSC/PAL comb ﬁlter for 2-dimensional

chrominance/luminance separation for

N Increased luminance and chrominance bandwidth for all NTSC and PAL standards

N Reduced cross-color and cross luminance artefacts, even with critical color pattern

I Automatic detection of any supported color standard

I High-quality RGB and Y-P_B-P_Rcomponent processing for STV and progressive TV

I Optional reduced resolution for Y-P_B-P_Rcomponent processing of HDTV (1080i and

720p) sources

I Automatic detection of any supported video standard, including 480p, 576p, 720p and

1080i

I Automatic detection of signals from consumer grade sources (e.g. VTRs)

I Versatile BCS adjustment for CVBS/S-video, RGB and Y-P_B-P_Rcomponent processing

I Easy discrimination between CVBS and Y/C signals

I Digital PLL for synchronization and clock generation from all standards and

non-standard video sources, e.g. consumer grade VTR

I Detection of copy protected input signals according to the Macrovision standard,

indicating level of protection, including progressive signals 480p and 576p

I On-chip LLC generation according to ITU-R BT.601(standard deﬁnition) or

SMPTE 293M/ITU-R BT.1358 (HD0)

2.4 Dual channel video scalers

I Horizontal and vertical down-scaling and up-scaling to randomly sized windows

I Horizontal up-down scaling

N Linear horizontal scaling ratio down to ¹⁄₅₁₂and up to 1024 limited by transfer data

rates

N Horizontal integer pre-scaler with range 1 to ¹⁄₁₂₈

N Horizontal VPD ﬁnal scaler for down-scaling by ¹⁄_7.999to up-scaling by factor 1024

SAA7162E_SDS_2

Product short data sheet

Rev. 02 — 13 August 2007

2 of 18

SAA7162E

NXP Semiconductors

PCI Express based dual channel audio and video decoder

I Vertical up-down scaling

N Linear phase accurate vertical scaling ratio down to 64 and up to 1024 limited by

transfer data rates

N Two separate 4-tap programmable polyphase ﬁlters for luminance (Y) and

chrominance (U or V) data streams optimized for STV and HDTV

N EDGI scale algorithm for areas with detected edges

N Edge detector controlled mixing of 4-tap polyphase interpolator results and EDGI

results enabling a maximum of performance with a minimize scale artefacts

I Two separated tasks processing pipes for active video (task A) and raw VBI (task B)

regions

I Linear zooming of free programmable picture fragment

I Programmable panorama scaling

I Versatile BCS adjustment for scaled video outputs

I Optional DCI via programmable LUT

I Optional intraﬁeld de-interlacing (EDGI)

I Optional CTI

I Optional RGB matrix and a programmable gamma correction

2.5 Dual channel advanced signal processing

I Support for letter box detection (black bar detection) via histogram evaluation

I Approximate noise level estimation of video input signal

I Status register and programmable status change output (interrupt) to minimize

software overhead

I Support for RMS noise level estimation via histogram evaluation

2.6 Dual channel VBI slicing

I Versatile VBI data slicer (slicer, clock regeneration and data byte synchronization) for

all common text and data services

N WST525/WST625, Gemstar2x and Gemstar1x/VPS, VITC525/VITC625,

CC525/CC625, WSS525 (CGMS)/WSS625, CGMS-A (line 41) of 480p (HD0),

CGMS (line 41) of 576p (HD0), US NABTS/European teletext (FC) and

MOJI (Japanese)

I Sliced VBI data can be transferred as ANC data on the digital video output ports (1, 2,

4 or 5) or on the parallel host port

I I²C-bus read-back access to data of following VBI data standards

N Closed caption (CC525 and CC625), CGMS (WSS525), WSS625, Gemstar1x,

Gemstar2x and VPS

I Optionally, raw data with dedicated gain and offset adjustment is available for software

decoding

SAA7162E_SDS_2

Product short data sheet

Rev. 02 — 13 August 2007

3 of 18

SAA7162E

NXP Semiconductors

PCI Express based dual channel audio and video decoder

2.7 Digital peripheral interfaces

I Digital video input ports of 50 pins usable for maximum clock rates up to 75 MHz

N Five independent standard TV (ITU-R BT.656 and VMI) 8-bit or 10-bit input

streams

N Two STV/HDTV 16-bit input streams

N One STV/HDTV 20-bit input stream

N One STV/HDTV 24-bit (RGB) input stream

N Four TS or PS 8-bit input streams

I Selectable video input streaming standards

N STV/HDTV video in ITU-R BT.656 representation, either 8-bit, 10-bit, 16-bit or

20-bit format Y-C_B-C_R4 : 2 : 2

N STV/HDTV video in VMI representation, either 8-bit, 10-bit, 16-bit or 20-bit format

N Optionally, STV/HDTV 24-bit (RGB) input stream converted to YUV 4 : 2 : 2 via

internal programmable RGB/YUV matrix

I A digital video output port of 50 pins usable for maximum clock rates up to 75 MHz

N Four independent TV streams [STV (ITU-R BT.656 (8-bit or 10-bit) or VMI (8-bit))

and STV/HDTV (16-bit)]

N Four independent standard TV (ITU-R BT.656, VMI) 8-bit or 10-bit output streams

N Two STV/HDTV 16-bit output streams

N Two STV/HDTV 20-bit output streams

I Selectable video output streaming standards

N STV/HDTV video in ITU-R BT.656 representation, either 8-bit, 10-bit, 16-bit or

20-bit format Y-C_B-C_R4 : 2 : 2, optional with included sliced VBI data and/or audio

data

N STV/HDTV video in VMI representation, either 8-bit, 10-bit, 16-bit or 20-bit format

I One serial input port for infrared transceivers supporting RC5 and RC6 transmission

standards

I One serial output port for infrared transmitter adjustable to all common transmission

standards

2.8 Analog audio acquisition

I Differential inputs of analog SSIF

N Two differential SSIF signal inputs connectable to internal digital IF via simple post

ﬁlter

or

N Two single ended SSIF signal inputs connectable to conventional tuners (TV and

FM)

I Sound processing channels with automatic signal clamping and signal amplifying

adjustment to a high quality 10-bit CMOS ADC with 24.576 MHz sample frequency

I Three stereo analog audio baseband inputs with four serial sigma-delta 16-bit high

resolution audio ADC

I Two stereo analog baseband outputs with ﬁlter stream stereo DACs

I Integrated analog audio pass-through (support for analog audio loopback cable to

sound card)

SAA7162E_SDS_2

Product short data sheet

Rev. 02 — 13 August 2007

4 of 18

SAA7162E

NXP Semiconductors

PCI Express based dual channel audio and video decoder

2.9 TV sound decoder

I All standards TV stereo or mono sound decoder: BTSC, EIAJ, NICAM, FM A2 and AM

I dbx-TV noise reduction decoding for BTSC systems

I FM radio stereo decoding

I Automatic sound standard detection

I Automatic decoding for stereo and dual

2.10 Digital peripheral audio interfaces

I Two SPDIF inputs and two 24-bit SPDIF outputs (according to IEC 60958-3 and

TTL compliant only) with 32 kHz, 44.1 kHz or 48 kHz

I Five I²S-bus inputs and two 24-bit I²S-bus outputs for up to 4 channels with 32 kHz,

44.1 kHz or 48 kHz

I Two inputs of external audio reference clock of 256 × f_sor 384 × f_s

I Two outputs of audio output master clock (512 × f_s, 256 × f_sor 128 × f_sselectable)

I Audio output sampling clock can be locked to video frame rate (constant number of

audio samples per frame)

2.11 Audio feature processing

I Four stereo SRCs from 32 kHz, 44.1 kHz or 48 kHz to 32 kHz, 44.1 kHz or 48 kHz

I Volume, balance, bass and treble control

I Incredible Mono and Incredible Stereo

I AVL

I Optional generation of a frame locked audio master clock to support a constant

number of audio clocks per video ﬁeld

2.12 Programming ports

I PHI; byte oriented programming interface for fast access of modern microcontroller in

future oriented PC TV applications

N Fast alternative to I²C-bus based general control

N Supports fast access to programming register (up to 8 MHz)

N Supports 8-bit data and 16-bit address interface

N Data read from VBI slicer (FIFO) for teletext decoding

N IRQ register support

I Four I²C-bus interfaces

N Support register access with 100 kHz and 400 kHz bit rate

N I²C-bus master usable PHI port to program additional system devices like tuner,

MPEG encoder and decoder

N I²C-bus slave, usable to support a programming interface for application systems

with limiting controller performance

N Two ‘silent’ I²C-bus ports to support noise sensitive devices

I One SPI master interface for controlling external peripherals like MPEG encoder

I 28 GPIO pins, partly shared with interrupt and chip select functions

SAA7162E_SDS_2

Product short data sheet

Rev. 02 — 13 August 2007

5 of 18

SAA7162E

NXP Semiconductors

PCI Express based dual channel audio and video decoder

2.13 PCI Express interface

I Compliant to PCI Express Base Speciﬁcation 1.0a

I The PCI Express circuit supports isochronous data trafﬁc intended for uninterrupted

transfer of streaming data like video streaming

N x1 PCI Express endpoint (2.5 Gbit/s)

N Data and clock recovery from serial stream

N Low jitter and BER

I Type 0 conﬁguration space header

N 64-bit addressing

N Single BAR; programmable address range of 17 bits, 18 bits, 19 bits or 20 bits

dependent on application requirements

I PCI Express capabilities

N 128 bytes write packet size and 64 bytes read packet size

N MSI support

N Software directed power management of four device power states (D0 to D3)

N Active state power management of link states

N Vendor speciﬁc capability for VC1 support; after reset VC1 isochronous capability

is disabled

2.14 DMA support

I DMA write support

N One DMA write channel for MSI

N 12 DMA write channels for audio and video streaming: Maximum 8 software buffers

per DMA channel or maximum buffer size of 2 MB

N Round-robin arbitration between DMAs; support for graceful overﬂow recovery if

PCI Express bandwidth is not provided in the required amount

I DMA read support

N One DMA read channel for reading from page table(s); required for

virtual-to-physical address translation of the streaming DMAs

2.15 General features

I Only a single crystal of 24.576 MHz or 32.11 MHz is required for all standards

I Software controlled power saving Standby modes

I Boundary scan test circuit according to ‘IEEE Std. 1149.1’

SAA7162E_SDS_2

Product short data sheet

Rev. 02 — 13 August 2007

6 of 18

SAA7162E

NXP Semiconductors

PCI Express based dual channel audio and video decoder

3. Quick reference data

Table 1.

Symbol

Quick reference data

Parameter

Conditions

Min

Typ

Max Unit

V_{DDDI0(1V8)_A}

V_{DDDI3(1V8)_B}

V_{DDDM0(1V8)_A}

V_{DDDM0(1V8)_B}

V_DDDI1(1V2)

digital internal supply voltage 0 (1.8 V) for unit A

digital internal supply voltage 3 (1.8 V) for unit B

memory digital supply voltage 0 (1.8 V) for unit A

memory digital supply voltage 0 (1.8 V) for unit B

digital internal supply voltage 1 (1.2 V)

1.65 1.8

1.95

1.3

V

W

1.1

3.0

1.2

3.3

V_DDDI2(1V2)

digital internal supply voltage 2 (1.2 V)

1.3

V_{DDD(PCI0)(1V2)}

V_{DDD(PCI1)(1V2)}

V_{DDDE0(3V3)_A}

V_DDDE2(3V3)

PCI Express 0 digital supply voltage (1.2 V)

PCI Express 1 digital supply voltage (1.2 V)

digital extend supply voltage 0 (3.3 V) for unit A

digital extend supply voltage 2 (3.3 V)

1.3

3.6

V_DDDE3(3V3)

digital extend supply voltage 3 (3.3 V)

3.6

V_DDDE4(3V3)

digital extend supply voltage 4 (3.3 V)

3.6

V_DDDE5(3V3)

digital extend supply voltage 5 (3.3 V)

3.6

V_{DDDE6(3V3)_B}

V_{DDD(PCI0)(1V0)}

V_{DDD(PCI1)(1V0)}

digital extend supply voltage 6 (3.3 V) for unit B

PCI Express 0 digital supply voltage (1.0 V)

PCI Express 1 digital supply voltage (1.0 V)

3.6

0.95 1.0

1.05

3.5

V_{DDA(DAC1_3V3)_A}DAC 1 3.3 V analog supply voltage for unit A

V_{DDA(DAC2_3V3)_A}DAC 2 3.3 V analog supply voltage for unit A

V_{DDA(PLL)(3V3)_A}PLL analog supply voltage (3.3 V) for unit A

3.1

3.3

3.5

V_{DDA0(3V3)_A}

V_{DDA1(3V3)_A}

V_{DDA2(3V3)_A}

analog supply voltage 0 (3.3 V) for unit A

analog supply voltage 1 (3.3 V) for unit A

analog supply voltage 2 (3.3 V) for unit A

3.5

V_{DDA(ADC)(3V3)_A}ADC analog supply voltage (3.3 V) for unit A

V_{DDA(DAC1_3V3)_B}DAC 1 3.3 V analog supply voltage for unit B

V_{DDA(DAC2_3V3)_B}DAC 2 3.3 V analog supply voltage for unit B

V_{DDA(PLL)(3V3)_B}PLL analog supply voltage (3.3 V) for unit B

3.5

V_{DDA0(3V3)_B}

V_{DDA1(3V3)_B}

V_{DDA2(3V3)_B}

analog supply voltage 0 (3.3 V) for unit B

analog supply voltage 1 (3.3 V) for unit B

analog supply voltage 2 (3.3 V) for unit B

3.5

V_{DDA(ADC)(3V3)_B}ADC analog supply voltage (3.3 V) for unit B

3.5

V_{DDA(PCI0)(3V3)}

V_{DDA(PCI1)(3V3)}

V_{DDA(1V8)_A}

PCI Express 0 analog supply voltage (3.3 V)

PCI Express 1 analog supply voltage (3.3 V)

analog supply voltage (1.8 V) for unit A

analog supply voltage (1.8 V) for unit B

3.5

1.65 1.8

1.95

4.2

V_{DDA(1V8)_B}

V_{DDA(OSC)(1V8)_A}oscillator analog supply voltage (1.8 V) for unit A

V_{DDA(OSC)(1V8)_B}oscillator analog supply voltage (1.8 V) for unit B

P_tot

total power dissipation

power

-

3.7

management

states; D0 for

typical application

SAA7162E_SDS_2

Product short data sheet

Rev. 02 — 13 August 2007

7 of 18

SAA7162E

NXP Semiconductors

PCI Express based dual channel audio and video decoder

Table 1.

Symbol

T_amb

Quick reference data …continued

Parameter

Conditions

Min

Typ

Max Unit

ambient temperature

0

-

70

°C

PCI Express link data rate

f_RXreceiver data rate

f_TXtransceiver data rate

10-bit ADCs (including analog clamp and gain stages)

-

2.5

-

Gbit/s

DLE_DC

ILE_DC

DC differential linearity error

DC integral linearity error

-

1

-

LSB

Analog video outputs (AVO_A1 and AVO_B1)

V_o(p-p)peak-to-peak output voltage

for normal video

levels 1 V (p-p);

75 Ω termination

-

1

-

V

10-bit DACs (ASIFO_AP, ASIFO_AN, AVO_AP, AVO_AN, ASIFO_BP, ASIFO_BN, AVO_BP and AVO_BN)

DLE_DC

ILE_DC

DC differential linearity error

DC integral linearity error

-

1

2

LSB

Analog audio inputs (AAIL_AB2, AAIR_AB2, AAIL_A1, AAIR_A1) and analog audio outputs (AAOL_A2, AAOR_A2,

AAOL_A1 and AAOR_A1)

V_i(nom)(rms)

V_i(max)(rms)

V_o(nom)(rms)

V_o(max)(rms)

nominal input voltage (RMS value)

maximum input voltage (RMS value)

nominal output voltage (RMS value)

maximum output voltage (RMS value)

-

200

-

mV

V

[1]

[2]

THD < 3 %

1

-

180

1

mV

V

-

[1] The analog audio inputs are supported by two input levels: 1 V (RMS) and 2 V (RMS), selectable independently per stereo input pair.

[2] Deﬁnition of levels and level setting:

a) The full-scale level for analog audio signals is 0.8 V (RMS). The nominal level at the digital crossbar switch is deﬁned at −15 dB (FS)

b) Nominal audio input levels: external, mono, V_i= 180 mV (RMS); −15 dB (FS)

4. Ordering information

Table 2.

Ordering information

Type number

Package

Name

Description

Version

SAA7162E

BGA756

plastic ball grid array package; 756 balls; body 35 × 35 × 1.75 mm

SOT875-1

SAA7162E_SDS_2

Product short data sheet

Rev. 02 — 13 August 2007

8 of 18

SAA7162E

NXP Semiconductors

PCI Express based dual channel audio and video decoder

5. Block diagram

PORT_6

SPDIF_B

I2S_IO_B

PORT_5

PORT_4

SAA7162E

SDA_SILENT_B

SCL_SILENT_B

2

I C-BUS SILENT

AVI_B10P

AVI_B10N

SI_AGC_B

LOGICAL AUDIO

AND VIDEO UNIT B

DIGITAL

IF

FGPI2/3

AVO_B

ASIF_B

DUAL

DAC

CONTROL

MUX

ADC

DAC

SIF DEMODULATOR

STEREO DECODER

CROSSBAR

AAI_B

I2S_B

SPDIF_I_B

DSP

AI1

AVI_B

DIGITAL

VIDEO

INPUT

VSYNC_B

MULTISTANDARD

DECODER

PORT_7

PORT_8

VIDEO

FRONT-END

VI1

COMPONENT

PROCESSING

SCALER

QUADRUPLE

ADC

AUDIO

AND

VBI SLICER

VIDEO

INPUT

CROSSBAR

DMA

AND

FIFO

MUX

MULTISTANDARD

DECODER

VIDEO

FRONT-END

AUX

VSYNC_A

AVI_A

COMPONENT

PROCESSING

QUADRUPLE

ADC

VI0

VBI SLICER

SCALER

SPDIF_I_A

I2S_AB

I2S_A

DIGITAL

VIDEO

INPUT

AAI_AB

AAI_A

AI0

SIF DEMODULATOR

STEREO DECODER

ADC

DAC

CROSSBAR

AAO_A

DSP

ASIF_A

AVO_A

DUAL

DAC

MUX

CONTROL

DIGITAL

IF

FGPI0/1

SI_AGC_A

AVI_A10P

AVI_A10N

LOGICAL AUDIO

AND VIDEO UNIT A

SDA_SILENT_A

SCL_SILENT_A

2

I C-BUS SILENT

IR

MESSAGE

SIGNAL

PORT_1

PORT_2

I2S_IO_A

SPDIF_A

PORT_3

INTERRUPT

MEMORY

MANAGEMENT

UNIT

I2C_B

I2C_A

PHI

GPIO

SPI

PERIPHERAL

CONTROL

INTERFACE

PCI EXPRESS

INTERFACE

XTAL

JTAG

TEST

POWER

001aad710

JTAG

POWER

PCI_E

Fig 1. Block diagram of SAA7162E

SAA7162E_SDS_2

Product short data sheet

Rev. 02 — 13 August 2007

9 of 18

SAA7162E

NXP Semiconductors

PCI Express based dual channel audio and video decoder

6. Limiting values

Table 3.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

+2.5

+4.5

1.15

+1.7

Unit

V

V_{DDA(1V8)_A}

V_{DDA(1V8)_B}

analog supply voltage (1.8 V) for unit A

analog supply voltage (1.8 V) for unit B

−0.5

0.85

−0.5

−40

V_{DDA(OSC)(1V8)_A}oscillator analog supply voltage (1.8 V) for unit A

V_{DDA(OSC)(1V8)_B}oscillator analog supply voltage (1.8 V) for unit B

V_{DDDI0(1V8)_A}

V_{DDDI3(1V8)_B}

V_{DDDM0(1V8)_A}

V_{DDDM0(1V8)_B}

digital internal supply voltage 0 (1.8 V) for unit A

digital internal supply voltage 3 (1.8 V) for unit B

memory digital supply voltage 0 (1.8 V) for unit A

memory digital supply voltage 0 (1.8 V) for unit B

V_{DDA(DAC1_3V3)_A}DAC 1 3.3 V analog supply voltage for unit A

V_{DDA(DAC2_3V3)_A}DAC 2 3.3 V analog supply voltage for unit A

V_{DDA(PLL)(3V3)_A}PLL analog supply voltage (3.3 V) for unit A

V_{DDA0(3V3)_A}

V_{DDA1(3V3)_A}

V_{DDA2(3V3)_A}

analog supply voltage 0 (3.3 V) for unit A

analog supply voltage 1 (3.3 V) for unit A

analog supply voltage 2 (3.3 V) for unit A

V_{DDA(ADC)(3V3)_A}ADC analog supply voltage (3.3 V) for unit A

V_{DDA(DAC1_3V3)_B}DAC 1 3.3 V analog supply voltage for unit B

V_{DDA(DAC2_3V3)_B}DAC 2 3.3 V analog supply voltage for unit B

V_{DDA(PLL)(3V3)_B}PLL analog supply voltage (3.3 V) for unit B

V_{DDA0(3V3)_B}

V_{DDA1(3V3)_B}

V_{DDA2(3V3)_B}

analog supply voltage 0 (3.3 V) for unit B

analog supply voltage 1 (3.3 V) for unit B

analog supply voltage 2 (3.3 V) for unit B

V_{DDA(ADC)(3V3)_B}ADC analog supply voltage (3.3 V) for unit B

V_{DDA(PCI0)(3V3)}

V_{DDA(PCI1)(3V3)}

V_{DDDE0(3V3)_A}

V_DDDE2(3V3)

V_DDDE3(3V3)

V_DDDE4(3V3)

V_DDDE5(3V3)

V_{DDDE6(3V3)_B}

V_{DDD(PCI0)(1V0)}

V_{DDD(PCI1)(1V0)}

V_DDDI1(1V2)

V_DDDI2(1V2)

V_{DDD(PCI0)(1V2)}

V_{DDD(PCI1)(1V2)}

V_i

PCI Express 0 analog supply voltage (3.3 V)

PCI Express 1 analog supply voltage (3.3 V)

digital extend supply voltage 0 (3.3 V) for unit A

digital extend supply voltage 2 (3.3 V)

digital extend supply voltage 3 (3.3 V)

digital extend supply voltage 4 (3.3 V)

digital extend supply voltage 5 (3.3 V)

digital extend supply voltage 6 (3.3 V) for unit B

PCI Express 0 digital supply voltage (1.0 V)

PCI Express 1 digital supply voltage (1.0 V)

digital internal supply voltage 1 (1.2 V)

digital internal supply voltage 2 (1.2 V)

PCI Express 0 digital supply voltage (1.2 V)

PCI Express 1 digital supply voltage (1.2 V)

input voltage

V_DD+ 0.5 V

T_stg

storage temperature

+125

°C

SAA7162E_SDS_2

Product short data sheet

Rev. 02 — 13 August 2007

10 of 18

SAA7162E

NXP Semiconductors

PCI Express based dual channel audio and video decoder

Table 3.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

T_amb

Parameter

Conditions

Min

Max

70

Unit

°C

V

ambient temperature

electrostatic discharge voltage

0

-

[1]

[2]

V_esd

human body model

machine model

±2000

±200

-

V

[1] Class 2 according to JESD22-A114-D.

[2] Class B according to EIA/JESD22-A115-A.

SAA7162E_SDS_2

Product short data sheet

Rev. 02 — 13 August 2007

11 of 18

SAA7162E

NXP Semiconductors

PCI Express based dual channel audio and video decoder

7. Package outline

BGA756: plastic ball grid array package; 756 balls; body 35 x 35 x 1.75 mm

SOT875-1

D

B

D

1

A

ball A1

index area

A

2

A

E

1

A

1

detail X

C

e

1

y

C

1

y

M

v

C A

C

B

b

e

1/2 e

w

AP

AN

AM

AK

AH

AF

AD

AB

Y

AL

AJ

AG

AE

AC

AA

W

U

e

V

e

2

T

R

P

1/2 e

N

M

L

K

J

H

G

F

E

D

C

B

A

1

3

5

7

9

11 13 15 17 19 21 23 25 27 29 31 33

X

2

4

6

8 10 12 14 16 18 20 22 24 26 28 30 32 34

shape

optional (4×)

0

10

scale

20 mm

DIMENSIONS (mm are the original dimensions)

A

UNIT

A

1

A

2

b

D

E

e

1

e

2

v

w

y

1

max

0.6 1.85 0.7

0.4 1.60 0.5

35.2 30.75 35.2 30.75

34.8 29.75 34.8 29.75

mm 2.45

1

33

33 0.25 0.1

0.2 0.35

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

04-11-29

04-12-06

SOT875-1

- - -

MS-034

Fig 2. Package outline SOT875-1 (BGA756)

SAA7162E_SDS_2

Product short data sheet

Rev. 02 — 13 August 2007

12 of 18

SAA7162E

NXP Semiconductors

PCI Express based dual channel audio and video decoder

8. Abbreviations

Table 4.

Acronym

ADC

AGC

ANC

AVL

Abbreviations

Description

Analog-to-Digital Converter

Automatic Gain Control

Ancillary

Automatic Volume Levelling

Base Address Register

Brightness Contrast Saturation

Bit Error Rate

BAR

BCS

BER

BTSC

CC

Broadcast Television Systems Committee

Closed Caption

CGMS

CMOS

CTI

Copy Generation Management System

Complementary Metal-Oxide Semiconductor

Color Transient Improvement

Color Video Blanking Signal

Digital-to-Analog Converter

Direct Current

CVBS

DAC

DC

DCI

Dynamic Contrast Improvement

Direct Memory Access

DMA

EDGI

EIAJ

FC

Edge Guided 2-tap Interpolation

Electronic Industries Association/JEDEC standard

Framing Code

FIFO

GPIO

HD0

First In First Out

General Purpose Input/Output

High Deﬁnition 0

HDTV

IF

High Deﬁnition TV

Intermediate Frequency

Interrupt ReQuest

IRQ

LLC

Line-Locked Clock

LUT

Look-Up Table

MPEG

Moving Picture Experts Group; the ofﬁcial name is ISO/IEC JTC1/SC29/WG11 (International

Organization for Standardization/International Electrotechnical Commission, Joint Technical

Committee 1, Subcommittee 29, Working Group 11)

MSI

Message Signal Interrupt

NABTS

NICAM

NTSC

PAL

North American Broadcast Text System

Near Instantaneous Companded Audio Multiplex

National Television Standards Committee

Phase Alternating Line

PC

Personal Computer

PCI

Peripheral Component Interconnect

Parallel Host port Interface

PHI

SAA7162E_SDS_2

Product short data sheet

Rev. 02 — 13 August 2007

13 of 18

SAA7162E

NXP Semiconductors

PCI Express based dual channel audio and video decoder

Table 4.

Acronym

PLL

Abbreviations …continued

Description

Phase-Locked Loop

Program Stream

PS

RC

Remote Control

RGB

RMS

SECAM

SPDIF

SPI

Red Green Blue

Root Mean Square

Sequentiel Couleur avec Memoire

Sony Philips Digital Interface

Serial Peripheral Interface

Sample Rate Converter

SRC

SSIF

STV

Second Sound Intermediate Frequency

Standard TV

TS

Transport Stream

TTL

Transistor-Transistor Logic

Vertical Blanking Interval

Virtual Channel

VBI

VC

VCR

VITC

VMI

Voltage-Controlled Resistor

Vertical Interval Time Code

Video Module Interface

Variable Phase Delay

VPD

VPS

VTR

WSS

WST

YUV

Video Programming System

Video Tape Recorder

Wide Screen Signalling

World Standard Teletext

luminance (Y) and chrominance (U and V)

9. Revision history

Table 5.

Revision history

Document ID

Release date

Data sheet status

Change notice

Supersedes

SAA7162E_SDS_2

Modiﬁcations:

20070813

Product short data sheet

-

SAA7162E_SDS_1

• The format of this data sheet has been redesigned to comply with the new identity

guidelines of NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

SAA7162E_SDS_1

20060710

Preliminary short data sheet -

-

SAA7162E_SDS_2

Product short data sheet

Rev. 02 — 13 August 2007

14 of 18

SAA7162E

NXP Semiconductors

PCI Express based dual channel audio and video decoder

10. Legal information

10.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

10.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

10.4 Licenses

10.3 Disclaimers

ICs with RC5 functionality

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Purchase of an NXP Semiconductors IC with RC5 functionality does not

convey an implied license under any trade secret, copyright, know-how or

patent right to use this IC in any RC5 application. A license under applicable

rights of Koninklijke Philips Electronics N.V. needs to be obtained via Philips

Intellectual Property and Standards (www.ip.philips.com), e-mail:

info.licensing@philips.com.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

ICs with Macrovision copyright protection technology

This product incorporates copyright protection technology that is protected

by method claims of certain U.S. patents and other intellectual property

rights owned by Macrovision Corporation and other rights owners. Use of

this copyright protection technology must be authorized by Macrovision

Corporation and is intended for home and other limited viewing uses only,

unless otherwise authorized by Macrovision Corporation. Reverse

engineering or disassembly is prohibited.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of a NXP Semiconductors product can reasonably be expected to

result in personal injury, death or severe property or environmental damage.

NXP Semiconductors accepts no liability for inclusion and/or use of NXP

Semiconductors products in such equipment or applications and therefore

such inclusion and/or use is at the customer’s own risk.

ICs with RC6 functionality

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Purchase of an NXP Semiconductors IC with RC6 functionality does not

convey an implied license under any trade secret, copyright, know-how or

patent right to use this IC in any RC6 application. A license under applicable

rights of Koninklijke Philips Electronics N.V. needs to be obtained via Philips

Intellectual Property and Standards (www.ip.philips.com), e-mail:

info.licensing@philips.com.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

SAA7162E_SDS_2

Product short data sheet

Rev. 02 — 13 August 2007

15 of 18

SAA7162E

NXP Semiconductors

PCI Express based dual channel audio and video decoder

10.5 Trademarks

Purchase of NXP ICs with digital dbx-TV noise reduction functionality

Licensed Chips — Purchase of NXP Semiconductors ICs with digital

dbx-TV noise reduction functionality for which on top of the IC price, the

related THAT Corporation royalty payment is paid to NXP Semiconductors,

includes a license from THAT Corporation to use the ICs in a BTSC

decoding application.

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

I²C-bus — logo is a trademark of NXP B.V.

Silicon Tuner — is a trademark of NXP B.V.

Unlicensed Chips — Purchase of NXP Semiconductors ICs with digital

dbx-TV noise reduction functionality for which on top of the IC price, no

related THAT Corporation royalty payment is paid to NXP Semiconductors,

is only permitted to parties who according to information supplied to NXP

Semiconductors by THAT Corporation, have a BTSC set-maker license

from THAT Corporation,

45 Summer street, Milford, Massachusetts 01757-1656, USA.

11. Contact information

For additional information, please visit: http://www.nxp.com

For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

SAA7162E_SDS_2

Product short data sheet

Rev. 02 — 13 August 2007

16 of 18

SAA7162E

NXP Semiconductors

PCI Express based dual channel audio and video decoder

Notes

SAA7162E_SDS_2

Product short data sheet

Rev. 02 — 13 August 2007

17 of 18

SAA7162E

NXP Semiconductors

PCI Express based dual channel audio and video decoder

12. Contents

1

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2

2.1

2.2

2.3

Analog video acquisition. . . . . . . . . . . . . . . . . . 1

Digital IF demodulator. . . . . . . . . . . . . . . . . . . . 2

Dual channel video signal processing and

decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Dual channel video scalers. . . . . . . . . . . . . . . . 2

Dual channel advanced signal processing . . . . 3

Dual channel VBI slicing. . . . . . . . . . . . . . . . . . 3

Digital peripheral interfaces . . . . . . . . . . . . . . . 4

Analog audio acquisition. . . . . . . . . . . . . . . . . . 4

TV sound decoder . . . . . . . . . . . . . . . . . . . . . . 5

Digital peripheral audio interfaces . . . . . . . . . . 5

Audio feature processing . . . . . . . . . . . . . . . . . 5

Programming ports. . . . . . . . . . . . . . . . . . . . . . 5

PCI Express interface. . . . . . . . . . . . . . . . . . . . 6

DMA support. . . . . . . . . . . . . . . . . . . . . . . . . . . 6

General features. . . . . . . . . . . . . . . . . . . . . . . . 6

2.4

2.5

2.6

2.7

2.8

2.9

2.10

2.11

2.12

2.13

2.14

2.15

3

4

5

6

7

8

9

Quick reference data . . . . . . . . . . . . . . . . . . . . . 7

Ordering information. . . . . . . . . . . . . . . . . . . . . 8

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 10

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 13

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14

10

Legal information. . . . . . . . . . . . . . . . . . . . . . . 15

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15

Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16

10.1

10.2

10.3

10.4

10.5

11

12

Contact information. . . . . . . . . . . . . . . . . . . . . 16

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 13 August 2007

Document identifier: SAA7162E_SDS_2


型号：	SAA7162E
厂家：	NXP
描述：	PCI Express based dual channel multistandard audio and video decoder 基于PCI Express双通道多标准音频和视频解码器解码器消费电路商用集成电路 PC
文件：	总18页 (文件大小：126K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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