TEA5761UK [NXP]
Low voltage single-chip FM stereo radio; 低电压的单芯片FM立体声收音机
| 型号： | TEA5761UK |
| 厂家： | 
NXP |
| 描述： | Low voltage single-chip FM stereo radio |
| 文件： | 总45页 (文件大小：230K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IMPORTANT NOTICE
Dear customer,
As from August 2nd 2008, the wireless operations of NXP have moved to a new company,
ST-NXP Wireless.
As a result, the following changes are applicable to the attached document.
●
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Company name - Philips Semiconductors is replaced with ST-NXP Wireless.
Copyright - the copyright notice at the bottom of each page “© Koninklijke Philips
Electronics N.V. 200x. All rights reserved”, shall now read: “© ST-NXP Wireless 200x -
All rights reserved”.
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Web site - http://www.semiconductors.philips.com is replaced with
http://www.stnwireless.com
Contact information - the list of sales offices previously obtained by sending an email
to sales.addresses@www.semiconductors.philips.com, is now found at
http://www.stnwireless.com under Contacts.
If you have any questions related to the document, please contact our nearest sales office.
Thank you for your cooperation and understanding.
ST-NXP Wireless
34ꢀ.80 7IRELESS
www.stnwireless.com
TEA5761UK
Low voltage single-chip FM stereo radio
Rev. 01 — 2 August 2006
Product data sheet
1. General description
The TEA5761UK is a single-chip electronically tuned FM stereo radio for low-voltage
applications with fully integrated IF selectivity and demodulation.
The radio is completely adjustment free and only requires a minimum of small and low
cost external components. The radio can tune to the European, US and Japanese
FM bands. The radio does not meet all of the requirements of EN55020; a trade off has
been implemented to achieve the following features.
2. Features
■ High sensitivity due to integrated low noise RF input amplifier
■ FM mixer for conversion of the US and Europe FM band (87.5 MHz to 108 MHz) and
Japanese FM band (76 MHz to 90 MHz) to IF
■ Preset tuning to receive Japanese TV audio up to 108 MHz, raster 100 kHz
■ Auto search tuning, 100 kHz grid
■ RF automatic gain control circuit
■ LC tuner oscillator operating with one low-cost chip inductor; no need for external
varicap
■ Fully integrated FM IF selectivity
■ Fully integrated FM demodulator; no external discriminator
■ Crystal oscillator at 32768 Hz, or external reference frequency at 32768 Hz
■ PLL synthesizer tuning system
■ IF counter; 7-bit output via the I2C-bus
■ Level detector; 4-bit level information output via the I2C-bus
■ Soft mute: signal dependent mute function
■ Mono/stereo blend: gradual change from mono to stereo, depending on signal; Stereo
Noise Cancelling (SNC)
■ Soft mute and SNC can be switched off via the I2C-bus
■ Adjustment-free stereo decoder
■ I2C-bus interface
■ Autonomous search tuning function
■ Standby mode
■ MPX output
■ One software programmable port
■ Interrupt flag
TEA5761UK
Philips Semiconductors
Low voltage single-chip FM stereo radio
3. Applications
■ FM stereo radio
4. Quick reference data
Table 1:
Quick reference data
VCCA = VCCD = 2.7 V; Tamb = 25 °C; unless otherwise specified.The listed parameters are valid when a crystal is used that
meets the requirements as stated in Table 31.
Symbol
General[1]
VCCA
Parameter
Conditions
Min
Typ
Max
Unit
analog supply voltage
digital supply voltage
analog supply current
2.5
2.5
10
-
2.7
2.7
14
2.0
-
3.6
3.6
16.5
6.0
20
V
VCCD
V
ICCA
Operating mode
Standby mode
Operating mode
Standby mode
mA
µA
µA
µA
ICCD
digital supply current
5
1
3.3
20
Reference voltage
VVREFDIG
IVREFDIG
Tamb
digital reference voltage for
V
VREFDIG ≤ VCC
1.65
-
1.8
0.5
-
VCCD
2.0
V
I2C-bus interface
digital reference supply
current
Operating mode;
VREFDIG = 1.65 V to VCCD
µA
°C
V
[1]
ambient temperature
VCD1 = 2.7 V; VVREFDIG = 1.8 V
−20
+85
FM overall system parameters
fi(FM)
FM input frequency
76
-
-
108
3.6
MHz
Vsens(EMF)
sensitivity EMF value
voltage
fRF = 76 MHz to 108 MHz; L = R;
∆f = 22.5 kHz; fmod = 1 kHz;
2.2
µV
(S+N)/N = 26 dB; TCdeem = 75 µs;
A-weighting filter; Baud = 300 Hz to 15 kHz
IP3in
in-band 3rd-order intercept ∆f1 = 200 kHz; ∆f2 = 400 kHz;
81
87
87
93
-
-
dBµV
dBµV
point related to VRFIN1-RFIN2
ftune = 76 MHz to 108 MHz; RFagc = off
IP3out
out-of-band 3rd-order
intercept point related to
VRFIN1-RFIN2
∆f1 = 4 MHz; ∆f2 = 8 MHz; ftune = 76 MHz
to 108 MHz; RFagc = off
[2]
S
selectivity
ftune = 76 MHz to 108 MHz
high-side: ∆f = +200 kHz
low-side: ∆f = −200 kHz
39
32
60
43
36
75
-
dB
dB
mV
-
VVAFL
VVAFR
left audio output voltage on VRF = 1 mV; L = R; ∆f = 22.5 kHz;
pin VAFL mod = 1 kHz; TCdeem = 75 µs
90
f
right audio output voltage on VRF = 1 mV; L = R; ∆f = 22.5 kHz;
60
75
90
mV
pin VAFR
fmod = 1 kHz; TCdeem = 75 µs
9397 750 13451
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 2 August 2006
2 of 44
TEA5761UK
Philips Semiconductors
Low voltage single-chip FM stereo radio
Table 1:
Quick reference data …continued
VCCA = VCCD = 2.7 V; Tamb = 25 °C; unless otherwise specified.The listed parameters are valid when a crystal is used that
meets the requirements as stated in Table 31.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
(S+N)/N(m) maximum signal-to-noise
ratio, mono
VRF = 1 mV; ∆f = 22.5 kHz; L = R;
53
57
-
dBA
f
mod = 1 kHz; TCdeem = 75 µs;
aud = 300 Hz to 15 kHz + A-weighted
B
filter
αcs
channel separation
VRF = 1 mV; ∆f = 75 kHz; including 9 %
pilot deviation; R = 0 and L = 1 or R = 1
and L = 0; fmod = 1 kHz; bit MST = 0;
bit SNC = 1; Baud = 300 Hz to 15 kHz
22
-
27
-
dB
%
THD
total harmonic distortion
VRF = 1 mV; ∆f = 75 kHz; fmod = 1 kHz;
0.4
1
measured (at pins VAFL and L = R; TCdeem = 75 µs; Baud = 300 Hz to
VAFR) 15 kHz
[1] Crystal influence not included.
[2] Low-side and high-side selectivity can be measured by changing the mixer LO injection from high-side to low-side.
5. Ordering information
Table 2:
Ordering information
Type number
Package
Name
Description
Version
TEA5761UK
WLCSP34 wafer level chip-size package; 34 bumps; 3.5 × 3.5 × 0.6 mm
NAU000
9397 750 13451
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 2 August 2006
3 of 44
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n.c.
i.c.
33 nF
GNDA
F2
GNDA
G2
VAFR TMUTE
MPXOUT
VAFL
F4
G3
G4
G5
G6
F6
FREQIN
XTAL
G1
F1
CRYSTAL
OSCILLATOR
X1
TEA5761UK
GAIN
STABILIZER
V
CCA E1
3.7
Ω
CD3
IF
FILTER
SOFT
MUTE
LIMITER
DEMODULATOR
IF COUNT
D2
33 nF
SDS
FM
antenna
LEVEL
ADC
10 nF
I/Q MIXER
1st FM
÷2
N1
MPX
DECODER
100 pF
I
ref
IF CENTER
FREQUENCY ADJUST
INTX
G7
27
pF
D1
RFIN1
GNDD
F7
E6
L1
120 nH
AGC
RFIN2 C1
47
pF
i.c.
33 nF
agc
C2
B1
GNDRF
CAGC
E7 CD2
mono
pilot
12 Ω
V
CCD
D7
prog. div out
ref. div out
D6 GNDD
2
I C-BUS
INTERFACE
TUNING SYSTEM
C7 GNDD
B7 SDA
SCL
A7
MUX
VCO
A2
SW PORT
A5
A4
A1
B2
A3
B4
A6
BUSENABLE
B6
VREFDIG
001aab486
LOOPSW
CPOUT
LO1
CD1
SWPORT
LO2
n.c.
10
nF
100 nF
10 kΩ
L2
39 nH
100 kΩ
33 nF
Fig 1. Block diagram
TEA5761UK
Philips Semiconductors
Low voltage single-chip FM stereo radio
7. Pinning information
7.1 Pinning
ball A1
index area
TEA5761UK
1
2
3
4
5
6
7
A
B
C
D
E
F
G
001aab488
Transparent top view
Fig 2. Pin configuration of WLCSP34 package
7.2 Pin description
Table 3:
Pin description
Symbol
LOOPSW
LO1
Pin
A1
A2
A3
A4
A5
A6
A7
B1
B2
B4
B6
B7
C1
C2
C7
D1
D2
D6
D7
E1
E6
E7
Description
synthesizer PLL loop filter switch output
local oscillator coil connection 1
local oscillator coil connection 2
VCO supply decoupling capacitor
software programmable port output
I2C-bus enable input
I2C-bus clock line input
RF AGC time constant capacitor
charge pump output of synthesizer PLL
not connected
LO2
CD1
SWPORT
BUSENABLE
SCL
CAGC
CPOUT
n.c.
VREFDIG
SDA
digital reference voltage for I2C-bus
I2C-bus data line input and output
RF input 2
RFIN2
GNDRF
GNDD
RFIN1
CD3
RF ground
digital ground
RF input 1
VCCA decoupling capacitor
digital ground
GNDD
VCCD
digital supply voltage
VCCA
analog supply voltage
i.c.
internally connected; leave open
VCCD decoupling capacitor
CD2
9397 750 13451
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 2 August 2006
5 of 44
TEA5761UK
Philips Semiconductors
Low voltage single-chip FM stereo radio
Table 3:
Symbol
XTAL
Pin description …continued
Pin
F1
Description
crystal oscillator input
GNDA
VAFL
F2
analog ground
F4
left audio output
i.c.
F6
internally connected; leave open
digital ground
GNDD
FREQIN
GNDA
n.c.
F7
G1
G2
G3
G4
G5
G6
G7
32.768 kHz reference frequency input
analog ground
not connected
MPXOUT
VAFR
FM demodulator MPX output
right audio output
TMUTE
INTX
soft mute time constant capacitor
interrupt flag output
8. Functional description
8.1 Low noise RF amplifier
The LNA input impedance together with the LC RF input circuit defines an FM band filter.
The gain of the LNA is controlled by the RF AGC circuit.
8.2 I/Q mixer 1st FM
The FM quadrature mixer converts FM RF (76 MHz to 108 MHz) to IF.
8.3 VCO
The LC tuned VCO provides the Local Oscillator (LO) signal for the FM quadrature mixer.
The VCO frequency range is from 150 MHz to 217 MHz. No external varactor is required.
8.4 Crystal oscillator
The crystal oscillator can operate with a 32.768 kHz clock crystal or via an external
32.768 kHz reference clock source connected to pin FREQIN. Selection between a
reference clock or a reference crystal can be done by software programming via the
I2C-bus. When a clock crystal is used, pin FREQIN must be left open-circuit, or when
external clocking is used, there should be no crystal connected to pin XTAL.
The temperature drift of 32.768 kHz clock crystals limits the operational temperature
range. The preferred crystal specifications are given in Table 31.
The crystal oscillator generates the reference frequency for:
• Synthesizer PLL tuning system
• Timing for the IF counter
• Free running frequency adjustment of the stereo decoder VCO
• Center frequency adjustment of the IF filters
9397 750 13451
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 2 August 2006
6 of 44
TEA5761UK
Philips Semiconductors
Low voltage single-chip FM stereo radio
8.5 PLL tuning system
The PLL synthesizer tuning system is suitable to operate with a 32.768 kHz reference
frequency generated by the crystal oscillator or a reference clock of 32.768 kHz fed into
the TEA5761UK. To tune the radio to the required frequency requires the PLL word to be
calculated and then programmed to the register. The PLL word is 14 bits long; see
Table 12 and Table 13. Calculation of this 14-bit word can be done as follows.
Formula for high-side injection:
4 × ( f RF + f IF
)
NDEC
=
(1)
(2)
--------------------------------------
f ref
Formula for low-side injection:
4 × ( f RF – f IF
)
NDEC
=
-------------------------------------
f ref
where:
NDEC = decimal value of PLL word
fRF = wanted tuning frequency (Hz)
fIF = intermediate frequency of 225 kHz
fref = reference frequency of 32.768 kHz
Example for receiving a channel at 100.1 MHz:
4 × (100.1 × 106 + 225 × 103)
NDEC
=
= 12246.704
(3)
------------------------------------------------------------------------
32768
The result found using Equation 1 or Equation 2 must always be rounded to the lowest
integer value. If rounded down to the lowest integer value of NDEC = 12246, the PLL word
becomes 2FD6h.
This value can be written to register FRQSET via the I2C-bus and the TEA5761UK will
then start an autonomous search at this frequency or go to a preset channel at this
frequency. When the application is built according to the application diagram (see
Figure 13) and with the preferred components, the PLL will settle to the new frequency
within 40 ms.
The PLL is triggered by writing to any one of the bytes FRQSETMSB, FRQSETLSB,
TNCTRL1, TNCTRL2, TESTBITS, TESTMODE.
Accurate validation of the PLL locking on the new frequency can take 40 ms. When a lock
is detected bit LD is set.
8.6 Band limits
The TEA5761UK can be switched to the Japanese FM band or to the US and Europe FM
band. Setting bit BLIM to logic 0 the band range is 87.5 MHz to 108 MHz; setting bit
BLIM to logic 1 selects the Japanese band range of 76 MHz to 90 MHz.
9397 750 13451
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 2 August 2006
7 of 44
TEA5761UK
Philips Semiconductors
8.7 RF AGC
Low voltage single-chip FM stereo radio
The RF AGC prevents overloading and limits the amount of intermodulation products
created by strong adjacent channels. The RF AGC is on by default and can be turned off
via the I2C-bus.
The TEA5761UK also has an in-band AGC to prevent overloading by the wanted channel.
The in-band AGC is always turned on.
8.8 Local or long distance receive
If bit LDX = 1, the LNA gain is reduced by 6 dB to prevent distortion when a transmitter is
very near. If bit LDX = 0, the LNA gain is normal to receive long distance (DX) stations.
8.9 IF filter
A fully integrated IF filter with a center frequency of 225 kHz is built-in.
8.10 FM demodulator
The FM quadrature demodulator has an integrated resonator to perform the phase shift of
the IF signal.
8.11 IF counter
The received signal is mixed to an IF of 225 kHz. The result of the mixing is counted. A
good IF count result indicates that the radio is tuned to a valid channel instead of an
image or a channel with much interference. The IF counter outputs a 7-bit count result via
the I2C-bus. The IF counter is continuously active and can be read at any time via the
I2C-bus. It also activates a flag when the IF count result is outside the IF count valid result
window; see Section 9.2.2. The IF count period can be set to 1.953 ms or 15.625 ms by
bit IFCTC.
8.12 Voltage level generator and analog-to-digital converter
The voltage level indicates the field strength received by the antenna. The voltage level is
analog-to-digital converted to a 4-bit word and output via the I2C-bus. The ADC level is
continuously active and can be read at any time via the I2C-bus. It also activates a flag
when the voltage level falls under a predefined selectable threshold. Bit LHSW allows
either large or small hysteresis steps to be chosen; see Table 21 and Section 9.2.3.
8.13 Mute
8.13.1 Soft mute
The low-pass filtered level voltage drives the soft mute attenuator at low RF input levels:
the audio output is faded and hence also the noise (curves 1 and 2 of Figure 12).
The soft mute function can also be toggled via the I2C-bus, using bit SMUTE.
9397 750 13451
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 2 August 2006
8 of 44
TEA5761UK
Philips Semiconductors
8.13.2 Hard mute
Low voltage single-chip FM stereo radio
The audio outputs VAFL and VAFR can be hard muted by bit MU in byte TNCTRL2 which
means they are put into 3-state. This can also be done by setting bits Left Hard Mute
(LHM) or Right Hard Mute (RHM) in byte TESTBITS, which allows either one or both
channels to be muted and forces the TEA5761UK to Mono mode. When the TEA5761UK
is in Standby mode the audio outputs are hard muted.
8.13.3 Audio frequency mute
The audio signal is muted by setting bit AFM of the TNCTRL1 register to logic 1. In the
soft mute attenuator the audio signal is blocked and so pins VAFL and VAFR will be at
their DC biasing point with no signal.
The audio is automatically muted during a preset as shown in the flowchart of Figure 3.
When the audio must be muted during Search mode, it is done by setting bit AFM to
logic 1 before the search action and resetting it to logic 0 afterwards.
Table 4:
Specification of Mute modes
Mute mode
Bit
MPX output
VAFL output (left)
Impedance State
VAFR output (right)
Impedance State
Impedance State
Audio frequency mute AFM = 1
500 Ω
500 Ω
500 Ω
500 Ω
3-state
muted
muted
audio
audio
muted
50 Ω
muted
muted
muted
50 Ω
muted
Hard mute
MU = 1
3-state
3-state
50 Ω
3-state
50 Ω
muted
Left hard mute
Right hard mute
Standby mute
Soft mute
LHM = 1
RHM = 1
PUPD = 0
SMUTE = 1
mono audio
muted
mono audio 3-state
muted 3-state
3-state
muted
RF level sensitive audio level; has no influence on mute or output impedance
8.14 MPX decoder
The PLL stereo decoder is adjustment free. It can be switched to mono via the I2C-bus.
8.15 Signal dependent mono/stereo blend (stereo noise cancellation)
If the RF input level decreases, the MPX decoder blends from stereo to mono to limit the
output noise. The continuous mono-to-stereo blend can also be programmed via the
I2C-bus to an RF level dependent switched mono-to-stereo transition. Stereo noise
cancellation can be switched off via the I2C-bus by bit SNC.
8.16 Software programmable port
The software programmable port (CMOS output) can be addressed via the I2C-bus:
• Bit SWPM = 1: port functions as the output for bit FRRFLAG.
• Bit SWPM = 0: port outputs the level corresponding to bit SWP.
In Test mode, the software port outputs signals according to Table 23. Test mode is
selected by setting bit TM of byte TESTMODE to logic 1.
The programmed output status of the software port remains, independent of bit PUPD;
see Section 8.17.
9397 750 13451
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 2 August 2006
9 of 44
TEA5761UK
Philips Semiconductors
Low voltage single-chip FM stereo radio
8.17 Standby mode
The radio can be put into Standby mode by Power-Up / Power-Down bit PUPD. In this
mode, the FM part can be turned off. The TEA5761UK is still accessible via the I2C-bus
but takes only very low power from the supply. In Standby mode, the audio outputs are
hard muted.
When the supply voltages VCCA and VCCD are made 0 V and VREFDIG = HIGH, all inputs
and outputs, the audio outputs and the reference clock input are in high-impedance state.
The power supplies can be switched on in any order.
8.18 Power-on reset
After start-up of VCCA and VCCD a power-on reset circuit will generate a reset pulse and
the registers will be set to their default values. The power-on reset is effectively generated
by VCCD
.
At power-on reset, the mute is set and all other bits are set to the reset value as given in
Table 9. To initialize the TEA5761UK all bytes have to be transferred.
8.19 I2C-bus interface
The I2C-bus interface operates with a maximum clock frequency of 400 kHz.
When, during operation, the signal on pin BUSENABLE is toggled, the device will not
generate an I2C-bus acknowledge bit on the first following I2C-bus transmission. It is then
necessary to send either the I2C-bus address two times prior to the complete transmission
or send the complete I2C-bus transmission twice. After this, the I2C-bus communication is
restored in the normal behavior. Now an I2C-bus acknowledge is generated on each
transmitted byte again.
8.20 Auto search and Preset mode
8.20.1 Search mode
In Search mode the IC can search channels automatically; see Figure 3.
When the INTX signal is used as an interrupt to the microcontroller to indicate a search
stop, the INTMSK register must be reset and only bit FRRMSK must be set. In this way
the microcontroller will only be interrupted when the search or preset algorithm is ready.
Search mode is initiated by setting bit SM in byte FRQSETMSB to logic 1. The search
direction is set by bit SUD; bit SUD = 0 (search down), bit SUD = 1 (search up). The tuner
starts searching at the frequency from where it is or at a start frequency set in bytes
FRQSETLSB and FRQSETMSB. The Search Stop Level (SSL) bits define the field
strength level at which a desired channel is detected. The tuner will stop on a channel with
a field strength equal to or higher than this reference level and then checks the IF
frequency; when both are valid, the search stops. If the level check or the IF count fails,
the search continues. If no channels are found, the TEA5761UK stops searching when it
has reached the band limit, setting bit BLFLAG HIGH. A search always stops when the
FRRFLAG is set and on the occurrence of a hardware interrupt, this procedure is shown in
Figure 3.
9397 750 13451
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 2 August 2006
10 of 44
TEA5761UK
Philips Semiconductors
Low voltage single-chip FM stereo radio
The search algorithm can stop at a frequency that is offset from the IF by up to a
maximum of 12 kHz. The maximum offset can be limited to 8 kHz by applying a preset.
For optimum tuning, it is recommended that a preset is applied after a search and when
the found frequency has an offset that is above 8 kHz.
After this interrupt the TEA5761UK will not update the tuner registers INTREG, FRQCHK
and TUNCHK for a period of 15 ms. The state of the TEA5761UK can be checked by
reading registers INTREG, FRQCHK and TUNCHK. Table 5 shows the possible states of
these registers after an auto search.
8.20.2 Preset mode
A preset occurs by setting bit SM to logic 0 and writing a frequency to register FRQSET.
The tuner jumps to the selected frequency and sets bit FRRFLAG when it is ready.
After this interrupt the TEA5761UK will not update the tuner registers INTREG, FRQCHK
and TUNCHK for a period of 15 ms. The state of the TEA5761UK can be checked by
reading registers INTREG, FRQCHK and TUNCHK. Table 5 shows the possible states
after a preset.
Table 5:
Bit
Tuner truth table
Comment
IFFLAG BLFLAG FRRFLAG
0
0
0
if pin INTX = LOW and bits IFMSK, LEVMSK, FRRMSK and
BLMSK were set, then this cannot occur
0
0
0
0
1
1
1
0
1
channel found during search; bits BLMSK and FRRMSK are set
not a valid combination
channel found and the band limit has been reached during a
search; bits BLMSK and FRRMSK are set
1
1
0
0
0
1
not possible during a preset or a search
a preset or search has been done and the wanted channel has
a valid RSSI level but the IF count fails; if bit AHLSI = 1, then bit
HLSI must be toggled and a new PLL value must be
programmed
1
1
1
1
0
1
not a valid combination
band limit is reached during search; no valid channel found
9397 750 13451
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 2 August 2006
11 of 44
TEA5761UK
Philips Semiconductors
Low voltage single-chip FM stereo radio
start
during a preset mute is always active
search mode is default not muted
unless bit AFM is set or bit AHLSI is set
reset flags
set PLL frequency
wait for PLL to settle
false
level OK
set LEVFLAG
true
false
IF OK
true
false
AHLSI
true
false
search mode
true
false
search up
true
increment current_pll
by 100 kHz
decrement current_pll
by 100 kHz
false
band limit
true
BLFLAG = 0
FRRFLAG = 1
no mute
BLFLAG = 0
FRRFLAG = 1
mute
BLFLAG = 1
FRRFLAG = 1
no mute
001aab461
Fig 3. Flowchart auto search or preset
8.20.3 Auto high-side and low-side injection stop switch
When a channel is searched or a preset is done, reception can sometimes be improved
when Local Oscillator (LO) injection is done at the other side of the wanted channel.
Bit HLSI toggles the injection of the local oscillator from high-side (bit HLSI = 1) to
low-side (bit HLSI = 0). When bit HLSI is toggled, a new PLL setting must be sent to the
TEA5761UK.
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Low voltage single-chip FM stereo radio
When bit AHLSI is set to logic 1, the search or preset algorithm will stop after a channel
has a valid RSSI level check, but fails the IF count. The microcontroller can now respond
by toggling bit HLSI and sending a new PLL value to the tuner.
image on low-side
wanted channel
image on high-side
switch LO from high-side to low-side
001aab460
Fig 4. Switch LO from high-side injection to low-side injection using bit HLSI
8.20.4 Muting during search or preset
During a preset the tuner is always muted and is implemented by the algorithm.
A search is not muted by default unless bit AFM = 1 or bit AHLSI = 1.
When bit AHLSI = 1 and the tuner stops during a preset or a search because of a wrong
IF count, the tuner stays muted; this allows the microcontroller to switch LO injection mode
quietly and wait for the new result.
The tuner is always muted if bit AFM = 1 and is independent of a search or a preset. A
search can be muted by setting bit AFM to logic 1 before a search is initiated and resetting
it to logic 0 when the tuner is ready (only set bit FRRMSK when initiating a search or
preset).
All these mute actions are done by blocking the audio signal inside the soft mute
attenuator, so the audio output will keep its DC level and stay low-impedance i.e. 50 Ω (a
hard mute set by bit MU will cause a plop).
9. Interrupt handling
9.1 Interrupt register
The first two bytes of the I2C-bus register contain the interrupt masks and the interrupt
flags. A flag is set when it is a logic 1.
Table 6:
Bit
INTFLAG register- byte0R
7
6
5
4
3
2
1
0
Symbol
-
-
-
IFFLAG
LEVFLAG
-
FRRFLAG
BLFLAG
Table 7:
Bit
INTMSK register - byte0W or byte1R
7
6
5
4
3
2
1
0
Symbol
-
-
-
IFMSK
LEVMSK
-
FRRMSK
BLMSK
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Low voltage single-chip FM stereo radio
The interrupt flag register contains the flags set according to the behavior outlined in
Section 9.2. When these flags are set they can also cause pin INTX to go active
(hardware interrupt line) depending on the status of the corresponding mask bit in Table 7.
A logic 1 in the mask register enables the hardware interrupt for that flag.
Hence, it is conceivable that, with all the mask bits cleared, the software could operate in
a continuous polling mode that reads the interrupt flag register for any bits that may be
set.
Interrupt mask bits are always cleared after reading the first two bytes of the interrupt
register. This is to control multiple hardware interrupts; see Figure 5.
9.1.1 Interrupt clearing
The interrupt flag and mask bits are always cleared after:
• they have been read via the I2C-bus
• a power-on reset
9.1.2 Timing
The timing sequence for the general operation interrupts is shown in Figure 5 and shows
a read access of the interrupt register INTFLAG and a subsequent (though not
necessarily immediate) write to the mask register INTMSK. It also indicates the two key
timing points A and B1 or B2.
If an interrupt event occurs while the register is being accessed (after point A), it must be
held until after the mask register is cleared at the end of the read operation (point B2).
Point A is after the R/W bit has been decoded and point B2 is where the acknowledge has
been received from the master after the first two bytes have been sent.
The LOW time for the INTX line (tL) has a maximum value specified in Table 30. However,
it can be shorter if a read of the INTMSK and INTFLAG registers occurs within tL.
9.1.3 Reset
A reset can be performed at any time by a simple read of the interrupt registers (byte0R
and byte1R), which automatically clears the interrupt flags and masks.
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read access
INTFLAG
INTMSK
write access
INTMSK
FRQSETMSB
FRQSETLSB
data
device
S
device
S
R
ack 0R data ack 1R data ack
data
ack
W
ack 0W data ack 1W data ack 2W data ack
P
address
address
(2)
(1)
interrupt event
A
B
B
2
1
(3)
interrupt flag bit
interrupt mask bit
(4)
(6)
(5)
(5)
INTX
001aab464
(1) Interrupt events that occur outside of the region A to B1 or B2 set their respective flag bits in the normal way immediately and can thus trigger a hardware interrupt if the
mask bits are set.
(2) The blocking of interrupts is marked by the region A to B1 or B2, depending on the actual read cycle.
B1 is when only the INTFLAG register is read and a stop condition is received (only INTFLAG is read, so only this will be cleared).
B2 is when both registers are read and hence cleared; this is terminated by either an acknowledge or stop bit.
(3) Interrupt events that occur between A and B1 or B2 set their respective flags after the mask bits are cleared. This means that in this diagram an interrupt event occurred
in period A to B1 or B2, so after period A to B2 the flag goes to logic 1.
(4) All interrupt mask bits are cleared after the interrupt flag and mask registers are read.
(5) Software writes to the mask register and enables the required mask bits. Any flags currently set will then trigger a hardware interrupt.
(6) Pin INTX is set HIGH (inactive) after the interrupt flag and mask registers are read.
Fig 5. I2C-bus interrupt sequence, read and write operation
TEA5761UK
Philips Semiconductors
Low voltage single-chip FM stereo radio
9.2 Interrupt flags and behavior
9.2.1 Multiple interrupt events
If the interrupt mask register bit is set then the setting of an interrupt flag for that bit
causes a hardware interrupt (pin INTX goes LOW). If the event occurs again, before the
flag is cleared, then this does not trigger any further hardware interrupts until that specific
flag is cleared. However, two different events can occur in sequence and generate a
sequence of hardware interrupts. A second interrupt can be generated only after the
INTMSK byte is read, followed by a write as the first interrupt blocks the input of the INTX
one-shot generator.
If subsequent interrupts occur within the INTX LOW period then these do not cause the
INTX period to extend beyond its specified maximum period (see Section 9.3).
9.2.2 IF frequency flag
During automatic frequency search or preset, the FM part of the TEA5761UK performs a
check of the received IF frequency. If an incorrect IF frequency is received, it indicates a
detuning situation or the presence of either strong interferers or tuning to an image which
sets bit IFFLAG in the INTFLAG register. Also a preset to a channel with no signal may
result in a wrong IF count value and hence the setting of bit IFFLAG.
When a search or preset is finished, bit FRRFLAG will be set to indicate this and an
interrupt is generated. The microcontroller can now read the outcome of the registers
which will contain the IF count value and the IFFLAG status of the channel it is tuned to.
15 ms after the FRRFLAG flag has been set the IF counter will start to run continuously on
the tuned frequency and if the conditions for correct frequency are not met then this sets
bit IFFLAG in the interrupt register. When bit IFMSK is set this will also cause an interrupt.
Bit IFFLAG is cleared by reading byte0R, or by starting the tuning algorithm.
9.2.3 RSSI threshold flag
The RSSI level voltage reflects the field strength received by the antenna. The voltage
level is analog-to-digital converted to a 4-bit value and output via the I2C-bus. This 4-bit
level value can be compared to a threshold level (see Table 21). The level ADC (which
converts the analog value to digital) can be triggered to convert in two ways:
1. During a tuning step, which can be a search or a preset, it is triggered by these
algorithms and compares the level with the threshold set by bits SSL[1:0]. Bit
LEVFLAG is set if the RSSI level drops below the threshold level set by bits SSL[1:0];
see Table 15. The hardware interrupt is only generated if the corresponding mask bit
is set.
2. After a search or a preset, the threshold for comparison is switched to the hysteresis
level. The hysteresis level is set by the level bits and can be selected using bit LHSW
(see Table 21). Then it waits 15 ms and the level ADC starts to run automatically and
compares the level each 500 µs with this hysteresis level. Bit LEVFLAG is set if the
RSSI level drops below the threshold level set by the LH bits; the hardware interrupt is
only generated if the corresponding mask bit is set. Bit LHSW allows either a small or
a large hysteresis to be selected. When a search or preset is done with the ADC level
set to 3 then when the algorithm has finished, the threshold level is set to 0. Hence the
LEVFLAG will never be set.
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Low voltage single-chip FM stereo radio
Bit LEVFLAG is cleared when the interrupt register INTFLAG is read.
9.2.4 Frequency ready flag
The frequency ready flag bit FRRFLAG is set to logic 1 when the automatic tuning has
finished a search or preset. The description of this bit is given in Table 5. This bit is
cleared when the INTMSK register is read.
9.2.5 Band limit flag
The band limit bit BLFLAG is set to logic 1 when the automatic tuning has detected the
end of the tuning band or when the PLL cannot lock on a certain frequency. This bit is
described in Table 5. This bit is cleared when the INTMSK register is read.
9.3 Interrupt output
The interrupt line driver is a MOS transistor with a nominal sink current of 380 µA. It is
pulled HIGH by an 18 kΩ resistor connected to pin VREFDIG. The interrupt line can be
connected to one other similar device with an interrupt output and an 18 kΩ pull-up
resistor providing a wired-OR function. This allows any of the drivers to pull the interrupt
line LOW by sinking the current. When a flag is set and not masked it generates an
interrupt; see Figure 6.
V
CCA
(1)
flag
INTX
<10 ms
<10 ms
10 ms
10 ms
read clears INTX
(2)
read INTMSK
write
(3)
INTMSK
001aab489
(1) When flag is set, the next interrupts are blocked until INTMSK is read from or written to.
(2) Reading INTMSK clears flag, INTMSK and INTX.
(3) Writing INTMSK enables INTX.
Fig 6. Interrupt line behavior
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Low voltage single-chip FM stereo radio
10. I2C-bus interface
The I2C-bus interface is based on The I2C-bus specification, version 2.1 January 2000,
expanded by the following definitions.
10.1 Write and Read mode
S
BYTE 1
chip address
0010 0000
A
BYTE 2
byte0W
A
BYTE n
.....
A
BYTE 8
byte6W
NAK
P
R/W
0
xxxx xxxx
xxxx xxxx
xxxx xxxx
001aac341
Fig 7. Write mode
S
BYTE 1
A
BYTE 2
byte0R
A
BYTE n
.....
A
BYTE 17
byte15R
xxxx xxxx
A
P
chip address
0010 0000
R/W
1
xxxx xxxx
xxxx xxxx
001aac342
Fig 8. Read mode
Table 8:
Code
S
I2C-bus transfer description
Description
START condition
Byte 1
I2C-bus chip address (7 bits)
R/W = 0 for write action and R/W = 1 for read action
acknowledge (SDA = LOW)
data byte (8 bits)
A
Byte 2, etc.
NAK
P
non acknowledge (SDA = HIGH)
STOP condition
10.2 Data transfer
Structure of the I2C-bus:
• Slave transceiver
• Subaddresses not used
• Maximum LOW-level input voltage: VIL = 0.3 × VVREFDIG
• Minimum HIGH-level input voltage: VIH = 0.7 × VVREFDIG
Remark: The I2C-bus operates at a maximum clock rate of 400 kHz. It is not allowed to
connect the TEA5761UK to an I2C-bus operating at a higher clock rate.
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Low voltage single-chip FM stereo radio
Data transfer to the TEA5761UK:
• Bit 7 of each byte is considered the MSB and has to be transferred as the first bit of
the byte.
• The LSB indicates the write or read action.
• The data becomes valid byte-wise at the appropriate falling edge of the SCL clock.
• A STOP condition after any byte can shorten transmission times. When writing to the
transceiver by using the STOP condition before completion of the whole transfer:
– The remaining bytes will contain the old information.
– If the transfer of a byte is not completed the new bits will be used, but a new tuning
cycle will not be started.
I2C-bus activity:
• With bit PUPD the TEA5761UK can be switched in a low current Standby mode. The
I2C-bus is then still active.
• When the I2C-bus interface is deactivated, by making pin BUSENABLE LOW and
without programmed Standby mode, the TEA5761UK keeps its normal operation, but
is isolated from the I2C-bus lines.
• Bus traffic can be started 10 µs after activating the bus again by making
pin BUSENABLE HIGH.
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Low voltage single-chip FM stereo radio
SDA
t
f
t
BUF
t
r
t
SCL
P
P
S
Sr
t
SU;STO
t
t
t
t
t
SU;STA
HD;STA
SU;DAT
HD;DAT
HIGH
LOW
t
t
HO;BUSEN
SU;BUSEN
BUS
ENABLE
001aac796
tf = fall time of both SDA and SCL signals: 20 + 0.1 Cb < tf < 300 ns, where Cb = total capacitance on bus line in pF.
tr = rise time of both SDA and SCL signals: 20 + 0.1 Cb < tr < 300 ns, where Cb = total capacitance on bus line in pF.
tHD;STA = hold time (repeated) START condition. After this period, the first clock pulse is generated: > 600 ns.
tHIGH = HIGH period of the SCL clock: > 600 ns.
tSU;STA = setup time for a repeated START condition: > 600 ns.
tHD;DAT = data hold time: 300 < tHD;DAT < 900 ns.
Remark: 300 ns lower limit is added because the ASIC has no internal hold time for the SDA signal.
tSU;DAT = data setup time: tSU;DAT > 100 ns. If ASIC is used in a standard mode I2C-bus system, tSU;DAT > 250 ns.
tSU;STO = setup time for STOP condition: > 600 ns.
tBUF = bus free time between a STOP and a START condition: > 600 ns.
Cb = capacitive load of one bus line: < 400 pF.
tSU;BUSEN = bus enable setup time: tSU;BUSEN > 10 µs.
tHO;BUSEN = bus enable hold time: tHO;BUSEN > 10 µs.
Fig 9. Bus timing diagram
10.3 Register map
Table 9:
Register overview
Byte number
Byte name
Access
Reset value Reference
Read
0R
Write
INTFLAG
R
00h
00h
80h
00h
08h
D2h
-
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
1R
0W
1W
2W
3W
4W
INTMSK
R/W
R/W
R/W
R/W
R/W
R
2R
FRQSETMSB
FRQSETLSB
TNCTRL1
TNCTRL2
FRQCHKMSB
FRQCHKLSB
IFCHK
3R
4R
5R
6R
7R
R
-
8R
R
-
9R
LEVCHK
R
-
10R
5W
TESTBITS
R/W
00h
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TEA5761UK
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Low voltage single-chip FM stereo radio
Table 9:
Register overview …continued
Byte number
Byte name
Access
Reset value Reference
Read
11R
12R
13R
14R
15R
Write
6W
TESTMODE
MANID1
R/W
R
00h
40h
2Bh
57h
61h
Table 22
Table 24
Table 25
Table 26
Table 27
MANID2
R
CHIPID1
CHIPID2
R
R
10.4 Byte description
Table 10: INTFLAG - interrupt flag byte0R description
Bit
7 to 5
4
Symbol
-
Access Reset
Description
-
-
reserved
IFFLAG
LEVFLAG
R
R
0
0
1 = IF count is not correct
3
continuous checking of the RSSI level
1 = RSSI level has dropped below VSSL[1:0] − Vhys
during a tuning cycle (preset or search)
1 = RSSI level has dropped below VSSL[1:0]
-
2
1
0
-
-
-
FRRFLAG
BLFLAG
R
R
0
0
1 = tuner state machine is ready
1 = during a search the band limit has been reached or
time out
Table 11: INTMSK - interrupt mask byte1R and byte0W description
Bit
Symbol
-
Access Reset
Description
7 to 5
-
-
reserved
4
3
2
1
0
IFMSK
R/W
0
0
-
masks bit IFFLAG
masks bit LEVFLAG
reserved
LEVMSK R/W
-
-
FRRMSK R/W
BLMSK R/W
0
0
masks bit FRRFLAG
masks bit BLFLAG
Table 12: FRQSETMSB - frequency setting MSB byte2R and byte1W description
Bit
Symbol
Access Reset
Description
7
SUD
R/W
R/W
1
1 = search up
0 = search down
1 = Search mode
0 = Preset mode
6
SM
0
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Low voltage single-chip FM stereo radio
Table 12: FRQSETMSB - frequency setting MSB byte2R and byte1W description …continued
Bit
5
Symbol
FR13
FR12
FR11
FR10
FR09
FR08
Access Reset
Description
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
PLL frequency set bits
4
3
2
1
0
Table 13: FRQSETLSB - frequency setting LSB byte3R and byte2W description
Bit
7
Symbol
FR07
FR06
FR05
FR04
FR03
FR02
FR01
FR00
Access Reset
Description
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
0
1
0
0
1
0
PLL frequency set bits
6
5
4
3
2
1
0
Table 14: TNCTRL1 - tuner control register byte4R and byte3W description
Bit
7
Symbol
-
Access Reset
Description
-
0
reserved
6
PUPD0
R/W
power-up and power-down
1 = FM on
0
0
0 = FM off
5
4
3
2
1
0
BLIM
R/W
R/W
R/W
R/W
R/W
R/W
1 = Japanese FM band 76 MHz to 90 MHz
0 = US/Europe FM band 87.5 MHz to 108 MHz
1 = output pin SWPORT is bit FRRFLAG
0 = output pin SWPORT is bit SWP
1 = IF count time is 15.625 ms
0 = IF count time is 1.953 ms
1 = left and right audio muted
0 = audio not muted
SWPM
IFCTC
AFM
0
1
0
0
0
SMUTE
SNC
1 = soft mute on
0 = soft mute off
1 = stereo noise cancellation on
0 = stereo noise cancellation off
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Low voltage single-chip FM stereo radio
Table 15: TNCTRL2 - tuner control register byte5R and byte4W description
Bit
Symbol
Access Reset
Description
7
MU
R/W
R/W
1
1 = left and right audio hard mute
0 = no hard mute
6 to 5 SSL[1:0]
search stop level (see Table 21)
00 = ADC3
01 = ADC5
10
1
10 = ADC7
11 = ADC10
4
3
2
1
0
HLSI
MST
SWP
DTC
R/W
R/W
R/W
R/W
R/W
1 = high-side injection
0 = low-side injection
1 = forced mono
0
0 = stereo on
1 = pin SWPORT is HIGH
0 = pin SWPORT is LOW
1 = de-emphasis time constant = 50 µs
0 = de-emphasis time constant = 75 µs
0
1
AHLSI
1 = tuner will stop during search on failed IF count and
correct level
0
0 = tuner will search continuously
Table 16: FRQCHKMSB - frequency check register byte6R description
Bit
7
Symbol
-
Access Reset
Description
-
-
-
-
-
-
-
-
-
reserved
6
-
-
reserved
5
PLL13
PLL12
PLL11
PLL10
PLL09
PLL08
R
R
R
R
R
R
frequency found bit 13 (MSB)
frequency found bit 12
frequency found bit 11
frequency found bit 10
frequency found bit 9
frequency found bit 8
4
3
2
1
0
Table 17: FRQCHKLSB - frequency check register byte7R description
Bit
7
Symbol
PLL07
PLL06
PLL05
PLL04
PLL03
PLL02
PLL01
PLL00
Access Reset
Description
R
R
R
R
R
R
R
R
-
-
-
-
-
-
-
-
frequency found bit 7
frequency found bit 6
frequency found bit 5
frequency found bit 4
frequency found bit 3
frequency found bit 2
frequency found bit 1
frequency found bit 0 (LSB)
6
5
4
3
2
1
0
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Low voltage single-chip FM stereo radio
Table 18: IFCHK - tuner check register byte8R description
Bit
7
Symbol
IF6
Access Reset
Description
R
R
R
R
R
R
R
R
-
-
-
-
-
-
-
-
IF count bit 6 (MSB)
IF count bit 5
6
IF5
5
IF4
IF count bit 4
4
IF3
IF count bit 3
3
IF2
IF count bit 2
2
IF1
IF count bit 1
1
IF0
IF count bit 0 (LSB)
1 = PLL tuning time out
0 = PLL has settled
0
TUNTO
Table 19: LEVCHK - tuner check register byte9R description
Bit
7
Symbol
LEV3
LEV2
LEV1
LEV0
LD
Access Reset
Description
R
R
R
R
R
-
-
-
-
-
level count bit 3 (MSB)
level count bit 2
level count bit 1
level count bit 0 (LSB)
1 = PLL is locked
0 = PLL is not locked
1 = Pilot detected
0 = no Pilot detected
reserved
6
5
4
3
2[1]
STEREO
R
-
1
0
-
-
-
-
-
-
reserved
[1] This bit does not switch the radio from mono to stereo, this depends on the RF input level as shown in
sections ‘Mono stereo blend’ and Mono stereo switched’ in Table 33.
Table 20: TESTBITS - test bits register byte10R and byte5W description
Bit
Symbol
Access Reset
Description
7
LHM
R/W
0
1 = left audio output is hard muted
0 = left audio output is not hard muted
1 = right audio output is hard muted
0 = right audio output is not hard muted
-
6
RHM
R/W
0
5
4
-
-
0
0
0
0
LHSW
R/W
1 = level hysteresis is large (see Table 21)
0 = level hysteresis is small
3
2
TRIGFR
LDX
R/W
R/W
1 = reference frequency selected pin FREQIN
0 = crystal as reference pin XTAL
1 = local DX on, −6 dB gain of LNA
0 = local DX off, LNA has normal gain
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Low voltage single-chip FM stereo radio
Table 20: TESTBITS - test bits register byte10R and byte5W description …continued
Bit
Symbol
Access Reset
Description
1
RFAGC
R/W
0
1 = RF AGC off
0 = RF AGC on
0
INTCTRL
R/W
0
1 = interrupt generation on pin INTX enabled
0 = interrupt generation disabled
Table 21: LH - RSSI level hysteresis
Bits SSL[1:0]
RSSI ADC search
stop level
Bit LHSW
RSSI hysteresis
threshold level
00
01
3
5
X
1
0
1
0
1
0
0
1
2
3
4
5
7
10
11
7
10
Table 22: TESTMODE - Test mode register byte11R and byte6W description
Bit
Symbol
Access Reset
Description
1 = fast 4 ms
0 = slow 8 ms
reserved
7
DETT
R/W
0
6
5
4
-
-
-
-
-
-
reserved
TM
R/W
1 = TEA5761UK in Test mode and software port
outputs according to Table 23
0
0
0
0
0
0 = normal operation
3
2
1
0
TB3
TB2
TB1
TB0
R/W
R/W
R/W
R/W
test bits select the signals outputted to pin SWPORT
when bit SWPM = 0; see Table 23
Table 23: Test bits (SWPM = 0)
TB3
TB2
TB1
TB0
Pin SWPORT output
bit SWP of byte 4W or bit FRRFLAG (SWPM = 1)
oscillator output 32.768 kHz (TM = 1)
lock detect bit LD (TM = 1)
pilot detected (TM = 1)
programmable divider (TM = 1)
reserved
0
0
0
0
0
0
:
0
0
0
0
1
1
:
0
0
1
1
0
0
:
0
1
0
1
0
1
:
:
1
1
1
1
reserved
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Philips Semiconductors
Low voltage single-chip FM stereo radio
Table 24: MANID1 - manufacturer identification register byte12R description
Bit
7
Symbol
Access Reset
Description
VERSION3
VERSION2
VERSION1
VERSION0
MANID10
MANID9
R
R
R
R
R
R
R
R
0
1
0
0
0
0
0
0
version code; default 0100
6
5
4
3
manufacturer ID code; default 0000 (001 0101)
2
1
MANID8
0
MANID7
Table 25: MANID2 - manufacturer identification register byte13R description
Bit
7
Symbol
MANID6
MANID5
MANID4
MANID3
MANID2
MANID1
MANID0
IDAV
Access Reset
Description
R
R
R
R
R
R
R
R
0
0
1
0
1
0
1
1
manufacturer ID code; default (0000) 001 0101
6
5
4
3
2
1
0
1 = chip has manufacturer ID
0 = chip has no ID
Table 26: CHIPID1 - chip identification register byte14R description
Bit
7
Symbol
Access Reset
Description
CHIPID15
CHIPID14
CHIPID13
CHIPID12
CHIPID11
CHIPID10
CHIPID9
CHIPID8
R
R
R
R
R
R
R
R
0
1
0
1
0
1
1
1
TEA5761UK chip identification code: 1st digit = 5
6
5
4
3
TEA5761UK chip identification code: 2nd digit = 7
2
1
0
Table 27: CHIPID2 - chip identification register byte15R description
Bit
7
Symbol
CHIPID7
CHIPID6
CHIPID5
CHIPID4
Access Reset
Description
R
R
R
R
0
1
1
0
TEA5761UK chip identification code: 3rd digit = 6
6
5
4
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Product data sheet
Rev. 01 — 2 August 2006
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TEA5761UK
Philips Semiconductors
Low voltage single-chip FM stereo radio
Table 27: CHIPID2 - chip identification register byte15R description …continued
Bit
3
Symbol
CHIPID3
CHIPID2
CHIPID1
CHIPID0
Access Reset
Description
TEA5761UK chip identification code: 4th digit = 1
R
R
R
R
0
0
0
1
2
1
0
11. Limiting values
Table 28: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VCCD
VCCA
VLO1
VLO2
Tstg
Parameter
Conditions
Min
−0.3
−0.3
−0.3
−0.3
−55
−40
-
Max
+5.5
+8
Unit
V
digital supply voltage
analog supply voltage
VCO tuned circuit output 1
VCO tuned circuit output 2
storage temperature
ambient temperature
electrostatic discharge voltage
V
+8
V
+8
V
+150
+85
±2000
±500
±200
°C
°C
V
Tamb
Vesd
[1]
[2]
[3]
HBM
CDM
MM
-
V
-
V
[1] Human body model (R = 1.5 kΩ, C = 100 pF).
[2] Charged device model (“JEDEC standard JESD22-C101”).
[3] Machine model (R = 0 Ω, C = 200 pF).
9397 750 13451
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Product data sheet
Rev. 01 — 2 August 2006
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TEA5761UK
Philips Semiconductors
Low voltage single-chip FM stereo radio
12. Static characteristics
Table 29: Supply characteristics
The listed parameters are valid when a crystal is used with the requirements stated in Table 31.
Symbol
VCCA
Parameter
Conditions
Min
2.4
2.4
Typ
2.7
2.7
Max
3.6
Unit
V
analog supply voltage
digital supply voltage
analog supply current
VCCD
ICCA
3.6
V
VCCA = 2.7 V
Operating mode
Standby mode
10
-
14
16.5
6.0
mA
2.0
µA
ICCD
digital supply current
VCCD = 2.7 V
Operating mode
Standby mode
5
15
3.3
-
20
µA
µA
°C
1
20
[1]
Tamb
Ptot
ambient temperature
total power dissipation
VCCA = VCCD = 2.7 V; VCD1 = 2.7 V;
−20
+85
VVREFDIG = 1.8 V
-
38
-
mW
[1] Crystal influence not included.
Table 30: Control input and output characteristics
VCCA = VCCD = 2.7 V; Tamb = 25 °C; minimum and maximum values include spread due to the applied voltage from 2.5 V to
3.6 V and process spread; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Reference for I2C-bus interface: pin VREFDIG
VVREFDIG
digital reference voltage
V
VREFDIG ≤ VCCD
Operating mode;
VREFDIG = 1.65 V to
VCCD
Logic inputs: pins BUSENABLE, SCL and SDA
1.65
-
1.8
0.5
VCCD
2.0
V
IVREFDIG
digital reference current
µA
V
Ri
input resistance
10
-
-
-
MΩ
VIH
HIGH-level input voltage
input switching level
up
0.7 × VVREFDIG
VVREFDIG + 0.3 V
VIL
LOW-level input voltage
input switching level
down
0
-
-
0.3 × VVREFDIG
V
V
Software programmable output port: pin SWPORT
VOH
HIGH-level output voltage
Isource = 150 µA
VVREFDIG
0.45
−
VVREFDIG
VOL
LOW-level output voltage
maximum sink current
Isink = 150 µA
0
0.2
0.45
2000
500
V
Isink(max)
250
250
-
-
µA
µA
Isource(max) maximum source current
Interrupt output: pin INTX[1]
VOH
VOL
HIGH-level output voltage
LOW-level output voltage
VVREFDIG = 1.65 V;
pull-up resistance of
second device
V
VREFDIG − 0.2 -
VVREFDIG + 0.2 V
0.13
0.22 0.4
V
connected to INTX is
18 kΩ, or maximum
load current is 100 µA
9397 750 13451
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Product data sheet
Rev. 01 — 2 August 2006
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TEA5761UK
Philips Semiconductors
Low voltage single-chip FM stereo radio
Table 30: Control input and output characteristics …continued
VCCA = VCCD = 2.7 V; Tamb = 25 °C; minimum and maximum values include spread due to the applied voltage from 2.5 V to
3.6 V and process spread; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Isource(max) maximum source current
(pull-down)
including internal
pull-up resistor
260
380
615
µA
Rpu
tL
pull-up resistance
LOW time
14.4
9.9
18
22.5
kΩ
one-shot pulse time;
when the LOW period
is not shortened by a
read action
9.98 10
ms
[1]
VVREFDIG ≥ 1.65 V; Rpu of second device connected to pin INTX is 18 kΩ ± 20 %.
13. Dynamic characteristics
Table 31: Oscillators, clocks and synthesizer characteristics
VCCA = VCCD = 2.7 V; VVREFDIG = 1.8 V; Tamb = 25 °C; measured with test circuit in Figure 13; all AC values are given in RMS;
minimum and maximum values include spread due to the applied voltage from 2.5 V to 3.6 V and process spread; unless
otherwise specified; all RF input values are defined in potential difference (PD), except when EMF is explicitly stated.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Voltage controlled oscillator
fosc
oscillator frequency
150
-
217
MHz
Reference frequency input: pin FREQIN
VI
Ri
DC input voltage
input resistance
oscillator externally clocked
0
-
-
1.95
-
V
oscillator externally clocked with
fi = 32.768 kHz
500
kΩ
Ci
input capacitance
oscillator externally clocked with
fi = 32.768 kHz
5
6
7
pF
frsn
resonance frequency
-
32.768 -
kHz
ppm
ppm
%
∆frsn
resonance frequency deviation
−20
−150
30
0.9
0
-
-
-
-
-
-
+20
Tamb = −20 °C to +75 °C
square wave
+150
70
δ
duty cycle
VIH
VIL
J
HIGH-level input voltage
LOW-level input voltage
jitter
square wave
1.95
0.55
1
V
square wave
V
integrated over 300 Hz to 15 kHz
-
Hz
Crystal oscillator input 32.768 kHz: pin XTAL
frsn
resonance frequency
resonance frequency deviation
shunt capacitance
-
32.768 -
kHz
ppm
pF
∆frsn
Cshunt
Cm
−20
-
-
-
-
-
+20
3.5
3.0
75
motional capacitance
series resistance
1.5
-
fF
Rs
kΩ
9397 750 13451
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Product data sheet
Rev. 01 — 2 August 2006
29 of 44
TEA5761UK
Philips Semiconductors
Low voltage single-chip FM stereo radio
Table 31: Oscillators, clocks and synthesizer characteristics …continued
VCCA = VCCD = 2.7 V; VVREFDIG = 1.8 V; Tamb = 25 °C; measured with test circuit in Figure 13; all AC values are given in RMS;
minimum and maximum values include spread due to the applied voltage from 2.5 V to 3.6 V and process spread; unless
otherwise specified; all RF input values are defined in potential difference (PD), except when EMF is explicitly stated.
Symbol Parameter
Synthesizer
Conditions
Min
Typ
Max
Unit
Programmable divider
D/Dprog
programmable divider ratio
FRQSETMSB[5:0] = XX01 1111;
FRQSETLSB[7:0] = 1111 1111
-
-
8191
FRQSETMSB[5:0] = XX00 1000;
FRQSETLSB[7:0] = 0000 0000
2048
-
-
-
-
Dstep(prog) programmable divider step size
Charge pump output: pin CPOUT
1
IM(sink)
peak sink current
VCPOUT = 0.2 V to (VCD1 − 0.2 V);
2
4
8
µA
µA
f
VCO > fref × div_ratio
VCPOUT = 0.2 V to (VCD1 − 0.2 V);
VCO < fref × div_ratio
IM(source) peak source current
−2
−4
−8
f
Table 32: IF counter characteristics
VCCA = VCCD = 2.7 V; Tamb = 25 °C; measured with test circuit in Figure 13; all AC values are given in RMS; minimum and
maximum values include spread due to the applied voltage from 2.5 V to 3.6 V and process spread; unless otherwise
specified; all RF input values are defined in potential difference (PD), except when EMF is explicitly stated.
Symbol Parameter
IF counter
Conditions
Min
Typ
Max
Unit
N
length
-
7
6
-
-
bit
Vsens
ncount
T
sensitivity voltage
count result for search stop
period
-
18
3Ch
µV (EMF)
20 µV < VRF < 1 V
fxtal = 32768 Hz
bit IFCTC = 1
31h
-
-
-
15625
1953
4096
-
-
-
µs
µs
Hz
bit IFCTC = 0
fres
frequency resolution
fxtal = 32768 Hz
Table 33: FM signal channel characteristics
VCCA = VCCD = 2.7 V; Tamb = 25 °C; measured with test circuit in Figure 13; all AC values are given in RMS; minimum and
maximum values include spread due to the applied voltage from 2.5 V to 3.6 V and process spread; unless otherwise
specified; all RF input values are defined in potential difference (PD), except when EMF is explicitly stated.
Symbol
Parameter
Conditions
Min Typ Max Unit
FM RF input: pins RFIN1 and RFIN2
fi(FM)
FM input frequency
76
-
-
108 MHz
Vsens(EMF)
sensitivity EMF value voltage fRF = 76 MHz to 108 MHz; L = R;
∆f = 22.5 kHz; fmod = 1 kHz;
2.2
3.6
µV (EMF)
(S+N)/N = 26 dB; TCdeem = 75 µs,
A-weighting filter;
B
aud = 300 Hz to 15 kHz; see Figure 10
∆f1 = 200 kHz; ∆f2 = 400 kHz;
tune = 76 MHz to 108 MHz; RFagc = off
∆f1 = 4 MHz; ∆f2 = 8 MHz;
IP3in
in-band 3rd-order intercept
point related to VRFIN1-RFIN2
81
87
87
93
-
-
dBµV
dBµV
f
IP3out
out-of-band 3rd-order
intercept point related to
VRFIN1-RFIN2
ftune = 76 MHz to 108 MHz; RFagc = off
9397 750 13451
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Product data sheet
Rev. 01 — 2 August 2006
30 of 44
TEA5761UK
Philips Semiconductors
Low voltage single-chip FM stereo radio
Table 33: FM signal channel characteristics …continued
VCCA = VCCD = 2.7 V; Tamb = 25 °C; measured with test circuit in Figure 13; all AC values are given in RMS; minimum and
maximum values include spread due to the applied voltage from 2.5 V to 3.6 V and process spread; unless otherwise
specified; all RF input values are defined in potential difference (PD), except when EMF is explicitly stated.
Symbol
Ri
Parameter
Conditions
Min Typ Max Unit
input resistance
input capacitance
connected to pin GNDRF
connected to pin GNDRF
75
100 125
Ω
Ci
2.5
4
6
pF
In-band AGC
Vi(AGC)(min)
minimum RF AGC input
voltage
fRF = 98 MHz;
∆Vind(IF) / ∆Vi(RF) < 4 mV/dBµV
55
66
61
67
dBµV
dBµV
Wideband AGC
Vi(RF)
RF input voltage
fRF1 = 93 MHz; fRF2 = 98 MHz;
72
78
V
RF2 = 50 dBµV;
∆Vind(IF) / ∆Vi(RF) < 4 mV/dBµV; radio
tuned to 98 MHz
IF filter
fcenter
B
center frequency
bandwidth
215 225 235 kHz
85
94
102 kHz
[1]
S
selectivity
ftune = 76 MHz to 108 MHz
high-side; ∆f = +200 kHz
low-side; ∆f = −200 kHz
high-side; ∆f = +100 kHz
low-side; ∆f = −100 kHz
ftune = 76 MHz to 108 MHz;
39
32
8
43
36
12
12
30
-
-
-
-
-
dB
dB
dB
dB
dB
8
IR
image rejection
24
V
RF = 50 dBµV
FM IF level detector and mute voltage
Level detector RF input
VADC(start)
Gstep
ADC start voltage
2
2
3
3
5
5
µV
step resolution gain
correct code integrity tested
dB
Mute output: pin TMUTE
Vind(IF)
IF indication voltage
VRF = 0 µV
VRF = 3 µV
1.5
1.6
1.75
V
V
1.55 1.65 1.8
Vslope(ind)IF
IF indication voltage slope
definition:
∆Vslope(ind)IF = ∆Vind(IF) / ∆VRF
130 165 200 mV/
20dB
;
V
RF = 10 µV to 500 µV
RTMUTE
pin TMUTE output resistance
280 400 520 kΩ
FM demodulator: MPX output
(S+N)/N(m)
maximum signal-to-noise ratio, VRF = 1 mV; L = R; ∆f = 22.5 kHz;
53
57
-
dBA
mono
fmod = 1 kHz; TCdeem = 75 µs;
A-weighting filter; Baud = 300 Hz to
15 kHz
THD
total harmonic distortion
V
RF = 1 mV; L = R; fmod = 1 kHz;
TCdeem = 75 µs;
B
aud = 300 Hz to 15 kHz
∆f = 75 kHz
-
-
0.4
-
1
%
%
∆f = 100 kHz; see Figure 12
1.5
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Product data sheet
Rev. 01 — 2 August 2006
31 of 44
TEA5761UK
Philips Semiconductors
Low voltage single-chip FM stereo radio
Table 33: FM signal channel characteristics …continued
VCCA = VCCD = 2.7 V; Tamb = 25 °C; measured with test circuit in Figure 13; all AC values are given in RMS; minimum and
maximum values include spread due to the applied voltage from 2.5 V to 3.6 V and process spread; unless otherwise
specified; all RF input values are defined in potential difference (PD), except when EMF is explicitly stated.
Symbol
Parameter
Conditions
Min Typ Max Unit
AMsup
AM suppression
L = R; fmod = 1 kHz; VRF = 100 µV to
10 mV; m = 0.3; TCdeem = 75 µs;
40
-
-
dB
B
aud = 300 Hz to 15 kHz
FM demodulator output: pin MPXOUT
Vo
output voltage
VRF = 1 mV; L = R; ∆f = 22.5 kHz;
mod = 1 kHz; TCdeem = 75 µs;
aud = 300 Hz to 15 kHz
60
75
85
mV
f
B
Ro
output resistance
sink current
-
-
-
500
-
Ω
Isink
30
µA
Soft mute; SMUTE = 1; ∆f = 22.5 kHz; fmod = 1 kHz
Vstart(mute)
mute start voltage
relative to VVAFL at VRF = 1 mV;
αmute = 3 dB
3
5
10
30
µV
αmute
mute attenuation
VRF = 1 µV; L = R; TCdeem = 75 µs;
10
20
dB
B
aud = 300 Hz to 15 kHz
MPX decoder
αODi
αcs
input overdrive range
channel separation
THD < 3 %
4
-
-
-
dB
dB
VRF = 1 mV; ∆f = 75 kHz; including 9 %
pilot deviation; R = 0 and L = 1 or R = 1
and L = 0; fmod = 1 kHz; bit MST = 0;
bit SNC = 1; Baud = 300 Hz to 15 kHz
22
27
fu
fl
upper −3 dB bandwidth
lower −3 dB bandwidth
VRF = 1 mV; ∆f = 22.5 kHz; L = R;
pre-emphasis = 75 µs;
de-emphasis = 75 µs; no audio filter
13
-
15
20
17
30
kHz
Hz
(S+N)/N(m)
maximum signal-to-noise ratio,
mono
V
f
B
RF = 1 mV; ∆f = 22.5 kHz; L = R;
mod = 1 kHz; TCdeem = 75 µs;
aud = 300 Hz to 15 kHz; A-weighting
filter
53
57
-
dBA
(S+N)/N(s)
maximum signal-to-noise ratio,
stereo
V
RF = 1 mV; ∆f = 22.5 kHz; L = R;
49
53
-
dBA
fmod = 1 kHz; fpilot = 6.75 kHz;
TCdeem = 75 µs;
B
aud = 300 Hz to 15 kHz; A-weighting
filter
THD
total harmonic distortion,
stereo
VRF = 1 mV; ∆f = 75 kHz; L = R;
including 9 % pilot deviation;
-
0.9
50
2.5
-
%
fmod = 1 kHz; TCdeem = 75 µs
αsup(pilot)
pilot suppression
measured at pins VAFL and VAFR
related to ∆f = 75 kHz; fmod = 1 kHz;
TCdeem = 75 µs
40
dB
∆fpilot1
pilot frequency deviation 1
pilot frequency deviation 2
VRF = 1 mV; bit STEREO = 1
VRF = 1 mV; bit STEREO = 0
2.5
1.0
2
-
-
-
5.8
3.6
6
kHz
kHz
dB
∆fpilot2
αhys(pilot)
pilot tone detection hysteresis definition: fpilot(hys) = ∆fpilot1 / ∆fpilot2
;
V
RF = 1 mV
TCdeem
de-emphasis time constant
VRF = 1 mV
bit DTC = 1
bit DTC = 0
38
57
50
75
62
93
µs
µs
9397 750 13451
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Product data sheet
Rev. 01 — 2 August 2006
32 of 44
TEA5761UK
Philips Semiconductors
Low voltage single-chip FM stereo radio
Table 33: FM signal channel characteristics …continued
VCCA = VCCD = 2.7 V; Tamb = 25 °C; measured with test circuit in Figure 13; all AC values are given in RMS; minimum and
maximum values include spread due to the applied voltage from 2.5 V to 3.6 V and process spread; unless otherwise
specified; all RF input values are defined in potential difference (PD), except when EMF is explicitly stated.
Symbol
MPX decoder output: pins VAFR and VAFL
VVAFL left audio output voltage on pin VRF = 1 mV; L = R; ∆f = 22.5 kHz;
Parameter
Conditions
Min Typ Max Unit
60
75
75
-
90
90
mV
mV
VAFL
f
mod = 1 kHz; TCdeem = 75 µs
VRF = 1 mV; L = R; ∆f = 22.5 kHz;
mod = 1 kHz; TCdeem = 75 µs
definition:
between pins VAFL and VAFR ∆VO(VAFL-VAFR) = VVAFL / VVAFR
RF = 1 mV; L = R; ∆f = 75 kHz;
mod = 1 kHz, including 9 % pilot
VVAFR
right audio output voltage on
pin VAFR
60
f
∆VO(VAFL-VAFR) output voltage difference
−0.5
+0.5 dB
;
V
f
deviation; TCdeem = 75 µs
MU = LHM = RHM = 0
MU = LHM = RHM = 1
MU = LHM = RHM = 0
MU = LHM = RHM = 1
RO(VAFL)
output resistance pin VAFL
output resistance pin VAFR
50
-
-
-
-
-
-
100
Ω
500
50
-
kΩ
Ω
RO(VAFR)
100
500
170
170
-
-
-
kΩ
µA
µA
Isink(VAFL)
Isink(VAFR)
sink current on pin VAFL
sink current on pin VAFR
Mono stereo blend: bit SNC = 1
Vstart(blend)
blend start voltage
stereo channel separation = 1 dB; with
increasing input levels the radio
switches gradually from mono to stereo
7
4
10
10
18
16
µV
αcs
channel separation
VRF = 40 µV; ∆f = 75 kHz; R = 0 and
L = 1 or R = 1 and L = 0; including 9 %
pilot deviation; fmod = 1 kHz;
bit MST = 0
dB
Mono stereo switching; ∆f = 75 kHz including 9 % pilot deviation; fmod = 1 kHz; SNC = 0
αcs
channel separation
MST = 0; R = 1 and L = 0 or R = 0 and
L = 1
from mono to stereo with increasing
RF input level
22
-
-
-
-
dB
dB
from stereo to mono with decreasing
RF input level
1
Vsw
hys
switching voltage
hysteresis
25
1
35
3
60
4
µV
dB
Bus driven mute functions
Tuning mute; AFM = 1
αmute
mute depth on pins VAFL and bit AFM = 1
−60
-
-
dB
VAFR
αmute(VAFR)
αmute(VAFL)
mute depth on pin VAFR
mute depth on pin VAFL
bit AFM = 1; bit RHM = 1
bit AFM = 1; bit LHM = 1
−80
−80
-
-
-
-
dB
dB
[1] Low-side and high-side selectivity can be measured by changing the mixer LO injection from high-side to low-side.
9397 750 13451
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Product data sheet
Rev. 01 — 2 August 2006
33 of 44
TEA5761UK
Philips Semiconductors
Low voltage single-chip FM stereo radio
001aab491
4
10
(1)
V
V
(dBA)
THD, N
(%)
VAFR,
VAFL
3
2
1
0
−10
−30
−50
−70
(2)
(3)
−7
−6
−5
−4
−3
−2
−1
10
10
10
10
10
10
10
1
V
, V
(V)
RFIN1 RFIN2
(1) Mono signal: soft mute off, ∆f = 22.5 kHz.
(2) Noise in Mono mode, soft mute off, ∆f = 0 kHz.
(3) Total harmonic distortion, ∆f = 75 kHz.
Fig 10. FM characteristics mono
001aab490
4
10
(1)
(2)
THD, N
(%)
V
V
(dBA)
−10
VAFR,
VAFL
3
2
1
0
−30
−50
−70
(3)
(4)
(5)
−7
−6
−4
−3
−2
−1
10
10
10
10
10
10
10
1
V
, V
(V)
RFIN1 RFIN2
(1) VAFL signal, modulation left, SNC on, ∆f = 67.5 kHz; ∆fpilot = 6.75 kHz.
(2) VAFR signal, modulation left, SNC on, ∆f = 67.5 kHz; ∆fpilot = 6.75 kHz.
(3) Noise in Stereo mode, SNC on, ∆f = 0 kHz; ∆fpilot = 6.75 kHz.
(4) Total harmonic distortion: ∆f = 67.5 kHz; ∆fpilot = 6.75 kHz.
(5) Noise in Mono mode, SNC off, ∆f = 0 kHz; ∆fpilot = 0 kHz.
Fig 11. FM characteristics stereo
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Product data sheet
Rev. 01 — 2 August 2006
34 of 44
TEA5761UK
Philips Semiconductors
Low voltage single-chip FM stereo radio
001aab492
3.5
10
(1)
V
V
THD
(%)
VAFL,
VAFR
(dBA)
2.5
2.0
1.5
1.0
0.5
0
−10
−30
−50
−70
(3)
(2)
−1
2
3
4
5
6
10
1
10
10
10
10
10
10
EMF
V
(µV
)
RF
(1) Mono signal, soft mute on, ∆f = 22.5 kHz.
(2) Noise in Mono mode, soft mute on, ∆f = 0 kHz.
(3) Total harmonic distortion, ∆f = 100 kHz.
Fig 12. FM characteristics mono, soft mute active and THD at 100 kHz deviation
9397 750 13451
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 2 August 2006
35 of 44
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx
xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x
n.c.
i.c.
33 nF
GNDA
F2
GNDA
G2
VAFR TMUTE
MPXOUT
VAFL
F4
G3
G4
G5
G6
F6
FREQIN
XTAL
G1
F1
CRYSTAL
OSCILLATOR
X1
TEA5761UK
GAIN
STABILIZER
V
CCA E1
3.7
Ω
CD3
IF
FILTER
SOFT
MUTE
LIMITER
DEMODULATOR
IF COUNT
D2
33 nF
SDS
FM
antenna
LEVEL
ADC
10 nF
I/Q MIXER
1st FM
÷2
N1
MPX
DECODER
100 pF
I
ref
IF CENTER
FREQUENCY ADJUST
INTX
G7
27
pF
D1
RFIN1
GNDD
F7
E6
L1
120 nH
AGC
RFIN2 C1
47
pF
i.c.
33 nF
agc
C2
B1
GNDRF
CAGC
E7 CD2
mono
pilot
12 Ω
V
CCD
D7
prog. div out
ref. div out
D6 GNDD
2
I C-BUS
INTERFACE
TUNING SYSTEM
C7 GNDD
B7 SDA
SCL
A7
MUX
VCO
A2
SW PORT
A5
A4
A1
B2
A3
B4
A6
BUSENABLE
B6
VREFDIG
001aab486
LOOPSW
CPOUT
LO1
CD1
SWPORT
LO2
n.c.
10
nF
100 nF
10 kΩ
L2
39 nH
100 kΩ
33 nF
Total of 15 external components.
Fig 13. Application diagram
TEA5761UK
Philips Semiconductors
Low voltage single-chip FM stereo radio
Table 34: List of components
Number Component Description
Type
Manufacturer
1
L1
RF band filter coil 120 nH; 0603CS series or
equivalent; Qmin = 20;
Coilcraft, Murata,
Epcos, Panasonic
tolerance: ±5 %
2
L2
VCO coil
39 nH to 47 nH; 0603CS
series or equivalent;
Coilcraft, Murata,
Epcos, Panasonic
Qmin = 25; tolerance: ±5 %
3
X1
R
32.768 kHz crystal see Table 31
4
10 kΩ
100 kΩ
27 pF
47 pF
100 pF
10 nF
10 nF
33 nF
33 nF
33 nF
33 nF
100 nF
±10 % (max)
±10 % (max)
±10 % (max)
±10 % (max)
±10 % (max)
±10 % (max)
±10 % (max)
±10 % (max)
±10 % (max)
±10 % (max)
±10 % (max)
±10 % (max)
5
6
C
7
8
9
10
11
12
13
14
15
Table 35: DC operating points
VCCA = VCCD = VVREFDIG = 2.7 V.
Symbol
Ball
Mode
Unit
Active
Standby
LOOPSW
LO1
A1
A2
A3
A4
A5
A6
A7
B1
B2
B4
B6
B7
C1
C2
C7
D1
D2
D6
2.6
2.7
2.7
2.7
2.7
0.2
2.7
-
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1.8
LO2
1.8
CD1
2.6
SWPORT
BUSENABLE
SCL
0.2
2.7
-
CAGC
CPOUT
n.c.
1.2
2.2
0
0.5 to 2.5
0
0
VREFDIG
SDA
2.7
-
2.7
-
RFIN2
GNDRF
GNDD
RFIN1
CD3
0.5
0
0
0
0
0
0.5
2.6
0
0
2.7
0
GNDD
9397 750 13451
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 2 August 2006
37 of 44
TEA5761UK
Philips Semiconductors
Low voltage single-chip FM stereo radio
Table 35: DC operating points …continued
VCCA = VCCD = VVREFDIG = 2.7 V.
Symbol
Ball
Mode
Active
2.7
2.7
0
Unit
Standby
VCCD
D7
E1
E6
E7
F1
F2
F4
F6
F7
G1
2.7
2.7
0
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VCCA
i.c.
CD2
2.7
1.7
0
2.7
2.5
0
XTAL
GNDA
VAFL
0.8
0
0
i.c.
0
GNDD
FREQIN (no load)
TRIGFR = 0
TRIGFR = 1
GNDA
n.c.
0
0
-
0
0
-
1.5
0
-
G2
G3
G4
G5
G6
G7
0
0
0
MPXOUT
VAFR
0.8
0.8
1.9
2.7
2.4
0
TMUTE
INTX
2.3
2.7
9397 750 13451
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 2 August 2006
38 of 44
TEA5761UK
Philips Semiconductors
Low voltage single-chip FM stereo radio
15. Package outline
WLCSP34: wafer level chip-size package; 34 bumps; 3.5 x 3.5 x 0.6 mm
TEA5761UK
D
B
A
bump A1
index area
A
2
A
E
A
1
detail X
C
e
1
y
M
v
C A
C
B
b
e
M
w
G
F
e
E
D
C
B
A
e
2
1
2
3
4
5
6
7
X
0
1
2
3 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
1
A
2
b
D
E
e
e
e
2
v
w
y
1
max
0.26 0.38 0.34
0.22 0.34 0.30
3.6
3.5
3.6
3.5
mm
0.64
0.5
3
3
0.01 0.04 0.02
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
05-11-28
05-12-02
TEA5761UK
Fig 14. Package outline TEA5761UK (WLCSP34)
9397 750 13451
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 2 August 2006
39 of 44
TEA5761UK
Philips Semiconductors
Low voltage single-chip FM stereo radio
16. Soldering
16.1 Introduction to soldering WLCSP packages
This text gives a very brief insight to a complex technology. A more in-depth account of
soldering WLCSP packages can be found in “AN10365. Application note for wafer level
CSPs”. Wave soldering is not suitable for this package.
16.2 Reflow soldering process
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
16.2.1 Solder reflow profile
t
p
critical zone
to Tp
Tp
temperature
T
L
ramp-up
T
L
t
Ts
Ts
L
max
min
ramp-down
ts
preheat
25 °C
time
t
to peak
25°C
001aac838
Tp = 260 °C.
TL = 217 °C.
Tsmin = 150 °C.
Tsmax = 200 °C.
tp = 20 s to 40 s.
tsmin to tsmax = 60 s to 180 s.
Time from 25 °C to peak temperature is maximal 8 minutes.
Fig 15. Solder reflow profile
16.2.2 Quality of solder joint
A flip-chip joint is considered to be a good joint when the entire solder land has been
wetted by the solder from the bump. The surface of the joint should be smooth and the
shape symmetrical. The soldered joints on a chip should be uniform. Voids in the bumps
after reflow can occur during the reflow process in bumps with high ratio of bump diameter
to bump height, i.e. low bumps with large diameter. No failures have been found to be
related to these voids. Solder joint inspection after reflow can be done with X-ray to
monitor defects such as bridging, open circuits and voids.
9397 750 13451
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Product data sheet
Rev. 01 — 2 August 2006
40 of 44
TEA5761UK
Philips Semiconductors
16.2.3 Rework
Low voltage single-chip FM stereo radio
In general, rework is not recommended. By rework we mean the process of removing the
chip from the substrate and replacing it with a new chip. If a chip is removed from the
substrate, most solder balls of the chip may be damaged. In that case it is recommended
not using the chip again.
Device removal can be done when the substrate is heated until it is certain that all solder
joints are molten. The chip can then be carefully removed from the substrate without
damaging the tracks and solder lands on the substrate. The surface of the substrate
should be carefully cleaned and all solder and flux residues and/or underfill removed.
When a new chip is placed on the substrate, use the flux process instead of solder on the
solder lands. Apply flux on the bumps at the chip side as well as on the solder pads on the
substrate. Place and align the new chip while viewing with a microscope. To reflow the
solder, use the solder profile shown in this document.
16.2.4 Cleaning
Cleaning can be done after reflow soldering.
9397 750 13451
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 2 August 2006
41 of 44
TEA5761UK
Philips Semiconductors
Low voltage single-chip FM stereo radio
17. References
[1] The I2C-bus specification — version 2.1 January 2000
[2] JESD22-C101 — JEDEC standard for CDM test
[3] AN10365 — Application note for wafer level CSPs
18. Revision history
Table 36: Revision history
Document ID
Release date Data sheet status
20060802 Product data sheet
Change notice Doc. number
9397 750 13451
Supersedes
TEA5761UK_1
-
-
9397 750 13451
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 2 August 2006
42 of 44
TEA5761UK
Philips Semiconductors
Low voltage single-chip FM stereo radio
19. Data sheet status
Level Data sheet status[1] Product status[2] [3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
20. Definitions
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
makes no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
22. Trademarks
Notice — All referenced brands, product names, service names and
trademarks are the property of their respective owners.
I2C-bus — logo is a trademark of Koninklijke Philips Electronics N.V.
21. Disclaimers
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
23. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
9397 750 13451
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 2 August 2006
43 of 44
TEA5761UK
Philips Semiconductors
Low voltage single-chip FM stereo radio
24. Contents
1
2
3
4
5
6
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.3
Multiple interrupt events . . . . . . . . . . . . . . . . . 16
IF frequency flag . . . . . . . . . . . . . . . . . . . . . . 16
RSSI threshold flag . . . . . . . . . . . . . . . . . . . . 16
Frequency ready flag . . . . . . . . . . . . . . . . . . . 17
Band limit flag. . . . . . . . . . . . . . . . . . . . . . . . . 17
Interrupt output. . . . . . . . . . . . . . . . . . . . . . . . 17
I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . . 18
Write and Read mode . . . . . . . . . . . . . . . . . . 18
Data transfer. . . . . . . . . . . . . . . . . . . . . . . . . . 18
Register map . . . . . . . . . . . . . . . . . . . . . . . . . 20
Byte description . . . . . . . . . . . . . . . . . . . . . . . 21
10
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
10.1
10.2
10.3
10.4
8
Functional description . . . . . . . . . . . . . . . . . . . 6
Low noise RF amplifier . . . . . . . . . . . . . . . . . . . 6
I/Q mixer 1st FM . . . . . . . . . . . . . . . . . . . . . . . . 6
VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . 6
PLL tuning system . . . . . . . . . . . . . . . . . . . . . . 7
Band limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
RF AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Local or long distance receive . . . . . . . . . . . . . 8
IF filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
FM demodulator . . . . . . . . . . . . . . . . . . . . . . . . 8
IF counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Voltage level generator and analog-to-digital
converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Soft mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Hard mute. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Audio frequency mute. . . . . . . . . . . . . . . . . . . . 9
MPX decoder . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Signal dependent mono/stereo blend (stereo
noise cancellation) . . . . . . . . . . . . . . . . . . . . . . 9
Software programmable port . . . . . . . . . . . . . . 9
Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . 10
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 10
I2C-bus interface. . . . . . . . . . . . . . . . . . . . . . . 10
Auto search and Preset mode . . . . . . . . . . . . 10
Search mode . . . . . . . . . . . . . . . . . . . . . . . . . 10
Preset mode . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Auto high-side and low-side injection stop
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.12
11
12
13
14
15
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 27
Static characteristics . . . . . . . . . . . . . . . . . . . 28
Dynamic characteristics. . . . . . . . . . . . . . . . . 29
Application information . . . . . . . . . . . . . . . . . 36
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 39
16
16.1
16.2
16.2.1
16.2.2
16.2.3
16.2.4
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Introduction to soldering WLCSP packages. . 40
Reflow soldering process. . . . . . . . . . . . . . . . 40
Solder reflow profile . . . . . . . . . . . . . . . . . . . . 40
Quality of solder joint . . . . . . . . . . . . . . . . . . . 40
Rework. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Cleaning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.13
17
18
19
20
21
22
23
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Revision history . . . . . . . . . . . . . . . . . . . . . . . 42
Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 43
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Contact information . . . . . . . . . . . . . . . . . . . . 43
8.13.1
8.13.2
8.13.3
8.14
8.15
8.16
8.17
8.18
8.19
8.20
8.20.1
8.20.2
8.20.3
switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Muting during search or preset. . . . . . . . . . . . 13
8.20.4
9
9.1
9.1.1
9.1.2
9.1.3
9.2
Interrupt handling . . . . . . . . . . . . . . . . . . . . . . 13
Interrupt register . . . . . . . . . . . . . . . . . . . . . . . 13
Interrupt clearing. . . . . . . . . . . . . . . . . . . . . . . 14
Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Interrupt flags and behavior . . . . . . . . . . . . . . 16
© Koninklijke Philips Electronics N.V. 2006
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.
Date of release: 2 August 2006
Document number: 9397 750 13451
Published in The Netherlands
相关型号：
TEA5766UK
IC FM, AUDIO SINGLE CHIP RECEIVER, PBGA25, 3.30 X 3.25 MM, 0.60 MM HEIGHT, WLCSP-25, Receiver IC
NXP
TEA5767HN/V3,118
IC FM, AUDIO SINGLE CHIP RECEIVER, PQCC40, 6 X 6 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-618-1, HVQFN-40, Receiver IC
NXP
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