TZA1031HL [NXP]
IC SPECIALTY CONSUMER CIRCUIT, PQFP64, 10 X 10 MM, 1.40 MM, PLASTIC, MS-026, SOT-314-2, LQFP-64, Consumer IC:Other;
| 型号： | TZA1031HL |
| 厂家： | 
NXP |
| 描述： | IC SPECIALTY CONSUMER CIRCUIT, PQFP64, 10 X 10 MM, 1.40 MM, PLASTIC, MS-026, SOT-314-2, LQFP-64, Consumer IC:Other 商用集成电路 |
| 文件： | 总52页 (文件大小：207K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TZA1031
Signal processing IC for DVD
rewriteable
Product specification
2002 Jun 06
Philips Semiconductors
Product specification
Signal processing IC for DVD rewriteable
TZA1031
CONTENTS
8
LIMITING VALUES
9
CHARACTERISTICS
1
2
3
4
5
6
7
FEATURES
10
11
12
12.1
APPLICATION INFORMATION
PACKAGE OUTLINE
SOLDERING
GENERAL DESCRIPTION
ORDERING INFORMATION
QUICK REFERENCE DATA
BLOCK DIAGRAM
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
PINNING
12.2
12.3
12.4
12.5
FUNCTIONAL DESCRIPTION
7.1
7.1.1
EFMTIM
Suitability of surface mount IC packages for
wave and reflow soldering methods
Data signal synchronization and read-write
detection
13
14
15
DATA SHEET STATUS
DEFINITIONS
7.1.2
7.1.3
7.1.4
7.1.5
7.2
EFMTIM input interface
EFMTIM test output
EFMTIM reset
EFMTIM control
NORM
DISCLAIMERS
7.2.1
7.2.2
AUX block
DOC block: normalization and drop-out
concealment
7.2.3
7.2.4
7.2.5
7.2.6
FOC block: focus servo signal normalization
RAD block: radial servo signal normalization
TL block: track loss servo signal
CANORM block: CA signal normalization
circuit
7.2.7
7.2.8
7.2.9
7.3
TILT block: tilt sensor normalization circuit
Output current polarities
Control signal overview
RF-AMP
7.3.1
7.4
Data path amplifier and filtering
PP-AMP
7.4.1
7.5
Push-pull channel amplifier and filtering
ALFA
7.5.1
7.5.2
7.5.3
7.5.4
7.6
ALFA measurement circuit for running OPC
Dye media
Phase change media
ALFA circuit general
BETA
7.6.1
BETA measurement circuit for write power
calibration
7.7
BCA
7.7.1
7.8
Burst cutting area signal processing circuit
MON
7.8.1
7.9
Monitor circuit for various internal servo signals
Serial bus: interface to system controller
Timing relations for serial bus control
Operation
Control register of the device
General control format
Register definitions
7.9.1
7.9.2
7.10
7.10.1
7.10.2
2002 Jun 06
2
Philips Semiconductors
Product specification
Signal processing IC for DVD rewriteable
TZA1031
1
FEATURES
• Programmable DC offset cancellation in RF path to
allow DC coupling to decoder ICs (HDR65 or IGUANA)
• Operates with DVD-ROM, DVD+RW, DVD-RW,
CD-ROM and CD-RW media
• Push-pull signal channel to read address information on
recordable and rewriteable media
• Specifically intended for writing applications
• Programmable running OPC processing for both dye
and phase change media
• Operates up to 64 × CD-ROM read, 16 × DVD-ROM
read, 16 × CDR/RW write and 4 × DVDR/RW write
• On-chip processing circuit for write power calibration
• Optimized interface to the optical pick-up unit
preprocessor IC (TZA1030) and Philips decoder ICs
HDR65 or IGUANA
• Burst cutting area read-out amplifier circuit with digital
output
• Monitor function to read out internal signals for test and
adjustment purposes
• On-chip EFM signal decoder for write synchronization
• Programmable normalization for servo signals
• 3-wire high-speed serial interface for programming of
the device by a decoder IC or microcontroller.
• Servo outputs programmable for direct unprocessed
currents or error signals
• RF data amplifier with wide (programmable) bandwidth
equivalent to 64 × CD or 16 × DVD when using
equaliser function
2
GENERAL DESCRIPTION
The TZA1031 is an analog preprocessor IC for recording
CD and DVD systems such as DVDRW, combo and
double writer applications. It is optimized to work with the
optical pick-up unit preprocessor IC TZA1030 and Philips
decoder ICs HDR65 and IGUANA. The TZA1031 takes
care of the specific recording functions in the servo,
RF and push-pull channels. It also provides read-out of
BCA code.
• Programmable noise filter in RF amplifier for improved
signal quality
• Programmable RF gain for DVD-ROM, DVD-RW,
CD-RW or CD-ROM applications; AGC possible with
decoder ICs (HDR65 or IGUANA)
• Dual differential RF signal input, differential RF signal
output
3
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
TZA1031HL
LQFP64
plastic low profile quad flat package; 64 leads; body 10 × 10 × 1.4 mm
SOT314-2
2002 Jun 06
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Philips Semiconductors
Product specification
Signal processing IC for DVD rewriteable
TZA1031
4
QUICK REFERENCE DATA
SYMBOL PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDD
positive supply voltage
4.5
5
5.5
V
V
VSS
negative supply voltage
total positive supply current
total negative supply current
−5.5
−
−5
40
40
−
−4.5
−
IDD(tot)
ISS(tot)
Iq(DD)
Iq(SS)
Tamb
circuit active
circuit active
mA
mA
mA
mA
°C
−
−
quiescent current positive supply STBY = 1
quiescent current negative supply STBY = 1
−
4
−
−
8
ambient temperature
operating
0
−
55
Write synchronization circuit (EFMTIM)
Ii(EFM)
input current on pins EFMDP,
EFMDN, EFMCP and EFMCN
0
−
−
−
−
−
−
1200
µA
µA
µA
µA
mV
Ω
Ii(dif)(H)
Ii(dif)(L)
Ii(dif)(th)
Vi(EFM)
Ri(EFM)
differential input current for HIGH
level
I
I
EFMDP−IEFMDN
EFMCP−IEFMCN
EFMDP−IEFMDN
EFMCP−IEFMCN
EFMDP−IEFMDN
EFMCP−IEFMCN
;
;
;
330
−330
0
−
differential input current for LOW
level
I
I
−
differential input current threshold
level
I
I
−
input voltage on pins EFMDP,
EFMDN, EFMCP and EFMCN
−
120
−
input resistance on pins EFMDP,
EFMDN, EFMCP and EFMCN
120
Normalizer and servo path (NORM)
Vi(Q)
Q1 to Q6 input voltage
Q/NE = 1;
i(Q) = 10 µA
Q/NE = 0;
i(Q) = 10 µA
−
−
1.3
1.5
−
−
V
V
I
I
Ii(Q)
servo input (Q1 to Q6) current
range
Q/NE = 0
Q/NE = 1
0
−
−
−
110
µA
µA
V
−8
−0.5
+12
Vo(S), Vo(D)
Ii(TS)
servo output (S1 to S2 and
D1 to D4) voltage range
0.5VDD
tilt sensor input (TS1 and TS2)
current range
0
−
40
µA
Vi(TS)
tilt sensor input voltage
−
VSS + 2.6 −
V
RF amplifier (RF-AMP)
ARF
gain range RF path
programmable by
parameters GRF
and HA
−4
−
+20
dB
BWRF
f0(RF)
−3 dB bandwidth of RFP and RFN ENEQ = 0;
180
16
−
−
−
MHz
MHz
ENNF = 0
noise filter and equalizer corner
frequency
controlled by
parameter BWRF
143
2002 Jun 06
4
Philips Semiconductors
Product specification
Signal processing IC for DVD rewriteable
TZA1031
SYMBOL
td(F)
PARAMETER
flatness delay RF
CONDITIONS
MIN.
TYP.
MAX.
0.10
UNIT
ns
f0 = 143 MHz;
ENEQ = 1;
F = 0 to 100 MHz
−
−
−
Vi(RF)
input voltage range (RFP-RFN)
differential
0
1
V
common mode
−
2.5
−
−
V
Ri(RF)
RF input impedance
100
1
−
kΩ
V
Vo(RFREF)
Vo(dif)(RF)
RF output voltage reference
−
2.5
+1
+2
40
RF differential output voltage
range (RFP-RFN)
GRF = 0 dB; HA = 0 −1
−
V
GRF = 0 dB; HA = 1 −2
−
V
Ro(RF)
RFP and RFN output impedance
−
−
Ω
PP amplifier (PP-AMP)
Ii(PPN)(p-p)
AC input current range
200
−
−
µA
(peak-to-peak value)
Vi(PPN)
input voltage level
−
−
−
2.4
0
−
−
−
V
V
Ω
Vo(PPNO)
Ro(PPNO)
output voltage DC level
output impedance
Ii(PPN) = 0
130
Running OPC (ALFA)
Io(ALFA) ALFA output current range
Ii(LASP)
Vo(ALFA) = 0 V
0
5
0
−
−
−
100
100
15
−
µA
µA
µA
V
LASP control current input range r/w = 0
−
r/w = 1
−
Vi(LASP)
Ri(LASP)
LASP input voltage
Ii(LASP) = 100 µA
1.7
1
LASP input impedance
−
kΩ
Write power calibration (BETA)
Vo(ref)(beta) beta output (A1, A2 and CALF)
−
0
−
1.25
−
−
3
−
V
V
Ω
reference voltage
Vo(beta)
A1, A2 and CALF output voltage
range
Ro(beta)
A1, A2 and CALF output
impedance
250
BCA amplifier (BCA)
VOH(BCA) HIGH-level output voltage on
BCAEN = 1;
VDD = 5 V;
Iload = 0.5 mA
3.0
0
−
−
3.3
0.6
V
V
pin BCA
VOL(BCA)
LOW-level output voltage on
pin BCA
BCAEN = 1;
Iload = 0.5 mA
Monitor outputs (MON)
Vo(MON) monitor output voltage range
Ro(MON)
IMON < 1.3 mA
−1.3
−
+1.3
V
output resistance on pins MON1
and MON2
−
120
−
Ω
2002 Jun 06
5
Philips Semiconductors
Product specification
Signal processing IC for DVD rewriteable
TZA1031
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Serial bus interface
Vi(logic)
logic input voltage compatibility
2.7
3.3
5.5
V
V
VOH(SROUT)
HIGH-level output voltage on
pin SROUT
TEST = 1;
ISROUT < 1 mA
0.8VDD
−
VDD
VOL(SROUT)
LOW-level output voltage on
pin SROUT
TEST = 1;
ISROUT < 1 mA
0
−
0.2VDD
V
2002 Jun 06
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Philips Semiconductors
Product specification
Signal processing IC for DVD rewriteable
TZA1031
5
BLOCK DIAGRAM
V
V
V
V
V
DD1
63
DD2
39
GND1
61
SSD
54
GNDD
55
SS1
59
SS2
43
GND2
40
46
33
PP-AMP
PPNO
RFP
PPN
41
42
44
25
26
28
29
RFP1
RFN1
RFP2
RFN2
RFN
RF-AMP
RFREF
36
BCA
BCA
10
CALF
A1, A2
12, 11
BETA
TZA1031
58
CCALF
CA1, CA2
56, 57
16
14
8
LASP
ALFA
ALFA
XDN
23 to 18
62
Q1 to Q6
CMPP
TS1
7 to 4
3, 2
D1 to D4
S1, S2
NORM
32
31
64
1
TS2
MON1
MON2
MON
control
51
50
49
48
47
switches
EFMDP
EFMDN
EFMCP
EFMCN
TIMOUT
current
controls
13
53
SROUT
TEST
REGISTERS
AND
LOGIC
EFMTIM
to
ALFA
circuit
37
38
35
SIDA
SICL
SILD
DACs
SERIAL
BUS
INTERFACE
BANDGAP
REFERENCE
60
RREF
MGW477
Fig.1 Block diagram.
7
2002 Jun 06
Philips Semiconductors
Product specification
Signal processing IC for DVD rewriteable
TZA1031
6
PINNING
SYMBOL
PIN
DESCRIPTION
MON2
1
monitor output voltage 2
servo output current
S2
2
S1
3
servo output current
D4
4
servo output current
D3
5
servo output current
D2
6
servo output current
D1
7
servo output current
XDN
n.c.
8
x-position output voltage
not connected; note 1
RF average level output signal
RF bottom level output signal
RF top level output signal
9
CALF
A2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
A1
SROUT
ALFA
n.c.
shift register output for register test mode
alfa output current
not connected; note 1
laser power setpoint signal
not connected; note 1
servo input current
LASP
n.c.
Q6
Q5
servo input current
Q4
servo input current
Q3
servo input current
Q2
servo input current
Q1
servo input current
n.c.
not connected; note 1
positive RF input voltage 1
negative RF input voltage 1
not connected; note 1
RF input voltage 2; positive
RF input voltage 2; negative
not connected; note 1
tilt sensor input current
tilt sensor input current
input PP current
RFP1
RFN1
n.c.
RFP2
RFN2
n.c.
TS2
TS1
PPN
n.c.
not connected; note 1
strobe line of serial bus interface
binary BCA output voltage
data line of serial bus interface
clock line of serial bus interface
positive supply voltage 2
supply ground 2
SILD
BCA
SIDA
SICL
VDD2
GND2
2002 Jun 06
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Philips Semiconductors
Product specification
Signal processing IC for DVD rewriteable
TZA1031
SYMBOL
RFP
PIN
DESCRIPTION
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
positive RF output voltage
negative RF output voltage
negative supply voltage 2
RFN
VSS2
RFREF
n.c.
reference voltage for differential RF output common mode level
not connected; note 1
PPNO
TIMOUT
EFMCN
EFMCP
EFMDN
EFMDP
n.c.
output PP voltage
test output signal of EFMTIM
negative EFM clock input
positive EFM clock input
negative EFM data input
positive EFM data input
not connected; note 1
TEST
VSSD
enable test mode (tie to GND for normal operation)
negative digital supply voltage
digital supply ground
GNDD
CA1
beta circuit external capacitor
beta circuit external capacitor
beta circuit external capacitor
negative supply voltage 1
reference resistor to VSS
CA2
CCALF
VSS1
RREF
GND1
CMPP
VDD1
supply ground 1
CMPP external capacitor
positive supply voltage 1
MON1
monitor output voltage 1
Note
1. For good signal integrity all n.c. pins should be connected to the application board’s ground plane.
2002 Jun 06
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Philips Semiconductors
Product specification
Signal processing IC for DVD rewriteable
TZA1031
MON2
S2
1
2
3
4
5
6
7
8
9
48 EFMCN
TIMOUT
47
S1
46 PPNO
45 n.c.
D4
D3
RFREF
44
43
V
D2
SS2
D1
42 RFN
RFP
XDN
n.c.
41
40 GND2
TZA1031HL
V
39
CALF 10
A2 11
DD2
38 SICL
37 SIDA
36 BCA
A1 12
SROUT 13
ALFA 14
n.c. 15
SILD
35
34 n.c.
LASP 16
33 PPN
MGW478
Fig.2 Pin configuration.
10
2002 Jun 06
Philips Semiconductors
Product specification
Signal processing IC for DVD rewriteable
TZA1031
7
FUNCTIONAL DESCRIPTION
To explain the interaction between the blocks of the device, a detailed block diagram including internal signal names is
shown in Fig.3. The separate blocks and their functions will be explained in Sections 7.1 to 7.8.
G
BWPP
PP
PPN
PP-AMP
PPNO
BWRF, ENNF,
KEQ, ENEQ,
RF1/2, HA, ZCAL
DC , O
RF RF
RF
,
G
RFP1, RFN1
RFP2, RFN2
RFP, RFN
RFREF
RF-AMP
rf-alfa
BCA BCAEN
T
rf-norm
rf-cal
bca-rfp
bca-rfn
TIM0 to TIM6, RST,
ENRW, ENRS, ENALF
BCA
I
BCA
BS
BCTL
rf-beta1
rf-beta2
AINTON
EFMDP
EFMDN
CCALF
CA1,CA2
ASTROBE
RS
BETA
EFMTIM
CALF, A1, A2
EFMCP
EFMCN
r/w
ALF1/2, IAT, IAN, NDYE,
PC/DYE, AN, ENALF,
SQRT
TIMOUT
I
A2
ALFA
LASP
AINTON
r/w
ALFA
INA, CAN, SLASP
RS, r/w
ASTROBE
AINT
CMPP
Q1 to Q6
TS1
alfa-mon
D1 to D4
S1, S2
XDN
NORM
I
I
, I , I , I ,
N1 N2 N3 N4
MIR TW TR
, I , I
,
TS2
OF , OF
R
W
MSEL
MON1
MON2
S4/8, CA/PP, REN4/2, PREN,
FEN4/2, RFCAL, DPD,
Q/NE, PFEN, PXDN, PTLN,
CLMP, VARP, MIR1/2, RTLN,
ALF1/2
REN, FEN, TLN, MIRN,
TILTN, CAN, PW
MON
MGW479
Fig.3 Detailed block diagram.
11
2002 Jun 06
Philips Semiconductors
Product specification
Signal processing IC for DVD rewriteable
TZA1031
7.1
EFMTIM
7.1.1
DATA SIGNAL SYNCHRONIZATION AND READ-WRITE DETECTION
EFMTIM derives from the incoming EFM clock and data signals a signal for switching between read and write, and
several timing signals used by the ALFA block.
The EFMTIM block derives the read/write signal r/w from EFMCP and EFMDP as shown in Fig.4.
READ
WRITE
T
EFMCP, EFMCN
EFMDP', EFMDN'
≤15T
r/w
(18 + D )T
1
WRITE
READ
EFMCP, EFMCN
EFMDP', EFMDN'
(18 + D )T
1
r/w
MGW480
Fig.4 The r/w signal.
The signals EFMDP’ and EFMDN’ are synchronous versions of the input signals EFMDP and EFMDN, clocked at the
rising edge, current LOW-to-HIGH, of EFMCP, i.e. they are the data signals after the first D flip-flop. The read/write
detection is either active or inactive, defined by bit ENRW. When it is inactive (ENRW = 0), r/w = 1 (forced read mode).
When ENRW = 1 a transition from read to write is signalled by the occurrence of two edges in EFMDP and EFMDN within
an interval of 15T or less. Then r/w becomes LOW after (18 + D1)T after the first edge in EFMDP, where D1 is a
programmable parameter.
2002 Jun 06
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Philips Semiconductors
Product specification
Signal processing IC for DVD rewriteable
TZA1031
A transition from write to read occurs when during an interval of 15T no edges are detected in EFMDP and EFMDN. Then
r/w becomes HIGH after (18 + D1)T after the final edge in EFMDP and EFMDN. It should be noted that the state itself of
EFMDP and EFMDN (i.e. HIGH or LOW) is irrelevant for the read/write detection, only the occurrence of transitions
matters.
In general both EFMCP and EFMCN as well as EFMDP and EFMDN will become stationary LOW or HIGH during read,
although this is not guaranteed.
T
T/2
EFMCP
EFMCN
pit
land
pit
land
pit
EFMDP'
EFMDN'
(10 + D )T
2
pit
land
pit
land
LIGHT
RS
m T/2
(n − 2)T/2
1
1
T
pit
land
pit
land
LIGHTA
AINTON
m T/2
2
T
ASTROBE
(n + 1)T/2
T/2
MGW481
2
Fig.5 Signals RS, AINTON and ASTROBE.
2002 Jun 06
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Philips Semiconductors
Product specification
Signal processing IC for DVD rewriteable
TZA1031
The actual laser power signal produced by the laser driver
has a delay (10 + D2)T with respect to EFMDP and
EFMDN (see Fig.5). In the device this actual power signal
is represented by LIGHT, which therefore is delayed
(10 + D2)T of EFMCP and EFMCN with respect to EFMDP
and EFMDN. The signal RS, used for sampling the
RF signal to obtain the disc’s ‘reflection’, is synchronously
derived from LIGHT. It is either active or inactive, defined
by bit ENRS and the state of r/w. When it is inactive
(ENRS = 0 or r/w = 1) RS is always HIGH. When it is
active (ENRS = 1 and r/w = 0) RS goes HIGH after m1
periods T/2 after the trailing edge of LIGHT (i.e. in the
‘land’ region) and LOW after (n1 − 2) periods T/2 after the
rising edge of LIGHT with m1 = 0 to 7 and n1 = 0 to 7. The
duty cycle of EFMCP and EFMCN can be assumed to be
50%.
7.1.3
EFMTIM TEST OUTPUT
An output test signal TIMOUT is defined for the EFMTIM
block. It can be used to check the timing relation between
the ingoing EFM signal and one of the output signals
AINTON, ASTROBE, RS and r/w. The selection of the
output signal is done by the 3-bit register TIM6, where the
MSB is used to enable or disable TIMOUT.
Remark: the voltage swing on TIMOUT is from 0 V to VDD
so direct interfacing to digital circuitry on a 3.3 V supply is
not generally possible.
,
7.1.4
EFMTIM RESET
The EFMTIM block has a local reset input which is
software-controlled by bit RST of the serial input register.
By sending the sequence 0 → 1 → 0 to bit RST the
asynchronous reset circuit in EFMTIM is loaded and the
actual reset is established after a number of edges (<16)
on EFMCP and EFMCN.
The signals AINTON and ASTROBE are derived from
LIGHTA (‘advanced light’) which is delayed (9 + D2) EFM
clocks T with respect to EFMCP and EFMCN. AINTON
and ASTROBE are either (together) active or inactive,
defined by bit ENALF. When they are inactive
(ENALF = 0) both AINTON and ASTROBE are LOW.
When they are active (ENALF = 1) AINTON goes HIGH
after m2 periods T/2 after the rising edge of LIGHTA (i.e. in
the ‘pit’ region) and ASTROBE goes HIGH after (n2 + 1)
periods T/2 after the rising edge of LIGHTA. The pulse
duration of ASTROBE is always T, and a period T/2 later
AINTON also goes LOW. This implies that the pulse
duration of AINTON equals (n2 − m2 + 4) periods T/2.
7.1.2
EFMTIM INPUT INTERFACE
To minimize crosstalk by the high frequency signals
EFM clock and EFM data, the inputs for these signals are
made balanced current mode inputs. The inputs
EFMDP, EFMDN, EFMCP and EFMCN show a resistance
of about 100 Ω to GND. A logic HIGH-level is received if
IEFMDP > IEFMDN or IEFMCP > IEFMCN. If IEFMDP < IEFMDN or
IEFMCP < IEFMCN a logic LOW-level is received. The
interface is intended to be driven from standard
complementary CMOS outputs with a resistor in series.
For instance EFMDP is connected to EFMdata and
EFMDN is connected to EFMdata, both with a series
resistor. To achieve sufficient speed, the current
corresponding to a HIGH-level should be large enough,
and therefore the resistors should not be too large. For
applications up to 16 × CD or 4 × DVD write a high level
current of 330 µA is sufficient, corresponding to a 10 kΩ
series resistance for 3.3 V supply.
2002 Jun 06
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7.1.5
EFMTIM CONTROL
Table 1 EFMTIM control parameters
PARAMETER
NAME
PURPOSE
r/w signal delay parameter for EFMTIM
TIM0[4:0]
TIM1[5:0]
TIM2[2:0]
TIM3[2:0]
TIM4[2:0]
TIM5[2:0]
TIM6[2:0]
D1
D2
LIGHT signal delay parameter for EFMTIM
m1
n1
RS signal rising edge delay parameter for EFMTIM
RS signal falling edge delay parameter for EFMTIM
AINTON signal rising edge delay parameter for EFMTIM
ASTROBE signal rising edge delay parameter for EFMTIM
EFMTIM test mode control parameter; see Table 2
m2
n2
TIM6
Table 2 TIMOUT selection
TIM6[2]
TIM6[1]
TIM6[0]
TIMOUT
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
AINTON
ASTROBE
RS
r/w
0
Table 3 EFMTIM control bits
BIT NAME
LOGIC 1
LOGIC 0
ENRS
ENRW
ENALF
enable sampling of RF signal
disable sampling of RF signal; RS = 0
enable automatic read/write detection
enable ALFA measurement
disable automatic read/write detection; r/w = 0
disable ALFA measurement; AINTON = 0;
ASTROBE = 0
7.2
NORM
The NORM block produces various normalized signals for servo purposes and for the ALFA block. The signals TILTN,
FEN, REN, TLN, MIRN and PW are multiplexed with detector signals Q1 to Q6. The top level of the NORM block with
it’s sub blocks is shown in Fig.6. The individual blocks of NORM will be explained in Sections 7.2.1 to 7.2.9.
2002 Jun 06
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V(Q1) to V(Q6)
mir
to MON
TILTN
Q1 to Q6
AUX
TS1
TS2
satsum
TILT
NORM
Q
S
FEN4/2
PFEN
I
OF , OF
R W
r/w
DOC1
V(Q1) to V(Q4)
FEN
to MON
FOC
(1) TILTN
(2) TLN
(3) REN
(4) FEN
(5) MIRN
(6) PW
I
I
DOC2
DOC3
REN4/2, PREN, DPD, PXDN,
RFCAL, S4/8, CA/PP
rf-cal
Q/NE
V(Q1) to V(Q6)
Q5, Q6
XDN
D1 to D4,
S1, S2
RAD
REN
(1) Q1
(2) Q3
(3) Q2
(4) Q4
(5) Q5
(6) Q6
to MON
CMPP
RTLN, PTLN,
CLMP, CA/PP
I
DOC4
V(Q1) to V(Q6)
satsum
TL
TLN
Q
S
to MON
VARP, ALF1/2,
MIR1/2
I
I
I
, I
to I
,
RS
r/w
MIR
TW TR
N1
r/w
N4
to MON
MIRN, CAN
rf-norm
I
to I
DOC4
DOC
DOC1
LASP
mir
to MON
CANORM
PW
satsum
to MON
to ALFA
SLASP
INA
MGW482
Fig.6 Top level of the NORM block.
16
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7.2.1
AUX BLOCK
7.2.2
DOC BLOCK: NORMALIZATION AND DROP-OUT
CONCEALMENT
The blocks FOC, RAD and TL contain normalizer circuits.
A normalizer circuit N with input currents I1 and I2
produces the following dropout-concealed output
current IO:
handbook, halfpage
V(Q1) to V(Q6)
mir
I1 – I2
Q1 to Q6
AUX
IO
=
× I
(1)
--------------
DOC
satsum
I1 + I2
Q
S
where IDOC is a dropout-concealed scaling current that is
chosen according to the modulation depth of the signal to
be normalized, produced by the DOC circuit. The NORM
block has one dropout-concealment circuit that delivers
various currents, IDOC1 through IDOC4, for the normalizer
circuits. The dropout-concealed scale currents IDOCi
(i = 1 to 4) are defined as IDOCi = GDOC × INi, where INi are
programmable reference currents and GDOC is defined by:
MGW483
Fig.7 AUX block.
The input currents Qi (i = 1 to 6) are converted into
voltages V(Qi) = VTln(Qi/IS) for use in the normalizer
circuits ((see Fig.7). Furthermore, AUX produces the
signals Qs, satsum and mir, defined as:
GDOC = 1 if CAN > IT
GDOC = CAN/IT if CAN ≤ IT
where IT is the threshold level for dropout-concealment
with which the normalized sum current CAN is compared.
If CAN drops below IT the scale factor GDOC will decrease
linearly with CAN in order to prevent ‘dividing-by-zero’.
There is a threshold ITW for write and a threshold ITR for
read: IT = ITW if r/w = 0, IT = ITR if r/w = 1. The currents INi,
ITW and ITR are programmable via the serial bus.
QS = Q1 + Q2 + Q3 + Q4
Satsum = Q5 + Q6
The mir signal is defined in Table 4.
Table 4 The mir signal definition
BIT S4/8
BIT CA/PP
mir
0
0
1
1
0
1
0
1
Qs
Qs
Q5 + Q6 + QS
Q5 + Q6 + QS
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7.2.3
FOC BLOCK: FOCUS SERVO SIGNAL NORMALIZATION
A schematic representation of the FOC circuit is shown in Fig.8.
I
I
DOC1
N
FEN4/2
PFEN
V(Q1)
V(Q3)
V
V
I
I
FEN
+/−
0.5
r/w
DOC1
N
OF
W
V(Q4)
V(Q2)
OF
R
MGW484
Fig.8 FOC block.
The normalized focus error signal FEN is based on either 2 or 4 input currents, defined by FEN4/2. If FEN4/2 = 1, then
4 input currents are used. The normalization blocks (N) perform the function described in equation (1) in Section 7.2.2.
An offset can be applied which depends on the state of r/w (to compensate for chromatic aberration in the optics). If
r/w = 1 (read mode) OFR is used. Finally the polarity of FEN can be reversed by setting PFEN = 1. FEN is available on
output D2 if Q/NE = 0. FEN can also be observed via the MON block.
7.2.4
RAD BLOCK: RADIAL SERVO SIGNAL NORMALIZATION
I
S4/8, CA/PP
DOC2
N
REN4/2
DPD
PREN
V(Q1) to V(Q6)
V
I
LPF
+/−
REN
CMPP
Q5
Q6
+
−
I
S4/8, CA/PP
DOC3
N
V
CAL
PXDN
RFCAL
R
XDN
+
+
V(Q1) to V(Q6)
V
I
I/V
+/−
XDN
rf-cal
MGW485
Fig.9 RAD block.
18
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The normalized radial error signal REN is based on either
2 or 4 input currents, defined by REN4/2 and DPD (see
Fig.9). If DPD = 0 and REN4/2 = 0 the associated tracking
method is either 1-spot PP (4 segments), 3-spot CA or
3-spot PP. If DPD = 0 and REN4/2 = 1 the associated
tracking method is 1-spot PP (8 segments). In that case
the offset correction signal obtained from the lower branch
is low-pass filtered before it is added to the main
Additionally, the signal XDN (normalized spot position) is
generated. XDN is either based on 3-spot PP, 1-spot PP
(4 segments) or on 1-spot PP (8 segments). For
RFCAL = 1 the XDN output is used to output an amplified,
low-pass filtered version of the signal rf (see Section 7.3).
This can be used to eliminate the offset in the RF path. It
should be noted that the output of rf-call is unipolar, so
only positive outputs are possible.
normalized PP. An external capacitor named CCMPP
,
connected to pin CMPP, defines the 3 dB frequency of the
filter. If DPD = 1 the tracking method is DPD and REN is
obtained from the difference of Q5 and Q6. Finally the
polarity of REN is reversed if PREN is set to logic 1.
7.2.5
TL BLOCK: TRACK LOSS SERVO SIGNAL
CA/PP
I
DOC4
Q
S
X
RTLN
satsum
CLMP
PTLN
Q
1/3
S
CLAMP
TLN
+/−
V(Q1) to V(Q6)
V
I
N
MGW486
Fig.10 TL block.
If RTLN = 1 the normalized trackless signal TLN is only valid for the tracking methods 3-spot CA and 3-spot PP. For
RTLN = 0 TLN is the low-pass filtered central sum signal QS, scaled with a factor 1/3.
The output of TLN (both positive and negative) can be clamped to a maximum value ICL in order to deal with media that
have a high and low modulation depth of TLN on one disc (e.g. written and blank regions). The clamp can be
enabled/disabled with bit CLMP. The polarity of TLN is reversed by setting PTLN = 1. TLN is sent as D4 to the output if
Q/NE = 0, a copy is sent to the MON block.
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7.2.6
CANORM BLOCK: CA SIGNAL NORMALIZATION CIRCUIT
RS
MIR1/2
srf
rf-norm
LPF2
ALF1/2
I
0
mir
I
MIR
INA
CAN
satsum
MIRN
r/w
MIR1/2
4.0
VARP
RS
I
01
I
PR
18.0
LPF2
LASP
SLASP
PW
1/7
MGW487
Fig.11 CANORM block.
When RS is active, rf = rf-norm is sampled and filtered
and then normalized on the laser power (see Fig.11).
The mirror signal mir must be normalized on the laser
power. When Q1 to Q6 are sampled and filtered (in the
TZA1030), mir is sampled and filtered too and hence LASP
must be sampled and filtered also, in order to obtain a
quotient MIRN which is a normalized reflection signal free
of EFM. In some situations the laser power does not vary
during sampling, while LASP does. In those situations a
reference current IPR is used as a read power reference. If
the signals Q1 to Q6 are not sampled during write in the
TZA1030, the mirror signal MIRN must be based on rf,
which is selected by setting MIR1/2 to 0. MIRN is sent as
S1 to the output if Q/NE = 0, a copy is sent to the MON
block. The output current PW is derived from the input
current LASP and is used for power calibration purposes.
When rf is sampled and filtered, LASP must be sampled
and filtered too, in order to obtain a quotient which is a
normalized reflection signal free of EFM. The signals srf
and SLASP are the sampled and filtered versions of rf and
LASP, respectively, which are used in the ALFA block. For
dye media the laser power does not vary during sampling,
while LASP does. In those situations a reference current
IPR is used as a read power reference. A copy of CAN is
sent to the MON block. The signal AIN is used for reflection
measurement in the ALFA block. It is either based on
central spot detection (ALF1/2 = 0) or on satellite spot
detection (ALF1/2 = 1). In the former case sampling during
the erase period of rf-norm takes place using RS, in the
latter case sampling is done in the TZA1030.
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7.2.7
TILT BLOCK: TILT SENSOR NORMALIZATION CIRCUIT
7.2.8
OUTPUT CURRENT POLARITIES
The currents TILTN, FEN, REN and TLN are bipolar
currents and are sent to D1 to D4 if Q/NE = 0. The
currents MIRN and PW are unipolar and are sent to
S1 and S2 if Q/NE = 0. They are negative according to the
definition used in this document, i.e. sourced by the
device. If Q/NE = 1 the input currents Q1 to Q6 are
transferred directly to D1 to D4, S1 and S2. They are, in
general, bipolar currents.
handbook, halfpage
TS1
TS2
N
TILTN
MGW488
Fig.12 TILT block.
In normal mode (ADTST = 0) the normalization block
produces a normalized tilt error signal TILTN according to:
TS1 – TS2
TS1 + TS2
TILTN =
× A DOC × IS0
(2)
-----------------------------
where ADOC is a drop-out concealed reference current
with:
ADOC = 1 if (TS1 + TS2) > ITT
ADOC = (TS1 + TS2)/ITT if (TS1+TS2) < ITT
The signal TILTN is sent as D1 to the output if Q/NE = 0.
A copy is sent to the MON block (see Fig.12).
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7.2.9
CONTROL SIGNAL OVERVIEW
Table 5 Single bit controls
BIT NAME
LOGIC 1
LOGIC 0
S4/8
4 segment central detector mode
central aperture mode
8 segment central detector mode
push-pull mode
CA/PP
FEN4/2
PFEN
REN4/2
PREN
PXDN
RFCAL
DPD
normalized focus error signal from 4 inputs
inverted focus error polarity
normalized focus error signal from 2 inputs
normal focus error polarity
normalized radial error signal from 4 inputs
inverted radial error polarity
normalized radial error signal from 2 inputs
normal radial error polarity
inverted spot position polarity
normal spot position polarity
normal mode of XDN output
connect rf-call signal to XDN output
DPD tracking method on
DPD tracking method off
PTLN
RTLN
CLMP
Q/NE
inverted track loss signal polarity
TLN signal for 3 spot CA and PP methods
activate TLN signal clamp
normal track loss signal polarity
TLN signal derived from central sum signal
disable TLN signal clamp
detector signals on servo outputs
use LASP input signal as read power reference
MIRN signal based on Q1 to Q6 signals
error signals on servo outputs
use internal read power reference Ipr
MIRN signal based on rf signal
VARP
MIR1/2
Table 6 Analog control parameters
PARAMETER
NAME
IMIR
PURPOSE
MIN.
1.5
LSB
1.5
MAX.
24
UNIT
µA
IMIR[3:0]
OFR[3:0]
OFW[3:0]
IN1[3:0]
IN2[3:0]
IN3[3:0]
IN4[3:0]
ITW[3:0]
current level setting for MIRN signal
focus error offset for read mode
focus error offset for write mode
OFR
OFW
IN1
−4
−4
+0.5
+0.5
2
+3.5
+3.5
34
µA
µA
µA
µA
µA
µA
µA
normalizer reference current for FEN signal 4
normalizer reference current for REN signal 10
normalizer reference current for XDN signal 16
normalizer reference current for TLN signal 20
IN2
10
160
256
470
6.4
IN3
16
IN4
30
ITW
drop-out concealment threshold value for
write mode
0.4
0.4
ITR[3:0]
ITR
drop-out concealment threshold value for
read mode
0.4
0.4
6.4
µA
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7.3
RF-AMP
7.3.1
DATA PATH AMPLIFIER AND FILTERING
RFP2
ENEQ
DC
RF
KEQ BWRF
ENNF BWRF
G
RF
HA
RFP1
+
a
−
RFP
RFN
+
rf
rf
VGA
NF
RF1/2
EQ
b
DC-CONTROL
−
RFN2
RFN1
RFREF
bca-rfp
bca-rfn
O
RF
rf-beta1
R
rf
rf-beta2
rf-norm
OFFSET
CONTROL
V/I
rf-alfa
ZCAL
R
cal
V
ref
I/V
rf-cal
0
MGW489
Fig.13 RF-AMP circuit.
The source signal for the RF-AMP is either the differential
voltage pair (RFP1 and RFN1) or (RFP2 and RFN2). The
selection is done via the serial bus with bit RF1/2 (see
Fig.13). A DC-control function is included to allow the
output signal to be DC-coupled to a channel decoder. The
relation between input and output of the DC-control block
is given by rfb = rfa − DCRF. The RF-AMP has a Variable
Gain Amplifier (VGA) that is controlled via the serial bus.
The output of the VGA is sent to a filter section that
consists of an Equalizer (EQ) and a Noise Filter (NF),
which are controlled by KEQ, ENEQ, BWRF and ENNF.
The equalizer has a transfer function H1(s) which is
modelled after a target transfer function He(s):
The corner frequency ω0(RF) = 2π × f0(RF) is programmable
via control parameter BWRF. The equalizer is switched on
with bit ENEQ.
The noise filter has a transfer function H2(s) which is
modelled after a 3rd-order Butterworth low-pass filter with
target transfer function Hn(s):
1
1
H n (s ) =
×
(4)
-------------------------------------------------- -------------------------
s2
s
s
1 +
---------------
1 +
+
----------------- ---------------
ω 0(RF)
2
ω 0(RF)
ω0(RF)
The corner frequency ω0(RF) is equal to that of the
equalizer filter.
s2
Finally the low-ohmic differential output voltage is
1 – k ×
------------------
2
produced by a driver stage, where input voltage RFREF
defines the common mode voltage of RFP and RFN.
Bit HA selects between a low output level (HA = 0) and a
high output level (HA = 1).
ω0(RF)
1
He(s) =
×
(3)
------------------------------------------------------------- ----------------------------------
s 2
s
s
1 + τ ×
---------------
1 +
+ α ×
---------------
------------------
2
ω 0(RF)
ω 0(RF)
ω 0(RF)
This represents a 3rd-degree equi-ripple phase filter with a
good delay response. The boost factor k is programmable
via the serial interface with control bit KEQ.
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The RF-AMP produces four derivative rf-signals for use in
other circuits. They are sent as rf-beta1, rf-beta2, rf-norm
and rf-alfa to the BETA, NORM and ALFA blocks. The
outgoing signals are offset-compensated rf-currents
handbook, halfpage
rf-cal
(V)
defined by:
rfa + ORF
rf =
-----------------------
Rrf
V
ref
The offset voltage ORF is set via the serial bus to obtain
rf = 0 if the laser is off. This offset is calibrated by
measuring voltage rf-cal via the XDN output. The
rf calibration signal is biased at a reference voltage Vref,
which can be measured separately by setting ZCAL = 1.
During offset calibration it must be kept in mind that the
rf-cal output can only be positive. Negative offsets can be
present in the system but will not be visible on the rf-cal
output, which will not go below Vref. The behaviour of rf-cal
is illustrated in Fig.14.
rf
(V)
a
MGW490
Fig.14 Output of rf-cal.
The balanced voltages bca-rfp and bca-rfn are derived as
well as input for the BCA circuit.
7.4
PP-AMP
7.4.1
PUSH-PULL CHANNEL AMPLIFIER AND FILTERING
BWPP
LPF
G
PP
PPN
I/V
PPNO
MGW491
Fig.15 PP-AMP circuit.
The input current PPN is converted into a voltage and then the gain is set by GPP, which is controlled via the serial bus
(see Fig.15). The bandwidth of the output signal is determined by a 1st-order Low-Pass Filter (LPF) which is controlled
by parameter BWPP.
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7.5
ALFA
7.5.1
ALFA MEASUREMENT CIRCUIT FOR RUNNING OPC
ENALF
A
ALF1/2
AINTON
N
ASTROBE
S&H
∫
+
PEAK
DETECTOR
rf-alfa
C
A
−
NDYE
I
I
I
LASP
AN
AT
A2
ALF1/2
CAN
G
+
d
−
CAN
NDYE
I
ref1
DOC
alfa-dye
I
ref2
r/w
r/w
SQRT
INA
PC/DYE
I
alfa-mon
LASP
AN
1/7
ALF1/2
0
0
ALFA
alfa-pc
4.0
9.0
SLASP
MGW492
I
ref2
Fig.16 ALFA circuit.
The task of the ALFA block is to measure the parameter ALFA for use as an error signal in the running-OPC control loop
of a dye or phase change writer. The two media types require different alfa measurement methods. For dye media the
decrease in pulse area of the returning signal during a write pulse is taken (‘absorption measurement’), for phase change
media the laser power incident on the recording layer is used, which is also derived from the returning signal (‘reflection
measurement’). For both media types two methods for alfa measurement are implemented, which are defined in
Sections 7.5.2 and 7.5.3. Selection of the 4 possible ALFA methods is done by bits PC/DYE (phase change or dye
media) and ALF1/2 (first or second method), see Fig.16.
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7.5.2
DYE MEDIA
For dye media the first method (ALF1/2 = 1) uses a circuit where the absorption area is measured by integrating the
difference between the peak level of the returning signal rf and rf itself during a period determined by the HIGH level of
AINTON. A part of that area is used for ALFA by sampling it at the trailing edge of ASTROBE, which occurs before the
trailing edge of AINTON. This results in an effective integration period T. The resulting signal is optionally normalized on
the disc reflection signal CAN. Method 1 produces an energy quantity alfa-dye, expressed in [J]/sample. The transfer
functions defining alfa-dye for the first method are shown below. The parameter NDYE controls the normalization of the
signal.
For NDYE = 0:
IAN
1
alfa-dye = G ×
×
(rfPEAK – rf) × dt ×
(5)
(6)
------
CA
-------
IAT
d
∫
Tα
For NDYE = 1:
IAR
1
alfa-dye = G ×
×
(rfPEAK – rf) × dt ×
------
------------
CAN
d
∫
CA
Tα
I
AT and IAN are parameters set via a 3-wire interface register.
IAR is a drop-out concealed version of IAN
.
IAR = IAN if CAN > IAT; IAR = IAN × CAN/IAT if CAN ≤ IAT
.
It should be noted that if NDYE = 0 the drop-out concealment acts as a programmable gain. The integrator capacitor
CA = ANC0, with AN = 2−AN and C0 a fixed reference value of 50 pF, can be programmed to match the integration time Tα
associated with the applied writing speed.
The second method (ALF1/2 = 0) for dye media measures the absorption area by directly integrating and sampling the
returning write pulse, then normalizing it on the actual laser peak write power LASP, and after an optional normalization
on the disc reflection signal CAN, subtracting the result from a reference current IA2. Method 2 produces a dimension
less relative alfa-dye, expressed as a ratio of the non-writing pulse area. The corresponding relations for alfa-dye are
shown in equations (7) and (8).
For NDYE = 0:
Iref1
I AN
1
alfa-dye = IA2 – G ×
×
rfdt ×
×
(7)
(8)
------
CA
-------------- -------
d
∫
LASP IAT
Tα
For NDYE = 1:
Iref1
I ref2
I AR
1
alfa-dye = IA2 – G ×
×
rfdt ×
×
×
------
-------------- ------------
---------
Iref2
d
∫
CA
LASP CAN
Tα
Here IA2 serves as a reference current that represents the peak level of rf normalized on the write power LASP and the
reflection signal CAN. Because IA2 is not accurately known in advance, it must be calibrated (outside the device) to yield
alfa-dye = 0 if pit formation is absent.
7.5.3
PHASE CHANGE MEDIA
For phase change media the produced alfa is either proportional to ‘P × R’ or to ‘P√R’, where P is the optical power and
R is the reflection. These quantities are measures of the laser power incident on the recording layer. There are two
methods defined. The first method (ALF1/2 = 1) uses the satellite spots to measure the disc reflection. The reflection
signal is the satellite-sum signal satsum, normalized on the sampled power signal SLASP. If SQRT = 1 a square-root
operation is applied and the result is multiplied by LASP to give alfa-pc. The relations for alfa-pc are shown in
equations (9) and (10).
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For SQRT = 0:
IAN
satsum
--------- ----------------------------
Iref2 9 × SLASP
alfa-pc =
×
× LASP
(9)
For SQRT = 1:
IAN
satsum
---------------------------- × LASP
9 × SLASP
alfa-pc =
×
(10)
---------
Iref2
The second method for phase change media (ALF1/2 = 0) uses the signal from the central spot rather than from
satellite spots to measure the disc reflection. The reflection signal is the sampled rf-signal srf, normalized on the sampled
power signal SLASP.
For SQRT = 0:
IAN
srf
--------- ----------------------------
Iref2 4 × SLASP
alfa-pc =
alfa-pc =
×
× LASP
(11)
(12)
For SQRT = 1:
IAN
srf
---------------------------- × LASP
4 × SLASP
×
---------
Iref2
7.5.4
ALFA CIRCUIT GENERAL
The ALFA circuit is enabled by setting bit ENALF = 1. For ENALF = 0 the ALFA output current remains zero. A copy of
the ALFA output current is sent to the MON block. The polarity of the ALFA output current is negative, i.e. the current is
sourced by the device.
7.6
BETA
7.6.1
BETA MEASUREMENT CIRCUIT FOR WRITE POWER CALIBRATION
I
BS
BCTL
+
PEAK
DETECTOR
V
V
V
beta
beta
beta
A1
−
BCTL
LPF
rf-beta1
rf-beta2
CA1
CALF
A2
BCTL
CCALF
+
−
PEAK
DETECTOR
MGW493
CA2
Fig.17 BETA circuit.
2002 Jun 06
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Philips Semiconductors
Product specification
Signal processing IC for DVD rewriteable
TZA1031
The BETA block measures of the input signal rf the average level CALF and the top and bottom peak levels A1 and A2.
Using rf-beta1 = rf-beta2 = rf, the signal relations for the BETA block are given in equations (13), (14) and (15).
LPF(rf)
IBS
CALF =
× V
(13)
(14)
(15)
------------------
beta
(rf – LPF(rf))
A1 =
A2 =
peak × V
------------------------------------------
IBS
beta
beta
(LPF(rf) – rf)
peak × V
------------------------------------------
IBS
The DC gain from (RFP−RFN) to A1, A2 and CALF is given by:
Vbeta
Gbeta
=
and can be controlled via the parameter IBS. The typical value of Vbeta is 1.25 V.
--------------------
I
BS × Rrf
7.7
BCA
7.7.1
BURST CUTTING AREA SIGNAL PROCESSING CIRCUIT
BCAEN
comp
BCA
T
bca-rfp
bca-rfn
BCA
LPF
D/S
MGW494
Fig.18 BCA circuit.
The BCA block filters the incoming signal rf-bca after which a comparator compares it with a programmable threshold
level BCATH. The low-pass filter is modelled after a target filter Ht(s) which is given in equation (16).
1
1
Ht(s) =
×
(16)
---------------------------------------------------------------------- ----------------------------------------------------------------------
s2
s
s 2
s
1 +
+
1 +
+
--------------------- --------------------------------
--------------------- --------------------------------
2
2
Q 1 × ω 0(BCA)
Q 2 × ω 0(BCA)
ω0(BCA)
ω 0(BCA)
Where ω0(BCA) = 2 × π × f0(BCA) is a fixed frequency of 300 kHz. Control bit BCAEN allows the BCA circuit to be enabled
(BCAEN = 1) or disabled (BCAEN = 0). If BCAEN = 0 the output signal remains LOW, irrespective of the input signals.
2002 Jun 06
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Product specification
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TZA1031
7.8
MON
7.8.1
MONITOR CIRCUIT FOR VARIOUS INTERNAL SERVO SIGNALS
The monitor circuit converts two input currents into bipolar voltages. The two input currents are selected via the serial
bus from a number of possible currents. The currents REN, TLN, FEN, MIRN, CAN, TILTN and PW come from the
NORM block and the current ALFA from the ALFA block (see Fig.3). The signals REN, TLN, FEN and TILTN are bipolar;
MIRN, ALFA, CAN and PW are unipolar. The output voltages for the unipolar signals are positive.
The 6-bit parameter MSEL defines the selection of the two input currents that will be I/V converted and will appear as
MON1 and MON2 at the output.
Table 7 MON block selection bits
MONITOR 1
MONITOR 2
MSEL[2]
MSEL[1]
MSEL[0]
MON[1]
REN
MSEL[5]
MSEL[4]
MSEL[3]
MON[2]
REN
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
TLN
TLN
FEN
FEN
MIRN
ALFA
PW
MIRN
ALFA
PW
CAN
CAN
TILTN
TILTN
The selection tables for MON1 and MON2 are identical, although a particular signal is only defined to appear at either
MON1or MON2, that is, if e.g. MSEL[5:0] = 000000, the outputs MON1 and MON2 are not defined (although the setting
for MSEL is not illegal). In the application different signals must be selected for MON1 and MON2.
For Q/NE = 1 the monitor outputs are distorted due to excess currents in the denominators of the various parameters.
2002 Jun 06
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TZA1031
7.9
Serial bus: interface to system controller
7.9.1
TIMING RELATIONS FOR SERIAL BUS CONTROL
SICL
t
t
clk(L)
clk(H)
t
su(strt)
t
T
clk
h(D)
t
su(D)
SIDA
SILD
D0
A3
t
su(load)
MGW495
Fig.19 Single-word transmission.
SICL
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 A0 A1 A2 A3
D0 D1 D2 D3 D4
A1 A2 A3
SIDA
SILD
t
load(H)
MGW496
Fig.20 Example of a two-word transmission.
2002 Jun 06
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TZA1031
7.9.2
OPERATION
During a transmission the serial data is first stored into an
input shift register. At the rising edge of SILD the contents
of the input register is copied into the addressed register.
This is also the moment the programmed information
becomes effective.
Programming of the control registers of the device is done
by means of the serial bus. The circuitry is formed by a
serial input shift register and a number of registers to store
the data. There is no Power-on reset. Control register
settings will be random at power-on, so to ensure proper
operation all registers must be programmed at least once.
The input pins have CMOS compatible threshold levels for
both 3.3 and 5 V supplies.
If required the bus lines can be connected in parallel with
a 3-wire interface. The protocol needs no switching of the
data line during SICL = HIGH. This means that other
3-wire interface devices will not recognise any start or stop
command. Control words addressed to the device should
uniquely go with the SILD signal. When SILD = HIGH, the
TZA1031 will not respond to any signal on SIDA or SICL.
7.10 Control register of the device
7.10.1 GENERAL CONTROL FORMAT
The device is controlled by means of a serial bit register. To keep programming fast and efficient, the control bits are sent
in 16-bit units. Four of these bits are meant as address. Each address contains 12 data bits.
Table 8 General register programming format
ADDRESS
A2 A1
DATA
D6 D5
A3
A0
D11 D10
D9
D8
D7
D4
D3
D2
D1
D0
MSB
LSB
LSB is sent out first.
A detailed description of the programmable parameters can be found in Tables 10, 11 and 12.
Important: There is no Power-on reset function present. In order to prevent unpredictable states at power on, it is
necessary to program all registers before starting normal operation.
2002 Jun 06
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7.10.2 REGISTER DEFINITIONS
Table 9 Register layout
A[3:0]
D11
S4/8
D10
D9
D8
D7
D6
D5
D4
D3
DPD
D2
D1
D0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
CA/PP
IMIR[2]
IN3[2]
FEN4/2
IMIR[1]
IN3[1]
PFEN
IMIR[0]
IN3[0]
REN4/2
OFR[3]
IN2[3]
PREN
OFR[2]
IN2[2]
PXDN
OFR[1]
IN2[1]
RFCAL
OFR[0]
IN2[0]
PTLN
RTLN
CLMP
IMIR[3]
IN3[3]
OFW[3]
IN1[3]
OFW[2]
IN1[2]
OFW[1] OFW[0]
IN1[1] IN1[0]
GRF[3]
GRF[2]
GRF[1]
GRF[0]
DCRF[5] DCRF[4] DCRF[3] DCRF[2] DCRF[1] DCRF[0]
ITW[3]
ITW[2]
ENRS
ITW[1]
ENRW
TIM1[4]
TIM5[0]
ITW[0]
ITR[3]
ITR[2]
ITR[1]
ITR[0]
IN4[3]
IN4[2]
IN4[1]
IN4[0]
ENALF
TIM6[2]
TIM1[3]
TIM4[2]
TIM6[1]
TIM1[2]
TIM4[1]
TIM6[0]
TIM1[1]
TIM4[0]
Q/NE
VARP
MIR1/2
TIM0[0]
TIM2[0]
RST
TIM1[5]
TIM5[1]
TIM1[0]
TIM3[2]
TIM0[4]
TIM3[1]
TIM0[3]
TIM3[0]
TIM0[2]
TIM2[2]
TIM0[1]
TIM2[1]
TIM5[2]
KEQ
BWRF[6] BWRF[5] BWRF[4] BWRF[3] BWRF[2] BWRF[1] BWRF[0]
RF1/2
ORF[5]
ADTST
ORF[4]
DACC
ORF[3]
ENEQ
GPP[3]
AN[0]
ORF[2]
ENNF
GPP[2]
ALF1/2
IAT[0]
ORF[1]
ZCAL
ORF[0]
HA
BWPP[2] BWPP[1] BWPP[0]
GPP[1]
NDYE
IAN[1]
GPP[0]
PC/DYE
IAN[0]
IA2[5]
BCTL[2] BCTL[1] BCTL[0]
STBY SQRT
IA2[4]
IA2[3]
IA2[2]
IBS[4]
IA2[1]
IBS[3]
IA2[0]
IBS[2]
AN[2]
IBS[1]
AN[1]
IBS[0]
IAT[1]
MSEL[5] MSEL[4] MSEL[3]
MSEL[2] MSEL[1] MSEL[0] BCAT[2] BCAT[1] BCAT[0] BCAEN
Philips Semiconductors
Product specification
Signal processing IC for DVD rewriteable
TZA1031
Table 10 Control bit descriptions
ADDR. BIT NAME
LOGIC 1
LOGIC 0
BLOCK
0H
S4/8
4 segment central detector mode
central aperture mode
8 segment central detector mode
push-pull mode
NORM
NORM
CA/PP
FEN4/2
normalized focus error signal from
4 inputs
normalized focus error signal from
2 inputs
NORM
PFEN
inverted focus error polarity
normal focus error polarity
NORM
NORM
REN4/2
normalized radial error signal from
4 inputs
normalized radial error signal from
2 inputs
PREN
PXDN
RFCAL
DPD
inverted radial error polarity
inverted spot position polarity
connect rf-cal signal to XDN output
DPD tracking method on
normal radial error polarity
normal spot position polarity
normal mode of XDN output
DPD tracking method off
NORM
NORM
NORM
NORM
NORM
NORM
PTLN
RTLN
inverted track loss signal polarity
normal track loss signal polarity
TLN signal for 3 spot CA and
PP methods
TLN signal derived from central sum
signal
CLMP
ENALF
ENRS
ENRW
Q/NE
activate TLN signal clamp
disable TLN signal clamp
NORM
ALFA
6H
enable ALFA measurement
disable ALFA measurement
enable sampling of RF signal
enable automatic read/write detection
detector signals on servo outputs
disable sampling of RF signal
disable automatic read/write detection
error signals on servo outputs
use internal read power reference Ipr
EFMTIM
EFMTIM
NORM
NORM
VARP
use LASP input signal as read power
reference
MIR1/2
RST
MIRN signal based on Q1 to Q6 signals MIRN signal based on rf-signal
NORM
7H
9H
AH
BH
enable EFMTIM reset mode
K parameter of RF equalizer set to 6
select RF input #1
EFMTIM reset off
EFMTIM
RF-AMP
RF-AMP
KEQ
K parameter of RF equalizer set to 4
select RF input #2
RF1/2
ADTST(1) internal test mode
normal operating mode
normal operating mode
disable RF equalizer
DACC(1)
ENEQ
ENNF
ZCAL
internal test mode
enable RF equalizer
enable RF noise filter
RF-AMP
RF-AMP
RF-AMP
disable RF noise filter
force zero input for RF calibration
measurement
RF calibration measurement enabled
HA
select high gain/high voltage swing for
RF output
select low gain/low voltage swing for
RF output
RF-AMP
DH
ALF1/2
NDYE
ALFA measurement, first method
ALFA-DYE normalization on
ALFA measurement, second method
ALFA-DYE normalization off
ALFA
ALFA
ALFA
PC/DYE
ALFA measurement for phase change
media
ALFA measurement for dye media
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TZA1031
ADDR. BIT NAME
LOGIC 1
set to standby mode
LOGIC 0
set to active mode
BLOCK
FH
STBY
SQRT
take square root in ALFA-PC
measurement
no square root in ALFA-PC
measurement
ALFA
MSEL[5:0] monitor block control signal
BCAEN BCA circuit enabled
MON
BCA
BCA circuit disabled
Note
1. These bits must be reset to zero at power-on by the user.
Table 11 Analog control parameters
ADDR.
PARAM. NAME
PURPOSE
REF.
MIN.
1.5
LSB MAX. UNIT
1H
IMIR[3:0]
OFR[3:0]
OFW[3:0]
IN3[3:0]
IMIR
OFR
OFw
IN3
current level setting for MIRN signal
focus error offset for read mode
focus error offset for write mode
NORM
NORM
NORM
NORM
1.5
24
µA
µA
µA
µA
−4
−4
16
+0.5
+0.5
16
+3.5
+3.5
256
2H
normalizer reference current for XDN
signal
IN2[3:0]
IN1[3:0]
GRF[3:0]
IN2
normalizer reference current for REN
signal
NORM
NORM
10
4
10
2
160
34
µA
µA
IN1
normalizer reference current for FEN
signal
3H
4H
5H
GRF
RF path VGA gain
RF-AMP −4
+0.8
10
+8
dB
mV
µA
DCRF[5:0] DCRF RF path DC offset
RF-AMP
NORM
0
630
6.4
ITW[3:0]
ITR[3:0]
IN4[3:0]
ITW
ITR
IN4
drop-out concealment threshold value
for write mode
0.4
0.4
drop-out concealment threshold value
for read mode
NORM
NORM
0.4
20
0.4
30
6.4
µA
µA
normalizer reference current for TLN
signal
470
9H
AH
BH
CH
DH
BWRF[6:0] f0RF
ORF[5:0] ORF
RF path filter corner frequency
RF path offset correction
RF-AMP 16
1
143
+94
>20
+9
MHz
mV
MHz
dB
RF-AMP −95
+3
−
BWPP[2:0] BWPP push-pull amplifier filter −3 dB frequency PP-AMP
2
GPP[3:0]
IA2[5:0]
Gpp
IA2
push-pull amplifier gain
PP-AMP −3
+0.8
1.5
ALFA measurement reference current
for dye media method 2
ALFA
0
94.5
µA
AN[2:0]
AN
ALFA-dye measurement integrator
capacitor multiplication factor:
AN = 2−AN; see also Chapter 9
ALFA
0.03125
−
1
−
EH
BCTL[2:0] fLPF
BETA circuit −3 dB frequency for CALF BETA
low-pass filter: fLPF = 0.5 × 2BCTL
0.5
−
−
32
kHz
τpeak
BETA circuit peak detector time
constant: τpeak = 500 × 2−BCTL; see also
Chapter 9
BETA
7.81
500
µs
IBS[4:0]
IBS
scaling current for BETA circuit
outputs A1, A2 and CALF
BETA
5
5
160
µA
2002 Jun 06
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Product specification
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TZA1031
ADDR.
PARAM. NAME
PURPOSE
REF.
MIN.
2.5
LSB MAX. UNIT
EH
IAT[1:0]
IAT
drop-out concealment threshold current ALFA
for ALFA signal; dye media
2.5
10
70
10
µA
µA
mV
IAN[1:0]
BCAT[2:0]
IAN
drop-out concealment reference current ALFA
for ALFA signal; dye media
10
40
FH
BCAT threshold level for BCA slicer circuit
BCA
100
590
Table 12 EFMTIM control parameters
ADDR.
PARAM. NAME
PURPOSE
BLOCK
7H
TIM0[4:0]
TIM1[5:0]
TIM2[2:0]
TIM3[2:0]
TIM4[2:0]
TIM5[2:0]
TIM6[2:0]
D1
D2
m1
n1
r/w signal delay parameter for EFMTIM
EFMTIM
EFMTIM
EFMTIM
EFMTIM
EFMTIM
EFMTIM
EFMTIM
LIGHT signal delay parameter for EFMTIM
8H
RS signal rising edge delay parameter for EFMTIM
RS signal falling edge delay parameter for EFMTIM
m2
n2
AINTON signal rising edge delay parameter for EFMTIM
ASTROBE signal rising edge delay parameter for EFMTIM
6H
TIM6 EFMTIM test mode control parameter
8
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
−0.5
MAX.
+5.5
UNIT
VDD
positive supply voltage on pins VDD1
and VDD2
V
V
VSS
Vn
negative supply voltage on pins VSS1, VSS2
and VSSD
−5.5
+0.5
voltage on
pins MON1, MON2 and PPN
note 1
V
SS − 0.5 VDD + 0.5
SS − 0.5 0.5
V
V
pins TS1, TS2, CA1, CA2, CCALF
and RREF
note 1
V
all other pins
note 1
−0.5
V
DD + 0.5
V
V
Vesd
electrostatic discharge voltage on all pins
human body model;
notes 2 and 3
−1500
+1500
machine model; notes 2 −100
+100
V
and 4
Tamb
Tstg
ambient temperature
storage temperature
0
55
°C
°C
−55
+125
Notes
1. The maximum value VDD + 0.5 V must not exceed +5.5 V; the minimum value VSS − 0.5 V must not exceed −5.5 V.
2. The ESD requirements as specified in the general quality specification are not met.
3. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor and with a rise time of 15 ns.
4. Equivalent to discharging a 200 pF capacitor via a 2.5 µH series inductor.
2002 Jun 06
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Product specification
Signal processing IC for DVD rewriteable
TZA1031
9
CHARACTERISTICS
VDD1 = 5 V; VDD2 = 5 V; VSS1 = −5 V; VSS2 = −5 V; VSSD = −5 V; Tamb = 25 °C; CCMPP = 100 nF; CCCALF = 27 nF;
CA1 = 10 nF; CCA2 = 10 nF; CCALF = 10 nF; CA1 = 10 nF; CA2 = 10 nF; RRREF = 47 kΩ; output load on pins RFP
and RFN is 5 pF and 10 kΩ to GND2; for location of external components see Chapter 10; unless otherwise stated.
C
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Write synchronization circuit (EFMTIM)
Ii(EFM)
input current on
0
−
1200
µA
pins EFMDP, EFMDN,
EFMCP and EFMCN
Ii(dif)(H)
Ii(dif)(L)
Ii(dif)(th)
Vi(EFM)
differential input current
for HIGH level
I
I
EFMDP − IEFMDN
EFMCP − IEFMCN
EFMDP − IEFMDN
EFMCP − IEFMCN
EFMDP − IEFMDN
EFMCP − IEFMCN
;
;
;
−
−
−
−
330
−330
0
−
µA
µA
µA
mV
differential input current
for LOW level
I
I
−
differential input current
threshold level
I
I
−
input voltage on
−
120
pins EFMDP, EFMDN,
EFMCP and EFMCN
Ri(EFM)
input resistance on
pins EFMDP, EFMDN,
EFMCP and EFMCN
100
−
−
−
Ω
Ci(EFM)
input capacitance on
pins EFMDP, EFMDN,
EFMCP and EFMCN
−
6
pF
tsu(EFM)
th(EFM)
td1(EFM)
td2(EFM)
set-up time
rising edge
rising edge
ENRW = 1
−
3
−
−
−
−
−
−
3
ns
ns
ns
ns
hold time
−
delay EFMD to r/w
20
4
delay EFMD to RS,
AINTON and ASTROBE
ENRS = 1; r/w = 0;
ENALF = 1;
Ci(EFM) = 6 pF
fEFM
EFM clock frequency
−
−
105
MHz
Normalizer and servo path
Vi(Q)
servo input voltage on
pins Q1 to Q6
Q/NE = 1;
Ii(Q) = 10 µA
−
−
1.3
1.5
−
−
V
V
Q/NE = 0;
I
i(Q) = 10 µA
Ii(Q)
servo input current range Q/NE = 0
0
−
−
−
110
µA
µA
V
on pins Q1 to Q6
Q/NE = 1
−8
+12
Vo(S), Vo(D)
servo output voltage
range on pins S1 to S2
and D1 to D4
−0.5
0.5VDD
Ii(TS)
tilt sensor input (TS1 and
TS2) current range
0
−
40
µA
Vi(TS)
tilt sensor input voltage
−
VSS + 2.6
−
V
2002 Jun 06
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Philips Semiconductors
Product specification
Signal processing IC for DVD rewriteable
TZA1031
SYMBOL
fLPF1
PARAMETER
CONDITIONS
MIN.
TYP.
1.0
MAX.
UNIT
−3 dB frequency of LPF1
in RAD
0.8
48
1.2
72
kHz
fLPF2
−3 dB frequency of LPF2
60
kHz
in CANORM
fTILT
−3 dB frequency of TILTN
40
64
50
80
60
96
kHz
RXDN
conversion resistance in
RAD on pin XDN
kΩ
∆RXDN/RXDN
RXDN variation with die
temperature
Tdie = 20 to 120 °C
−
−
5
%
VCAL
I0
XDN reference voltage
CAN reference current
1.2
9
1.3
10
1.4
11
V
µA
µA
I01
MIRN and CAN reference
current
180
200
220
IS0
TILTN reference current
40
45
50
µA
µA
IPR
read power reference
current
3.15
3.50
3.85
ITT
DOC threshold current for
TILTN
4.5
5
5.5
µA
µA
ICL
TLN clamp current
9
10
11
∆TS/(TS1 + TS2) normalizing error for
TS1 = TS2
−
−
0.05
TILTN
∆I/(I1 + I2)
normalizing error for FEN, I1 = I2
REN and TLN
−
−
−
−
0.03
4
τd
RS switch delay
ns
Normalizer control currents
IN1
FEN normalization control IN1[3:0] = 0000
3.6
4
4.4
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
current
IN1[3:0] = 1111
30.6
1.8
34
37.4
2.2
∆IN1
IN1 current step
∆IN1 = 1
2.0
10
IN2
REN normalization control IN2[3:0] = 0000
9
11
current
IN2[3:0] = 1111
144
9.0
160
10.0
16
176
11.0
17.6
282
17.6
22
∆IN2
IN2 current step
∆IN2 = 1
IN3
XDN normalization control IN3[3:0] = 0000
14.4
230
14.4
18
current
IN3[3:0] = 1111
256
16.0
20
∆IN3
IN3 current step
∆IN3 = 1
IN4
TLN normalization control IN4[3:0] = 0000
current
IN4[3:0] = 1111
423
27
470
30
517
33
∆IN4
IN4 current step
∆IN4 = 1
ITW
drop-out concealment
threshold current for write
ITW[3:0] = 0000
ITW[3:0] = 1111
∆ITW = 1
0.36
5.76
0.36
0.36
5.76
0.4
6.4
0.40
0.4
6.4
0.44
7.04
0.44
0.44
7.04
∆ITW
ITW current step
ITR
drop-out concealment
threshold current for read
ITR[3:0] = 0000
ITR[3:0] = 1111
2002 Jun 06
37
Philips Semiconductors
Product specification
Signal processing IC for DVD rewriteable
TZA1031
SYMBOL
∆ITR
PARAMETER
ITR current step
CONDITIONS
∆ITR = 1
MIN.
0.36
TYP.
0.40
MAX.
0.44
UNIT
µA
µA
µA
µA
µA
µA
µA
OFR
FEN offset current for
read
OFR[3:0] = 0000
OFR[3:0] = 1111
∆OFR = 1
−4.4
3.15
1.35
−4.4
3.15
1.35
−4
−3.6
3.85
1.65
−3.6
3.85
1.65
3.5
1.5
−4
∆OFR
OFR current step
OFW
FEN offset current for
write
OFW[3:0] = 0000
OFW[3:0] = 1111
∆OFW = 1
3.5
1.5
∆OFW
OFW current step
RF amplifier (RF-AMP)
Vi(RF)
input voltage range
(RFP-RFN)
differential
0
−
1
V
V
common mode
0.5VDD
V
V
DD – 0.25
DD + 0.25
----------
2
----------
2
Ii(RF)
Rrf
RF input current
−10
−
0
µA
kΩ
RF V-to-I conversion
resistance
2.12
2.5
2.88
Vref
Rcal
reference voltage for rf-cal
1.2
28
1.3
33
1.45
38
V
I-to-V conversion
resistance for offset
calibration
kΩ
Vcal
ORF
rf-cal output voltage range pin XDN; ZCAL = 0;
RFCAL = 1
Vref
−
V
DD − 1
V
RF offset control voltage
ORF[5:0] = 000000
ORF[5:0] = 111111
∆ORF = 1
−176
144
4.5
−160
160
5.0
−144
176
5.5
mV
mV
mV
∆ORF
RF offset control voltage
step
BWrf-cal
BWbca-rf
BWRF
−3 dB bandwidth of rf-cal filters off
−3 dB bandwidth of bca-rf
1
5
−
−
−
100
−
kHz
MHz
MHz
−3 dB bandwidth of RFP
ENEQ = 0; ENNF = 0 180
−
and RFN
α
τ
α-equalizer parameter
τ-equalizer parameter
k-equalizer parameter
ENEQ = 1
1.125
1.25
1.31
4.0
1.375
1.44
4.8
ENEQ = 1
1.18
3.2
k
ENEQ = 1; KEQ = 0
ENEQ = 1; KEQ = 1
4.8
6.0
7.2
f0(RF)
noise filter and equalizer
corner frequency;
f0 = (16 + BWRF) MHz
BWRF[6:0] = 0000000 13.6
BWRF[6:0] = 1111111 128.7
16
18.4
157.3
MHz
MHz
143
∆f0(RF)
noise filter and equalizer
corner frequency step
size
∆BWRF = 1
0.85
1
1.15
MHz
2002 Jun 06
38
Philips Semiconductors
Product specification
Signal processing IC for DVD rewriteable
TZA1031
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
td(F)
flatness delay RF for
equalizer off
ENEQ = 0; ENNF = 0
−
−
1.6
ns
flatness delay RF for
100 kHz < F < 0.7f0 for
equalizer on (ENEQ = 1
and ENNF = 0)
f0 = 45 MHz
f0 = 72 MHz
f0 = 102 MHz
f0 = 143 MHz
−
−
−
−
−
−
−
−
−
−
−
−
−
0
0.31
0.21
0.14
0.1
1.5
1.5
−
ns
ns
ns
ns
H1 - He
H1 - Hn
equalizer amplitude error 100 kHz < F < f0
noise filter amplitude error 100 kHz < F < f0
dB
dB
mV
mV
mV
DCRF
RF DC-control voltage
DCRF[5:0] = 000000
DCRF[5:0] = 111111 560
630
10
700
11
∆DCRF
RF DC-control voltage
step
∆DCRF = 1
9
Vo(RFREF)
RF output voltage
1
−
2.5
V
reference on pin RFREF
Ri(RFREF)
RFREF input impedance
100
−
−
−
kΩ
∆VCM
offset of (VRFP + VRFN)/2
compared to VRFREF
V
RFP − VRFN = 0;
HA = 0
RFP − VRFN = 0;
−
17
mV
V
−
−
−
−
70
mV
mV
HA = 1
Voffset(RF)
RF output voltage offset
DCRF = 0;GRF = 0 dB;
HA = 0; zero input
signal
100
V
RFP − VRFN
Ro(RF)
RFP and RFN output
impedance
−
−
40
Ω
Vo(dif)(RF)
RF differential output
voltage range (RFP-RFN)
GRF = 0 dB; HA = 0
−1
−
+1
+2
−2
V
G
RF = 0 dB; HA = 1(1) −2
−
V
GRF
RF path VGA gain
HA = 0;
−6
−4
dB
GRF[3:0] = 0000
HA = 0;
6
8
10
dB
GRF[3:0] = 1111
∆GRF
RF path VGA gain step
RF output driver gain
∆GRF = 1
−
1
−
dB
GDRV
HA = 0
−1
0
+1
13
−
dB
HA = 1
11
12
−
dB
SRRF
differential slew rate for
rf-output at maximum
bandwidth
HA = 0; CL < 15 pF
HA = 1; CL < 15 pF
100
300
V/µs
V/µs
−
−
(BWRF[6:0] = 1111111)
PP amplifier (PP-AMP)
Ii(PPN)(p-p)
AC input current range
200
−
−
µA
(peak-to-peak value)
Ii(PPN)
DC input current
−
−
−
−
40
−
µA
V
Vi(PPN)
Vo(PPNO)
input voltage level
output voltage DC level
2.4
0
Ii(PPN) = 0
−
V
2002 Jun 06
39
Philips Semiconductors
Product specification
Signal processing IC for DVD rewriteable
TZA1031
SYMBOL
Ro(PPNO)
PARAMETER
CONDITIONS
MIN.
TYP.
130
MAX.
UNIT
Ω
PPNO output impedance
−
−
RPP
I-to-V conversion
resistance
11.2
100
−
14
16.8
kΩ
SRPP
slew rate at PPNO output BWPP[2] = 1;
CL = 5 pF
−
−
V/µs
Voffset(PPNO)
GPP
offset voltage at PPNO
output
IPPN = 0; Gpp = 0 dB
−
0.2
V
voltage gain
GPP[3:0] = 0000
GPP[3:0] = 1111
∆GPP = 1
−4
8
−3
9
−2
10
0.88
2.4
4.8
9.6
−
dB
dB
∆GPP
voltage gain step size
bandwidth; note 2
0.72
1.6
3.2
6.4
−
0.8
2
dB
BWPP
BWPP[2:0] = 000
BWPP[2:0] = 001
BWPP[2:0] = 010
BWPP[2:0] = 011
BWPP[2:0] = 1XX
MHz
MHz
MHz
MHz
MHz
4
8
12
−
12
−
ALFA (running OPC processing)
Gd
V-to-I conversion for
alfa-dye
ASTROBE = 1
AN[2:0] = 000
AN[2:0] = 001
40
50
60
µA/V
Tpd
peak detector time
constant
−
4620
−
ns
Tpd = 20T
−
2310
1155
578
−
ns
ns
ns
ns
ns
ns
ns
pF
T = T0 × 2−AN, T0 = 231 ns AN[2:0] = 010
−
−
period of input signal
is 10T
AN[2:0] = 011
AN[2:0] = 100
AN[2:0] = 101
AN[2:0] = 110
AN[2:0] = 111
−
−
−
289
−
−
144
−
−
undefined
undefined
50
−
−
−
C0
AN
alfa-dye integrator
reference capacitor
40
60
alfa-dye integrator
AN[2:0] = 000
AN[2:0] = 001
AN[2:0] = 010
AN[2:0] = 011
AN[2:0] = 100
AN[2:0] = 101
AN[2:0] = 110
AN[2:0] = 111
0.9
1
1.1
capacitor multiplication
0.45
0.225
0.113
0.056
0.028
−
0.5
0.55
0.275
0.138
0.069
0.034
−
factor (AN = 2−AN
)
0.25
0.125
0.063
0.031
undefined
undefined
70
−
−
Iref1
Iref2
reference current for CAN
normalization in alfa-dye
63
77
µA
µA
reference current for
9
10
11
normalization in alfa-pc
2002 Jun 06
40
Philips Semiconductors
Product specification
Signal processing IC for DVD rewriteable
TZA1031
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
IAN
IAT
IA2
alfa normalization current IAN[1:0] = 00
IAN[1:0] = 01
9
10
20
30
40
11
22
33
44
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
18
27
36
IAN[1:0] = 10
IAN[1:0] = 11
alfa drop-out concealment IAT[1:0] = 00
2.25
4.5
6.75
9
2.5
5
2.75
5.5
8.25
11
threshold current
IAT[1:0] = 01
IAT[1:0] = 10
IAT[1:0] = 11
7.5
10
0
alfa-dye reference current IA2[5:0] = 000000
IA2[5:0] = 111111
−
−
85
94.5
1.5
104
1.65
∆IA2
∆α/α
alfa-dye reference current ∆IA2 = 1
step size
1.35
variation of ALFA with die ∆T = 40 °C
−
−
3
%
temperature
Io(ALFA)
Ii(LASP)
ALFA output current range Vo(ALFA) = 0 V
LASP control current input r/w = 0
0
5
0
−
−
−
100
100
15
−
µA
µA
µA
V
−
range
r/w = 1
−
Vi(LASP)
Ri(LASP)
LASP input voltage
Ii(LASP) = 100 µA
1.7
1
LASP input impedance
−
kΩ
BETA (write power calibration)
Vo(beta)
A1, A2 and CALF output
VDD = 5 V
0
−
3
V
voltage range
Ro(beta)
A1, A2 and CALF output
impedance
−
−
300
1.15
1.2
5
Ω
VA1/VA2
VA1/VCALF
matching of A1 and A2
input conditions set for 0.85
A1 = A2(3)
1.0
1.0
−
matching of A1 and CALF input conditions set for 0.8
A1 = A2 = CALF(3)
∆Vo(beta)/Vo(beta) variation of A1, A2 and
Tdie = 20 to 120 °C;
∆T = 10 °C;
−
%
CALF with temperature
∆VDD = 5 %
(VA1)0/VCALF
(VA2)0/VCALF
A1/CALF for DC input
A2/CALF for DC input
V
RFP − VRFN = 0.5 V;
DC; ORF[5:0] = 32H
RFP − VRFN = 0.5 V;
DC; ORF[5:0] = 32H
−
−
−
−
2
2
%
%
V
2002 Jun 06
41
Philips Semiconductors
Product specification
Signal processing IC for DVD rewriteable
TZA1031
SYMBOL
PARAMETER
CONDITIONS
MIN.
0.43
TYP.
0.5
MAX.
0.58
UNIT
fLPF
−3 dB frequency of CALF BCTL[2:0] = 000
low-pass filter
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
µs
BCTL[2:0] = 001
0.85
1.7
1
1.15
2.3
BCTL[2:0] = 010
BCTL[2:0] = 011
BCTL[2:0] = 100
BCTL[2:0] = 101
BCTL[2:0] = 110
BCTL[2:0] = 111
2
3.4
4
4.6
6.8
8
9.2
13.6
27.7
−
16
18.4
36.8
−
32
undefined
500
250
125
62.5
31.3
15.6
7.81
undefined
5
τpeak
time constant of
A1 and A2 peak detectors
BCTL[2:0] = 000
BCTL[2:0] = 001
BCTL[2:0] = 010
BCTL[2:0] = 011
BCTL[2:0] = 100
BCTL[2:0] = 101
BCTL[2:0] = 110
BCTL[2:0] = 111
IBS[4:0] = 00000
IBS[4:0] = 11111
∆IBS = 1
425
213
106
53.1
26.6
13.3
6.64
−
575
288
144
71.9
35.9
18.0
8.98
−
µs
µs
µs
µs
µs
µs
µs
Io(BS)
A1, A2 and CALF output
scaling current
4.5
5.5
µA
144
4.5
160
5
176
5.5
µA
∆Io(BS)
A1, A2 and CALF output
scaling current step size
µA
Gbeta
gain from (RFP-RFN) to
CALF, A1 and A2
(Gbeta = 100/(1 + IBS))
IBS[4:0] = 00000
IBS[4:0] = 11111
85
100
115
3.6
2.7
3.125
BCA (burst cutting area read-out)
VOH(BCA)
HIGH-level output voltage BCAEN = 1;
3.0
−
3.3
V
on pin BCA
VDD = 5 V;
Iload = 0.5 mA
VOL(BCA)
Vhys(BCA)
f0(BCA)
LOW-level output voltage BCAEN = 1;
0
−
−
−
0.6
−
V
on pin BCA
Iload = 0.5 mA
BCA comparator
hysteresis
50
300
mV
kHz
corner frequency of BCA
filter
−
Q1
BCA filter parameter
BCA filter parameter
−
−
−
0.54
1.31
−
−
Q2
−
H - Ht
BCA filter amplitude error 50 kHz < f < 500 kHz
1.5
dB
2002 Jun 06
42
Philips Semiconductors
Product specification
Signal processing IC for DVD rewriteable
TZA1031
SYMBOL
BCAT
PARAMETER
CONDITIONS
MIN.
TYP.
100
MAX.
110
UNIT
BCA comparator
threshold
BCAT[2:0] = 000
BCAT[2:0] = 001
BCAT[2:0] = 010
BCAT[2:0] = 011
BCAT[2:0] = 100
BCAT[2:0] = 101
BCAT[2:0] = 110
BCAT[2:0] = 111
90
mV
mV
mV
mV
mV
mV
mV
mV
153
216
279
342
405
468
531
170
240
310
380
450
520
590
187
264
341
418
495
572
649
MON (servo signal monitoring)
Vo(MON)
monitor output voltage
range
IMON < 1.3 mA
20 °C < Tdie < 120 °C
input current = 0
−1.3
64
−
+1.3
96
10
−
V
Ro(MON)(conv)
∆RMON/ RMON
BWMON
monitor output conversion
resistance
80
−
kΩ
%
conversion resistance
variation with temperature
−
monitor circuit −3 dB
bandwidth
100
−
kHz
VOFF(MON)
Ro(MON)
monitor voltage offset
−
−
−
100
mV
output resistance on
120
−
Ω
pins MON1 and MON2
2002 Jun 06
43
Philips Semiconductors
Product specification
Signal processing IC for DVD rewriteable
TZA1031
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Serial bus interface, registers and logic (see Fig 19)
Vi(logic)
logic input voltage
compatibility
2.7
3.3
5.5
V
V
V
VOH(SROUT)
VOL(SROUT)
HIGH-level output voltage TEST = 1;
on pin SROUT
0.8VDD
0
−
−
VDD
ISROUT < 1 mA
LOW-level output voltage TEST = 1;
0.2VDD
on pin SROUT
ISROUT < 1 mA
VIH
HIGH-level input voltage
LOW-level input voltage
2.1
−
−
−
−
−
V
VIL
1.0
150
V
IIH(TEST)
HIGH-level input current
on pin TEST
internal pull-down
resistor of 50 kΩ
−
µA
Ii(n)
input current on
−
−
100
nA
pins SIDA, SICL and SILD
tsu(strt)
tsu(D)
th(D)
set-up time start
set-up time data
hold time data
0
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
ns
ns
ns
ns
ns
ns
ns
ns
20
20
20
20
60
45
20
tclk(H)
tclk(L)
Tclk
clock HIGH time
clock LOW time
clock period
tsu(load)
tload(H)
set-up time load pulse
load pulse HIGH time
see Fig.20
Notes
1. For low values of VRFREF the output range may be limited. The minimum value for VRFP and VRFN is 0.3 V.
2. For input capacitance at pin PPN: 5 pF < Ci < 15 pF.
3. Conditions for A1, A2 and CALF matching: A1 = A2 = Vbeta. Input signal is ‘clipped sinusoidal’ with period (10T)2 − N
flat top/bottom part is (T/2)2 − N with N = 0 to 5, T = 231 ns.
,
2002 Jun 06
44
Philips Semiconductors
Product specification
Signal processing IC for DVD rewriteable
TZA1031
10 APPLICATION INFORMATION
+
5 V
100 nF
V
100 nF
V
DD1
DD2
to wobble ADC
PPNO
PPN
RFP, RFN
RFREF
to/from HDR65
RFP1, RFN1
Q1 to Q6
from DROPPI
XDN
CALF
A2
C
CALF 10 nF
C
A2 10 nF
from tilt sensor
from/to LADIC
TS1, TS2
C
A1 10 nF
LASP
ALFA
A1
to
MACE3
SPIDRE
TZA1031
D1 to D4, S1, S2
MON1, MON2
TIMOUT
monitoring
from HDR65
EFMCP, EFMCN
EFMDP, EMFDN
SIDA, SICL, SILD
C
C
CA2 10 nF (5%)
CA2
CA1
from AWESOME
CA1 10 nF (5%)
C
CCALF 27 nF (5%)
CCALF
GND1
GND2
GNDD
47 kΩ (1%)
RREF
TEST
R
RREF
−
5 V
V
V
V
SSD
SS1
SS2
100 nF
100 nF
100 nF
−
5 V
MGW497
Fig.21 Application diagram.
45
2002 Jun 06
Philips Semiconductors
Product specification
Signal processing IC for DVD rewriteable
TZA1031
11 PACKAGE OUTLINE
LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm
SOT314-2
y
X
A
48
33
Z
49
32
E
e
H
A
E
2
E
A
(A )
3
A
1
w M
p
θ
b
L
p
pin 1 index
L
64
17
detail X
1
16
Z
v
M
A
D
e
w M
b
p
D
B
H
v
M
B
D
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.20 1.45
0.05 1.35
0.27 0.18 10.1 10.1
0.17 0.12 9.9 9.9
12.15 12.15
11.85 11.85
0.75
0.45
1.45 1.45
1.05 1.05
1.60
mm
0.25
0.5
1.0
0.2 0.12 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
99-12-27
00-01-19
SOT314-2
136E10
MS-026
2002 Jun 06
46
Philips Semiconductors
Product specification
Signal processing IC for DVD rewriteable
TZA1031
12 SOLDERING
If wave soldering is used the following conditions must be
observed for optimal results:
12.1 Introduction to soldering surface mount
packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
12.2 Reflow soldering
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
12.4 Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
12.3 Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
2002 Jun 06
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Philips Semiconductors
Product specification
Signal processing IC for DVD rewriteable
TZA1031
12.5 Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE(1)
WAVE
not suitable
REFLOW(2)
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA
suitable
HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, not suitable(3)
HVSON, SMS
suitable
PLCC(4), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
suitable
not recommended(4)(5) suitable
not recommended(6)
suitable
Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
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Product specification
Signal processing IC for DVD rewriteable
TZA1031
13 DATA SHEET STATUS
PRODUCT
DATA SHEET STATUS(1)
STATUS(2)
DEFINITIONS
Objective data
Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Preliminary data
Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
Product data
Production
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change
Notification (CPCN) procedure SNW-SQ-650A.
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
14 DEFINITIONS
15 DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
Application information
Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2002 Jun 06
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Philips Semiconductors
Product specification
Signal processing IC for DVD rewriteable
TZA1031
NOTES
2002 Jun 06
50
Philips Semiconductors
Product specification
Signal processing IC for DVD rewriteable
TZA1031
NOTES
2002 Jun 06
51
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
© Koninklijke Philips Electronics N.V. 2002
SCA74
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753503/01/pp52
Date of release: 2002 Jun 06
Document order number: 9397 750 08641
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