UAA3522 [NXP]
Low power dual-band GSM transceiver with an image rejecting front-end; 用图像拒绝前端低功耗双频GSM收发器型号: | UAA3522 |
厂家: | NXP |
描述: | Low power dual-band GSM transceiver with an image rejecting front-end |
文件: | 总28页 (文件大小:152K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
UAA3522HL
Low power dual-band GSM
transceiver with an image rejecting
front-end
Objective specification
2000 Feb 18
File under Integrated Circuits, IC17
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
UAA3522HL
FEATURES
The input Low Noise Amplifier (LNA) can be switched off
via the bus to allow accurate calibration in the offset
cancellation mode.
• Dual-band application for Global System for Mobile
communication (GSM) and Digital Cellular
communication Systems (DCS)
The transmitter comprises a high precision I/Q modulator
and modulation loop architecture. The I/Q modulator
converts the baseband modulation frequency to the
transmit IF. The modulation loop architecture, which
includes an on-chip offset mixer and phase detector,
controls an external transmit RF VCO which converts the
transmit modulated IF signal to RF.
• Low noise and wide dynamic range single Intermediate
Frequency (IF) transceiver
• More than 30 dB on-chip image rejection in the receiver
• More than 60 dB gain control range
• I/Q demodulator with high performance integrated
baseband channel filter
A receive RF VCO provides the Local Oscillator (LO)
signal to the image rejection mixers in the RF receiver. An
IF VCO provides the LO signal to the I/Q demodulator and
I/Q modulator in the receiver and transmitter sections
respectively.
• High precision I/Q modulator
• Transmit modulation loop architecture including offset
mixer and phase detector
• Dual Phase-Locked Loop (PLL) with on-chip IF Voltage
The frequencies of the RF VCO and the IF VCO are set by
internal PLL circuits, which are programmable via the
3-wire serial bus. The RF and IF PLL comparison
frequencies are 200 kHz and 1 MHz respectively, derived
from a 13 MHz reference signal which has to be supplied
externally. The quadrature RF LO signals required by the
image rejection mixers are obtained using on-chip
Resistor Capacitor (RC) networks. The quadrature IF LO
signals required by the I/Q modulator and I/Q demodulator
are obtained by dividing the frequency of the IF VCO
signal.
Controlled Oscillator (VCO)
• Fully differential design minimizing cross-talk and spurii
• 3-wire serial bus interface
• Functional down to 2.7 V and up to 3.3 V
• LQFP48 package.
APPLICATIONS
• GSM 900 MHz hand-held transceiver
• GSM/DCS dual-band solution with the UAA2077CM
The IC can be powered on in either receiver (RX),
transmitter (TX) or synthesizer (SYN) operating mode
depending on the logic level at pins RXON, TXON and
SYNON, respectively. Alternatively, an operating mode
can be selected by software using the 3-wire serial
programming bus. In RX or TX mode, only those sections
of the IC which are required are switched on.
(down to 3.2 V) or UAA2077TS/D (down to 2.7 V).
GENERAL DESCRIPTION
The UAA3522HL integrates the receiver and most of the
transmitter section of a GSM hand-held transceiver. It also
integrates the receiver IF and the transmitter section of a
DCS transceiver.
The GSM or DCS band is selected by the 3-wire serial
programming bus. When activating RX mode for DCS
applications, the receiver RF section can be disabled by
software so that only the receiver IF section is
powered-on.
The receiver comprises an RF and an IF section. The RF
(GSM) front-end amplifies the aerial signal, converts the
chosen channel frequency to an IF of 200 MHz, and also
provides more than 30 dB of image suppression. Some
selectivity is provided at this stage by an off-chip bandpass
pre-filter. The IF section further amplifies the chosen
channel, maintains the gain at the required level,
demodulates the signal into I and Q components, and
provides channel selectivity at a baseband stage using a
high performance integrated low-pass filter. The IF gain
can be varied over a range of more than 60 dB. The offset
at the I and Q outputs can be cancelled out by software
using the 3-wire serial programming bus.
The SYN mode is used to power-on the synthesizer prior
to activating the RX or TX mode. In SYN mode, some
internal LO buffers are also powered-on to minimize the
‘pulling’ effect of the VCO when either the receiver or the
transmitter are switched on.
2000 Feb 18
2
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
UAA3522HL
QUICK REFERENCE DATA
SYMBOL
PARAMETER
GSM band RF input frequency in RX mode
GSM band RF output frequency in TX mode
DCS band RF output frequency in TX mode
IF frequency in all modes
MIN.
TYP.
MAX.
960
UNIT
MHz
MHz
fi(RF)(RX)
925
−
−
−
fo(RF)(TX)(GSM)
fo(RF)(TX)(DCS)
fIF
880
1710
−
915
1785 MHz
200
−
MHz
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
UAA3522HL
LQFP48
plastic low profile quad flat package; 48 leads; body
SOT313-2
7 × 7 × 1.4 mm
2000 Feb 18
3
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
g
90°
PHASE
SHIFTER
×
1805 to1880 MHz
90°
PHASE
SHIFTER
+
BALUN
ADDER
0°
SAW
×
UAA2077XM
46, 47
8, 9
90°
PHASE
SHIFTER
4, 5
2, 3
I
×
×
925 to 960 MHz
90°
41,
42
0°
IF VCO
400 MHz
PHASE
SHIFTER
BALUN
+
Q
ADDER
B
A
S
E
B
A
N
D
×
0°
90°
×
13,
14
DIVIDER &
PHASE
SHIFTER
÷2
IF VCO
XTAL
UAA3522HL
&
PROGRAMMABLE
DIVIDER
30, 31
A
U
D
I
DCS RF
RX VCO
1510 to 1680
MHz
GSM RF
RX VCO
1080 to 1160
MHz
IF PHASE/
FREQUENCY
DETECTOR
16
23
CHARGE
PUMP
PROGRAMMABLE
DIVIDER
O
I
N
T
E
R
F
A
C
E
RF PHASE/
FREQUENCY
DETECTOR
26
CHARGE
PUMP
DIVIDER
÷5
DIVIDER
÷13
REF OSC.
13 MHz
RX/TX
SWITCH
880 to 915 MHz
GSM BAND
38, 39
×
0°
ADDER
I
4, 5
2, 3
GSM TX RF VCO
880 to 915 MHz
×
90°
PHASE
DETECTOR
+
Q
35
CHARGE
PUMP
×
44, 45
1710 to 1785 MHz
DCS BAND
POWER
AMPLIFIER
DCS TX RF VCO
1710 to 1785 MHz
FCA004
Fig.1 Block diagram.
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
UAA3522HL
PINNING
SYMBOL
PIN
DESCRIPTION
SYMBOL
PIN
DESCRIPTION
VCCCPRF
25
RF charge pump and phase
detector supply voltage
RF charge pump output
RF charge pump ground
SYN mode control pin
VCCIF1
1
IF section of RF receiver supply
voltage 1
CPORF
GNDCP
SYNON
VCCRFLO
RFLOC
RFLOE
26
27
28
29
30
31
32
33
34
QA
2
3
4
5
6
7
Q path A baseband input/output
Q path B baseband input/output
I path A baseband input/output
I path B baseband input/output
AGC reference resistor
QB
IA
RF LO section supply voltage
LO signal input from RF VCO
LO signal input from RF VCO
RF LO section ground
IB
REFAGC
GNDIF2
I/Q modulator and I/Q demodulator
ground 2
GNDRFLO
RXON
RX mode control pin
RXIIFA
RXIIFB
VCCIF2
8
9
RX IF input A to AGC amplifier
RX IF input B to AGC amplifier
GNDPHD
transmit modulation loop charge
pump ground
10
I/Q modulator and I/Q demodulator
supply voltage 2
PHDOUT
VCCPHD
35
36
charge pump output
transmit modulation loop charge
pump supply voltage
TXON
VCCIFLO
IFLOC
11
12
13
TX mode control pin
IF LO supply voltage
RESEXT
37
reference resistor for transmit
modulation loop
IF LO signal input from
IF VCO resonator
TXIRFA
TXIRFB
VCCRF
38
39
40
TX RF VCO signal input
TX RF VCO signal input
IFLOE
14
IF LO signal input from
IF VCO resonator
RF receiver and transmit
GNDIFLO
CPOIF
15
16
17
IF LO ground
modulation loop supply voltage
IF charge pump output
RXIRFA
RXIRFB
GNDRF
41
42
43
RF receiver input A
RF receiver input B
GNDCPIF
IF charge pump and phase
detector ground
RF receiver and transmit
modulation loop ground
VCCCPIF
EN
18
19
IF charge pump and phase
detector supply voltage
TXIFA
44
45
46
47
48
transmit IF external filter A
transmit IF external filter B
receiver IF output A
serial programming bus enable
control pin
TXIFB
RXOIFA
RXOIFB
GNDIF1
DATA
20
21
22
23
24
serial programming bus data input
serial programming bus clock input
synthesizer ground
receiver IF output B
CLK
IF section of RF receiver ground 1
GNDSYN
REFIN
VCCSYN
13 MHz reference input
synthesizer supply voltage
2000 Feb 18
5
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
UAA3522HL
V
V
36
1
2
CCIF1
QA
CCPHD
35 PHDOUT
34 GNDPHD
33 RXON
QB
IA
3
4
IB
5
32 GNDRFLO
31 RFLOE
30 RFLOC
REFAGC
GNDIF2
RXIIFA
RXIIFB
6
UAA3522HL
7
V
29
8
CCRFLO
9
28 SYNON
27 GNDCP
26 CPORF
V
10
CCIF2
TXON 11
V
V
CCPRF
12
25
CCIFLO
FCA043
Fig.2 Pin configuration.
6
2000 Feb 18
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
UAA3522HL
FUNCTIONAL DESCRIPTION
RF receiver
The phase detector output transfers the modulation of the
I/Q IF signal to the off-chip transmit RF VCO making the
analog PLL act as a tracking filter. A PLL of at least
third-order is needed to meet noise requirements at
20 MHz offset from the carrier.
The receiver front-end converts the aerial RF signal, in the
GSM band (925 to 960 MHz), to an IF signal of
approximately 200 MHz. The first stage of the receiver is a
symmetrical LNA that is matched to 50 Ω by an external
balun. The LNA is followed by an image rejection mixer
which suppresses the image by more than 30 dB.
It comprises two mixers in parallel driven by 0° and 90°
quadrature LO signals respectively. The IF signal from
one mixer is shifted by 90° with respect to the IF signal
from the other mixer, then both signals are added together
to cancel out the image signal. The resultant IF signal is
fed to the output via a high output impedance
RF and IF LO sections
The active components required for the design of a low
noise IF VCO are provided on-chip. Pins IFLOC and
IFLOE connect the on-chip IF VCO components to an
external resonator and feedback circuit.
A divider and phase shifter divides the frequency of the
IF VCO signal by 2 and splits it into two signals having
phases of respectively 0° and 90° which are both fed to the
I/Q modulator and to the I/Q demodulator. The IF VCO
frequency is twice the IF to suppress the effects of
self-mixing and parasitic VCO modulation.
open-collector stage which drives an external Surface
Acoustical Wave (SAW) filter which selects the required
channel.
I/Q demodulator
Pins TXIRFA and TXIRFAB connect an external receive
RF VCO module to the on-chip RF LO section. This
section includes a RC phase shifter which splits the
RF VCO signal into two signals having phases of
respectively 0° and 90° which are both fed to the RX
image rejection mixer.
The signal from the SAW filter enters the I/Q demodulator
section. In addition to I/Q demodulation, this section
performs Automatic Gain Control (AGC) over a range of
60 dB to maintain a constant output level irrespective of
the antenna input level, and also applies additional
channel selectivity at the baseband stage using an
integrated high-order low-pass filter.
Dual PLL
An on-chip high performance dual PLL synthesizes the
frequencies of the receive RF VCO and IF VCO signals.
Very low close-in phase noise is achieved which provides
a wide PLL bandwidth with a short settling time.
The AGC amplifier output can be adjusted for a static
offset of less than 50 mV. Its design prevents the offset
from varying by more than ±5 mV. To allow a more
accurate offset calibration, the RF LNA can be switched off
to ensure that no IF signal is present at the AGC amplifier
input during the offset measurement.
A dual programmable divider chain reduces the frequency
of the receive RF and IF LO signals to 200 kHz and 1 MHz
respectively. A digital phase/frequency detector compares
their phases to a reference signal derived from an external
13 MHz clock signal. Phase error information is fed back
to both VCOs via the dual charge pump circuit which
adjusts the phase of each VCO signal by either ‘sinking’
current into, or ‘sourcing’ current from, its loop filter
capacitor, phase locking both RF and IF loops. The very
low leakage current of the dual charge pump circuit
ensures that any spurii are negligible.
I/Q modulator
Baseband I and Q signals are applied to the I/Q modulator
which shifts the modulation spectrum up to the transmit IF.
The I/Q modulator is designed for low harmonic distortion,
low carrier leakage and high image rejection to keep the
phase error as small as possible. Its IF output is loaded by
an integrated low-pass filter and by an external
LC tuned-circuit to prevent unwanted spurii from entering
the phase detector in the transmit modulation loop.
Operating modes
BASIC OPERATING MODES
Transmit modulation loop
The circuit can be powered on in one of four operating
modes in which different parts of the device are enabled or
disabled. The four operating modes are called Idle, RX,
TX and SYN, and are selected by the hardware control
voltage level applied to pins RXON, TXON and SYNON.
The analog transmit modulation loop comprises an on-chip
offset mixer and simple phase detector in switching mode
(triangular transfer function) forming an analog PLL with
an off-chip loop filter and transmit RF VCO.
2000 Feb 18
7
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
UAA3522HL
The synthesizer, receiver and transmitter cannot all be on
at the same time. Table 1 shows which parts of the device
are enabled (on) or disabled (off) in each mode.
Table 2 Bit LNA status
POWER STATUS OF BIT
LNA
BIT LNA STATUS
0
1
off
on
Table 1 Operating modes
POWER STATUS
MODE
SYNTHESIZER RECEIVER TRANSMITTER
Table 3 Bit RF status
Idle
SYN
RX
off
on
on
on
off
off
on
off
off
off
off
on
POWER STATUS OF
RECEIVER RF SECTION
IN RX MODE
BIT RF STATUS
TX
1
0
on (GSM)
off (DCS)
The synthesizer includes the oscillators and LO buffers
common to the receive and transmit sections. The receiver
includes the RF section and the I/Q demodulator. When
the receiver is on, the LNA can be switched off to allow
DC offset compensation to be performed. The RF section
can also be switched off for DCS applications. See Section
“Receiver power status control”.
Programming
SERIAL PROGRAMMING BUS
A simple 3-wire unidirectional serial bus is used for
programming the IC. The lines are called DATA, CLK
and EN (enable). Programming data is sent to the IC in
bursts which are separated from each other by EN.
Programming clock edges are ignored until EN goes
active LOW. The data is loaded into the addressed register
when EN returns inactive HIGH, and when the CLK is in
either state, without affecting the data in the register.
The register only holds the last 18 bits that are serially
clocked into the IC.
RECEIVER POWER STATUS CONTROL
• DC offset compensation: This feature allows the DC
offset of the receiver output to be set accurately. When
the receiver is on, the LNA can be switched off to isolate
the antenna input from the I/Q demodulator input.
The offset at the I and Q outputs can be independently
reduced to less than 50 mV by adequately programming
two 5-bit data registers, see Table 4 “Register bit
allocation”. The LNA is switched on or off by the status
of bit LNA (see Table 2).
Additional leading bits are ignored, and no check is made
on the number of clock pulses received. The fully static
CMOS design uses virtually no current when the bus is
inactive. It can always accept new programming data even
when both synthesizers are powered-off.
• Disabling RF section: For DCS applications, the RF
section can be disabled in RX mode. The same
IF circuits are used for both GSM and DCS applications
to avoid duplication. For DCS applications using the
UAA2077XM, for example, the RF section of the
UAA3522HL does not have to be powered on.
DATA FORMAT
Data is loaded into the register with the most significant bit
(MSB) first. The first 14 bits are data, while the last 4 bits
are the register address. The address bits are decoded on
the rising edge of EN. This internally generates a load
pulse to store the data in the addressed register.
To ensure that data loads correctly after the device has
powered-up, EN should be held LOW and only taken HIGH
after the appropriate register has been loaded.
The RF section is enabled or disabled by the status of
bit RF when the RX mode is activated (see Table 3).
The EN pulse is inhibited during the period when data is
read by the frequency dividers to prevent divider ratio data
from being read incorrectly. This state is guaranteed by
always allowing for a minimum EN pulse width after data
transfer.
2000 Feb 18
8
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
Table 4 Register bit allocation
X = don’t care; MSB = Most Significant Bit; LSB = Least Significant Bit.
DATA BITS
ADDRESS BITS
LAST
FIRST
BIT
BIT
13
12
11
10
9
8
7
6
5
4
3
2
1
0
3
2
1
0
X
MSB
X
X
X
X
X
X
MSB
IF LO frequency divider ratio
LSB
LSB
LSB
0
0
0
1
1
0
1
0
1
0
0
1
RF LO frequency divider ratio
X
X
X
X
X
X
X
LNA(1)
X
MSB
AGC amplifier gain (RX mode)
see Table 5
X
X
MSB Q output offset adjust
LSB
Q sign MSB
I output offset adjust
LSB
I sign(2)
0
0
0
0
0
0
1
0
0
0
1
0
(2)
X
X
X
IF RD IF VCO
(3)
0
0
RF(5)
X
SYN ON RX ON TX ON
(4)
For test purposes only(6)
Notes
1. Bit LNA: 1 = LNA ON in RX mode; 0 = LNA OFF in RX mode.
2. Bits Q sign and I sign = polarity of offset at Q/I channel outputs: 0 = negative offset step (output A with respect to output B); 1 = positive offset step
(output A with respect to output B).
3. Bit IF RD: 0 = frequency dividers programmed for GSM applications; 1 = frequency dividers programmed for DCS applications.
4. Bit IF VCO: 0 = IF LO buffer ON (external IF LO source connected); 1 = IF VCO ON (external IF LO source not connected).
5. Bit RF: 1 = RF section ON when RX mode is activated; 0 = RF section OFF when RX mode is activated.
6. This address must not be used. Data bits to be defined.
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
UAA3522HL
Table 5 AGC amplifier gain register look-up table
All codes not included in the table are forbidden.
AGC AMPLIFIER
GAIN (dB)(1)
BIT 5 (MSB)
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0 (LSB)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
−1
+1
+3
+5
+7
+9
+11
+13
+15
+17
+19
+21
+23
+25
+27
+29
+31
+33
+35
+37
+39
+41
+43
+45
+47
+49
+51
+53
+55
+57
+59
+61
Note
1. Voltage gain is defined as the differential baseband output voltage (either at pins IA/IB or pins QA/QB) divided by the
differential input voltage at pins RXIIFA and RXIIFB.
2000 Feb 18
10
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
UAA3522HL
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
VCCn
PARAMETER
MIN.
TYP. MAX. UNIT
supply voltage
−0.3
−
−
−
−
−
+6
1
V
Ptot
total power dissipation
storage temperature
ambient temperature
W
Tstg
Tamb
−40
−30
+150 °C
+70 °C
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However it is good practice to take
normal precautions appropriate to handling MOS devices (see “Handling MOS devices”).
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
in free air
VALUE
UNIT
Rth(j-a)
thermal resistance from junction to ambient
65
K/W
DC CHARACTERISTICS
All parameters are guaranteed at VCC = 2.8 V; Tamb = 25 °C.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
Supply pins VCCIF1, VCCIF2, VCCIFLO, VCCRFLO, VCCSYN, and VCCRF
VCC
Supply pins VCCCPIF and VCCCPRF
VCCCPIF supply voltage
VCCCPRF
Supply pin VCCPHD
VCCPHD supply voltage for charge pump of
supply voltage
note 1
note 1
2.7
−
−
3.3
4
V
V
;
2.7
2.7
note 1
−
5.5
V
phase detector in transmit
modulation loop
Supply pins VCCIF1, VCCIF2, VCCIFLO, VCCRFLO, VCCSYN, VCCCPIF, VCCCPRF, VCCPHD and VCCRF
ICC(pd)(tot)
total power-down supply current
pins TXON,
−
40
100
µA
RXON, SYNON = LOW-level;
pins EN, DATA, CLK = HIGH-l
evel; note 2
RF receiver IF section (pins VCCIF1, RXOIFA and RXOIFB)
ICC(RFIF)(RX) RF receiver and IF section total
supply current
RX mode active
−
16.9
21.9
mA
IF section supply (pin VCCIF2
)
ICCIF(RX)
ICCIF(TX)
I/Q demodulator supply current
I/Q modulator supply current
RX mode active
TX mode active
−
−
10.1
7.4
14.1
9.6
mA
mA
2000 Feb 18
11
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
UAA3522HL
SYMBOL
IF LO section supply (pin VCCIFLO
ICCIFLO(SYN) IF LO section supply current
IF charge pump supply (pin VCCCPIF
ICCCPIF(SYN) IF LO charge pump supply current
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
)
SYN mode active
−
5.5
1.2
6.6
1.5
mA
mA
)
SYN mode active; phase
locked
−
Synthesizer supply (pin VCCSYN
)
ICCSYN(SYN) synthesizer supply current
SYN mode active
−
−
5
6.7
1.7
mA
mA
RF LO charge pump and phase detector supply (pin VCCCPRF
)
ICCCPRF(SYN) RF LO charge pump supply current SYN mode active; phase
locked
1.4
RF LO supply (pin VCCRFLO
ICCRFLO(RX) RF LO buffer receive section supply SYN mode active; RX mode
current active
)
−
−
8.6
9.8
10.9
12.6
mA
mA
ICCRFLO(TX) RF LO buffer transmit section supply TX mode active
current
Closed-loop charge pump supply (pin VCCPHD
)
ICCPHD(TX)
closed-loop charge pump supply
current
TX mode active; phase locked
−
−
5.6
7.5
mA
mA
RF receiver and transmit modulation loop supply (pin VCCRF
)
ICCRF(RX)on
ICCRF(RX)off
ICCRF(TX)
supply current of RF receiver
(receive IF section disconnected)
with RX image rejection mixer and
LNA ON
RX mode active; LNA ON
RX mode active; LNA OFF
TX mode active
17.9
23.6
supply current of RF receiver
(receive IF section disconnected)
with RX image rejection mixer and
LNA OFF
−
−
11.2
6.1
14.6
7.6
mA
mA
supply current of transmit
modulation loop (charge pump
disconnected)
Pins VCCIF1, VCCIF2, VCCIFLO, VCCCPIF, VCCSYN, VCCCPRF, VCCPHD, VCCRF and RXOIFA, RXOIFB
ICC(RX)
ICC(TX)
ICC(SYN)
supply current in RX mode
supply current in TX mode
supply current in SYN mode
RX mode active; note 3
TX mode active; note 3
SYN mode active; note 3
−
−
−
44.9
20.3
21.7
59.6
26.4
27.4
mA
mA
mA
Pins IA IB, QA and QB
VO(IQ)
VI(IQ)
DC voltage at I/Q baseband outputs TX mode active
1.125 1.25
1.175 1.25
1.325
1.35
V
V
DC voltage at I/Q baseband inputs
RX mode active
Logic levels (pins EN, DATA, CLK, TXON, RXON and SYNON)
VIH
VIL
HIGH-level input voltage
LOW-level input voltage
1.9
−
−
−
V
V
−
0.7
2000 Feb 18
12
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
UAA3522HL
Notes:
1. VCCCPRF, VCCCPIF and VCCPHD must be equal to, or greater than, the other supply voltages. The other supply
voltages must be equal.
2. ‘HIGH-level’ means the control pin voltage must be equal to the supply voltage VCC. ‘LOW-level’ means the control
pin voltage must be equal to the supply ground.
3. ICC(RX) = ICC(RFIF)(RX) + ICCIF(RX) + ICCRF(RX); CC(TX) = ICCIF(TX) + [ICCRFLO(TX) − ICCRFLO(RX)] + ICCPHD(TX) + ICCRF(TX);
I
ICC(SYN) = ICCIFLO(SYN) + ICCCPIF(SYN) + ICCPLL(SYN) + ICCCPRF(SYN) + ICCRFLO(SYN)
.
AC CHARACTERISTICS
All parameters are guaranteed at VCC = 2.8 V; Tamb = 25 °C; unless specified otherwise.
SYMBOL PARAMETER CONDITIONS MIN. TYP.
MAX.
UNIT
RF receiver section; measured in a 50 Ω impedance system, including external input/output baluns and
matching networks to 50 Ω (see Fig.3)
RF RECEIVER INPUTS (PINS RXIRFA AND RXIRFB)
fi(RF)(GSM)
GSM band RF input
frequency
925
−
−
960
−
MHz
Ri(dif)
differential input
resistance
146
0.85
Ω
Ci(dif)
differential input
capacitance
−
−
pF
S11
input power matching
note 1
−
−
−15 −10
−50 −40
dB
Pi(spur)
level of spurious input
power due to
dBm
LO leakage
RECEIVER IF OUTPUT (PINS RXOIFA AND RXOIFB)
fo(IF)
IF output frequency
LO > RF
−
−
200
1
−
−
MHz
RL(m)
matched load
resistance
differential; note 2
kΩ
Gconv(p)
Gripple
power conversion gain into specified matched load
resistance; note 1
23
24.5 27
dB
dB
gain ripple
over specified frequency range;
note 3
−0.5
−
+0.5
∆G/∆T
gain variation
with temperature
noise figure
note 6
−60
−30
−
dBm/K
dB
F
for Ri(dif); notes 1, 3 and 4
note 1
−
3.45 3.85
CP1
−1 dB input
compression point
referenced to input
at Tamb = 25 °C
over temperature range
note 1
−23.5
−24.2
−18
−
−
−
−
−
−
dBm
dBm
dBm
IP3
third-order intercept
point referenced to
input
DES3dB
3 dB desensitization
point referenced to
input
∆fi(RF) = 3 MHz RF input power =
−101 dBm; note 1
−25
−
−
dBm
2000 Feb 18
13
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
UAA3522HL
SYMBOL
PARAMETER
image rejection
CONDITIONS
fo(IF) = 200 MHz; note 1
bit LNA = 0; notes 1 and 5
MIN. TYP.
MAX.
UNIT
dB
dB
IR
Goff
30
60
35
70
−
−
output isolation in
off-state
Receiver IF section (AGC and baseband filter); the impedance of the source, input balun, matching network
and specified input is 50 Ω
IF INPUT TO AGC AMPLIFIER (PINS RXIIFA AND RXIIFB)
fi(IF)
IF input frequency
−
−
200
1
−
−
MHz
Ri(dif)
differential input
resistance
kΩ
Pi(m)
input power matching
note 1
−
−15 −10
dB
dB
BASEBAND INPUT/OUTPUT; RX MODE (PINS IA, IB, QA AND QB)
Gconv(dif)(min)
differential voltage
conversion gain per
channel; gain set to
minimum
notes 1 and 7
−2.5 −0.5 +1.5
Gconv(dif)(max)
differential voltage
conversion gain per
channel; gain set to
maximum
59.5 61.5 63.5
dB
Gconv(step)
∆GI-Q
∆ϕ
voltage conversion step note 1
gain
−
2
−
−
−
dB
gain difference
note 1
−
0.8
+5
dB
between I and Q paths
quadrature-phase error
between I and Q paths
−5
deg
GL
gain control linearity
noise figure
note 1
−2
−3
−1
−
−
+2
+3
+1
9
dB
notes 1 and 11
within any 20 dB gain range
−
dB
−
dB
F
G
conv(dif)(max); notes 1 and 9
conv(dif)(min); notes 1 and 9
−
dB
G
−
−
61
−
dB
IP3
third-order intercept
point referenced to
input
Gconv(dif)(max) = 61 dB; note 8
−42
−38
dBm
CP1
−1 dB compression
point referenced to
input
G
conv(dif)(min); note 8
−4
0
−
−
dBm
dBm
CP1adjacent
−1 dB compression
point for adjacent
channels referenced to
input
Gconv = 49 dB; notes 7 and 6
∆fmod = n × 200 kHz; n = 1, 2, 3
−45
−40
Bbf(-1dB)
−1 dB baseband filter
bandwidth
note 10
67.7
−
−
−
kHz
∆td(g)
group delay variation
DC < ∆fmod < 67.7 kHz
−
1.5
µS
2000 Feb 18
14
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
UAA3522HL
SYMBOL
αbf5
PARAMETER
baseband filter
attenuation
(fifth-order Butterworth)
CONDITIONS
MIN. TYP.
MAX.
UNIT
note 10;
∆fmod = 140 kHz
8
11
25
55
−
−
−
−
−
−
dB
∆fmod = 200 kHz
∆fmod = 400 kHz
∆fmod = 600 kHz
19
dB
dB
dB
V
36
44
Vo(pin)(peak)(max) maximum peak output differential resistance between
0.75
−
voltage per pin giving a QA/QB or IA/IB > = 180 kΩ; note 1
total harmonic
distortion of less
than 3% at Gconv >7
VOO
output offset voltage
adjustment
Gconv = 31 dB
−60
−
+60
mV
LSBoffset
LSB offset adjustment
offset variation
−
50
100
+10
mV
mV
∆Voffset
gain from Gconv(dif)(min)
to Gconv(dif)(max)
−10
−
Transmit IF section; general conditions: Vmod(peak) = 0.25 V; VI(IQ) = VO(IQ) = 1.25 V; fmod = 67.7 kHz
BASEBAND INPUT/OUT; TX MODE (PINS IA, IB, QA AND QB)
∆fmod
modulation frequency
gain = −3 dB gain
0
−
2
MHz
V
Vmod(peak)
modulation level (peak single-ended
value)
0.225 0.25 0.275
DRi
dynamic input
resistance
single-ended per pin
−
12.5
−
−
kΩ
TRANSMITTER IF LC TUNED CIRCUIT (PINS TXIFA AND TXIFB)
fo(IF)
IF output frequency
−
−
200
MHz
dBc
LOout
local oscillator
fo(IF) = 200 MHz
−40 −30
feedthrough level
Po
transmit power without fo(IF) = 200 MHz
−
−16
−
dBm
LC tuned circuit
± 67.7 kHz; measured through a
balun; note 12
IM2o
IM3o
IMo
level of second-order
image products
fo(IF) = 200 MHz
± 2 × 67.7 kHz; note 12
−
−
−
−48 −45
−55 −50
dBc
dBc
dBc
level of third-order
image products
fo(IF) = 200 MHz
± 3 × 67.7 kHz; note 12
image level
fo(IF) = 200 MHz
−34
−
− 67.7 kHz; note 12
ϕN
phase noise output
power density
foffset = 400 kHz
−
−
−
−125
dBc/Hz
dBc/Hz
foffset = 10 MHz
−140 −133
Transmit modulation loop section; General conditions: Vmod(peak) = 0.25 V; VI(IQ) = VO(IQ) = 1.25 V;
fmod = 67.7 kHz
OFFSET MIXER; GSM BAND (PINS TXIRFA AND TXIRFB)
fi(RF)(TX)
TX RF VCO input
frequency
880
−
915
MHz
2000 Feb 18
15
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
UAA3522HL
SYMBOL
Ri(pin)
Ci(pin)
PARAMETER
CONDITIONS
MIN. TYP.
MAX.
UNIT
input resistance per pin note 13
−
100
1
−
−
Ω
input capacitance per
pin
−
pF
Pi
input power
symmetrical
single-ended
note 1
−14.5 −10 −5.5
−11.5 −7 −2.5
−15 −10
dBm
dBm
dB
S11
input power matching
−
−
LOL
reverse isolation local
oscillator leakage
−
−40
dBm
OFFSET MIXER; DCS BAND (PINS TXIRFA AND TXIRFB)
fi(RF)(TX)
TX RF VCO input
frequency
1710
−
1785
MHz
Ri(pin)
Ci(pin)
input resistance per pin note 13
−
−
100
1
−
−
Ω
input capacitance per
pin
pF
Pi
input power
symmetrical
−14.5 −10 −5.5
−11.5 −7 −2.5
−15 −10
dBm
dBm
dB
single-ended
note 1
S11
input power matching
−
−
LOL
reverse isolation local
oscillator leakage
−
−40
dBm
PHASE DETECTOR; DCS AND GSM BAND (PIN PHDOUT)
Icp(max)
charge pump maximum R = 270 Ω, 1%; VO = 1⁄2VCCPHD
2.2
2.4
2.6
mA
sink or source current
GPHD
phase detector gain
−
2
−
mA/rad
%
∆GPHD
phase detector gain
variation
VO = 1⁄2VCCPHD; note 11
−20
−
+20
VO
Ro
No
output voltage
0.5
−
−
V
CCPHD − 0.5 V
output resistance
VO = 1⁄2VCCPHD
10
−
−
kΩ
output noise current
density
20 kHz < foffset < 20 MHz in lock;
note 1
−
200
pA/√Hz
Isweep
Ro(off)
VCO sweeping source VO = 1⁄2VCCPHD
current
0.4
0.55 0.7
mA
output resistance to
ground when powered
down
TX mode disabled
−
1
−
−
−
kΩ
SPUR4fm
SPUR8fm
level of spurious signal fmod = 67.7 kHz;
−
−
−48
−55
dBc
dBc
at four times the
fo(RF)(GSM) = 880 MHz
wanted fmod signal
to 915 MHz; fo(RF)(DCS) = 1710 MHz
to 1785 MHz
level of spurious signal
at eight times the
wanted fmod signal
LOout
IMo
local oscillator
feedthrough level
at fRF
−
−
−40 −32
−38 −35
dBc
dBc
image level
at fRF; note 1
2000 Feb 18
16
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
UAA3522HL
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP.
MAX.
UNIT
RF LO buffer; measured and guaranteed on evaluation board
RF LO SOURCE CONNECTED TO PIN RFLOE (see Fig.7)
Ri
input resistance
−
50
1
−
−
Ω
Ci
input capacitance
input power matching
−
pF
S11
Pi(LO)
−
−15 −10
dB
input power acceptable
from the RF LO source
−7
−3
2
dBm
IF LO; measured and guaranteed on evaluation board
EXTERNAL RESONATOR CIRCUIT CONNECTED TO PINS IFLOC AND IFLOE
fosc
oscillation frequency
note 1
−
400
−
MHz
V
Vosc(peak)
peak voltage excursion VCCIFLO = 2.8 V; see Fig.5
1
−
1.5
limit at IFLOC
(collector)
ϕN
phase noise
foffset = 400 kHz; fLO(IF) = 400 MHz
−
−
−
−
−125
dBc/Hz
MHz/V
∆fTROFF
frequency variation with note 14
supply voltage
1
(pushing)
∆fTRON
frequency variation
between RX on and
RX off (pulling)
−
−
10
kHz
IF LO buffer; measured and guaranteed on evaluation board
IF SOURCE CONNECTED TO PIN IFLOE
Ri
input resistance
−
50
1
−
−
Ω
Ci
input capacitance
input power matching
−
pF
Pi(m)
PIF
−
−15 −10
dB
dBm
power available from
the IF source
see Fig.5
−8
−5
−2
RF and IF synthesizer VCOs
REFERENCE FREQUENCY INPUT (PIN REFIN)
fref
reference frequency
−
13
−
MHz
mV
Vi(fref)(rms)
input voltage level
(RMS value)
80
−
250
Ri
Ci
input resistance
fref = 13 MHz
−
−
10
1
−
−
kΩ
input capacitance
pF
RF SYNTHESIZER; GSM AND DCS MODES (PINS RXIRFA, RXIRFB AND CPORF)
fLO(RF)
RF LO frequency
1040
−
1720
MHz
kHz
fph(comp)
phase comparator
frequency
−
200
−
ϕN(GSM)
GSM close-in phase
noise
within the closed-loop bandwidth
Pxtal = 0 dBm; fLO(RF) = 1.1 GHz
−
−82 −75
dBc/Hz
2000 Feb 18
17
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
UAA3522HL
SYMBOL
ϕN(DCS)
PARAMETER
CONDITIONS
MIN. TYP.
MAX.
UNIT
DCS close-in phase
noise
within the closed-loop bandwidth
Pxtal = 0 dBm; fLO(RF) = 1.6 GHz
−
−79 −74
dBc/Hz
Vfph(comp)(spur) phase comparator
frequency spurii
foffset = 200 kHz; second-order loop
filter closed-loop
−
−75 −60
dBc
breakthrough level
bandwidth = 11 kHz
Io(cp)
charge pump output
current
sink or source current; at Vo(cp)
1.8
−5
2.2
−
2.6
+5
mA
nA
V
IL(cp)(off)
Vo(cp)
charge pump leakage
current in off-state
charge pump output
voltage
Io(cp) within specified values
0.4
−
VCC − 0.4
IF SYNTHESIZER (PINS IFLOC, IFLOE AND CPOIF)
fLO(IF)
IF LO frequency
380
400 440
MHz
MHz
fph(comp)
phase comparator
frequency
−
1
−
ϕN
close-in phase noise
within the closed-loop bandwidth
Pxtal = 0 dBm; fLO(IF) = 400 MHz
−
−
−95 −85
−75 −60
dBc/Hz
dBc
Vfph(comp)(spur) phase comparator
frequency spurii
foffset = 1 MHz; second order loop
filter closed-loop
breakthrough level
bandwidth = 25 kHz
Io(cp)
charge pump output
current
sink or source current; at Vo(cp)
0.75 1.1
1.35
+5
mA
nA
V
IL(cp)(off)
Vo(cp)
charge pump leakage
current in off-state
−5
−
−
charge pump output
voltage
0.4
VCC − 0.4
Frequency dividers
D/DfLO(RF) RF frequency
5200
−
8600
programmable divider
ratio
D/DfLO(IF)
IF frequency
programmable divider
ratio
−
200
−
D/Dfref(RF)
D/Dfref(IF)
RF reference frequency fixed ratio
divider ratio
−
−
65
13
−
−
IF reference frequency
divider ratio
General IC specification
tON
switch-on time
90% of the final current
−
−
10
µs
2000 Feb 18
18
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
UAA3522HL
Notes
1. Measured and guaranteed only on UAA3522 evaluation board.
2. The IF output has open collectors which are supplied via external inductors. External resistors are also needed to
set the output impedance and to match the IF output to the specified load resistance RL (see Fig.3).
3. Value includes losses due to the printed circuit board and balun.
4. Value is guaranteed only for the Pi(LO) typ.
5. For a given RF input power, the value is the difference in the power measured at the IF output when the LNA is
switched on and when it is switched off.
6. This value is guaranteed within the temperature range −10 to +70 °C.
7. Voltage gain is defined as the differential baseband output voltage (either at pins IA/IB or pins QA/QB) divided by the
differential input voltage at pins RXIIFA and RXIIFB.
8. Value refers to differential voltage at pins RXIIFA and RXIIFB (1 kΩ input impedance).
9. Value includes printed circuit board and balun losses.
10. RREFAGC = 18 kΩ, 1%.
11. Guaranteed at Tamb = −30 to +70 °C.
12. With specified LC tuned circuit (33 nH, 15 pF) connected as shown in Fig.4.
13. Defined for the typical input power.
14. Oscillator configured as shown in the evaluation board diagram Fig.7.
V
CC
50 Ω
RXIRFA
RXIRFB
LOW
LOSS
BALUN
RXOIFA
BALUN
1 kΩ/50 Ω
RF
RECEIVER
R
L
Z = 1 kΩ
50 Ω
RXOIFB
input port
output port
FCA047
Fig.3 RF receiver test principle.
2000 Feb 18
19
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
UAA3522HL
V
CC
EXTERNAL
IF FILTER
15 pF
33 nH
330 Ω
330 Ω
TXIFA
TXIFB
2 kΩ
FCA045
Fig.4 I/Q modulator output.
V
CCIFLO
V
CC
1 kΩ
UAA3522HL
IFLOC
IFLOE
IF VCO
XTAL
IF SOURCE
GNDIFLO
FCA048
Fig.5 Evaluating IF LO buffer.
20
2000 Feb 18
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
UAA3522HL
SERIAL TIMING CHARACTERISTICS
General conditions: VCC = 2.8 V; Tamb = 25 °C; see Fig.6; unless otherwise specified.
SYMBOL
PARAMETER
MIN.
TYP. MAX. UNIT
Serial programming clock (pin CLK)
tr
rise time
−
10
10
−
40
40
−
ns
ns
ns
tf
fall time
−
Tcy(clk)
clock cycle time
100
Enable programming (pin EN)
td(ENL-CLKH)
td(CLKL-ENH)
tW(reg)(min)
delay from enable active to rising clock edge
40
−
−
−
−
−
−
ns
ns
ns
delay from enable inactive to last falling clock edge
20
minimum inactive pulse width when consecutively programming
two different registers
150
tW(IFLO)(min)
tW(RFLO)(min)
tsu(ENH-CLKH)
minimum inactive pulse width when consecutively programming
two IF divider ratios
150
500
20
−
−
−
−
−
−
ns
ns
ns
minimum inactive pulse width when consecutively programming
two RF divider ratios
enable set-up time to next rising clock edge
Register serial input data (pin DATA)
tsu(DATA-CLK)
th(DATA-CLK)
set-up time DATA to CLK
hold time DATA to CLK
20
20
−
−
−
−
ns
ns
t
t
d(CLKL-ENH)
t
t
su(DATA-CLK)
h(DATA-CLK)
t
t
r
f
T
su(ENH-CLKH
)
cy(CLK)
CLK
DATA
EN
MSB
LSB
ADDRESS
INACTIVE
ACTIVE
t
FCA042
W
t
d(ENL-CLKH)
Fig.6 Serial bus timing diagram.
21
2000 Feb 18
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
g
RX RF
V
CC
100
2.2 pF
12 nH
RX IF
27 pF
18 pF
nH
27 pF
22 nH
27 pF
150 nH
3.9 pF
3.9 pF
ATTENUATOR
150 nH
10 pF
V
CC
18 pF
10 pF
47 nH
100 nH
12 nH
1.5 kΩ
V
270 Ω
TX RF
VCO
CC
12 pF
46 45 44 43 42 41 40
39 38 37
36
48 47
1
V
V
CC
CC
220 Ω
QA
2
35
34
33
32
31
30
29
28
27
26
25
1.8 nF
100 pF
QB
IA
3
18 Ω
RXON
4
27 nF
IB
5
22 pF
18 kΩ
6
UAA3522HL
3.9 pF
7
120 pF
470 nH
22 pF
CC
RXIIFA
RXIIFB
8
150 nH
3.9 pF
V
RX RF
VCO
RX IF
SYNON
9
10
11
12
V
CC
120 pF
150 nH
TXON
1 nF
3.3
kΩ
V
V
CC
CC
15 16 17 18 19 20 21
22 23 24
13 14
12 nF
V
(chip)
V
(board)
CC
CC
V
V
CC
CC
13 MHz
SERIAL
8.2 pF
BB149
27
pF
100
pF
1
nF
1 nF
200 mV
33 pF
22 nH
330 Ω
10 kΩ
10 kΩ
39 pF
3.3
kΩ
SERIAL
PROGRAMMING
BUS LINES
(chip)
PROGRAMMING
BUS LINES
(board)
470
pF
SERIAL
PROGRAMMING
BUS LINES
6.8
nF
100 pF
100 pF
FCA044
This schematic represents the UAA3522HL characterisation board for GSM application and does not guarantee full specification for any particular application.
Fig.7 Evaluation board.
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
ahdnbok,uflapegwidt
90°
PHASE
SHIFTER
×
1805 to1880 MHz
90°
PHASE
SHIFTER
+
BALUN
ADDER
0°
SAW
×
UAA2077XM
46, 47
8, 9
90°
PHASE
SHIFTER
4, 5
2, 3
I
×
×
925 to 960 MHz
90°
41,
42
0°
IF VCO
400 MHz
PHASE
SHIFTER
BALUN
+
Q
ADDER
B
A
S
E
B
A
N
D
×
0°
90°
×
13,
14
DIVIDER &
PHASE
SHIFTER
÷
2
IF VCO
XTAL
UAA3522HL
&
PROGRAMMABLE
DIVIDER
30, 31
A
U
D
I
DCS RF
RX VCO
1510 to 1680
MHz
GSM RF
RX VCO
1080 to 1160
MHz
IF PHASE/
FREQUENCY
DETECTOR
16
23
CHARGE
PUMP
PROGRAMMABLE
DIVIDER
O
I
N
T
E
R
F
A
C
E
RF PHASE/
FREQUENCY
DETECTOR
26
CHARGE
PUMP
DIVIDER
DIVIDER
÷13
÷
5
REF OSC.
13 MHz
RX/TX
SWITCH
880 to 915 MHz
GSM BAND
38, 39
×
0°
ADDER
I
4, 5
2, 3
GSM TX RF VCO
880 to 915 MHz
×
90°
PHASE
DETECTOR
+
Q
35
CHARGE
PUMP
×
44, 45
1710 to 1785 MHz
DCS BAND
POWER
AMPLIFIER
DCS TX RF VCO
1710 to 1785 MHz
FCA004
Fig.8 Typical application block diagram of a GSM dual-band solution using the UAA2077XM DCS front-end and the UAA3522HL transceiver.
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
UAA3522HL
PACKAGE OUTLINE
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
c
y
X
36
25
A
E
37
24
Z
E
e
H
E
A
2
A
(A )
3
A
1
w M
p
θ
pin 1 index
b
L
p
L
13
48
detail X
1
12
Z
v M
D
A
e
w M
b
p
D
B
H
v
M
B
D
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.20 1.45
0.05 1.35
0.27 0.18 7.1
0.17 0.12 6.9
7.1
6.9
9.15 9.15
8.85 8.85
0.75
0.45
0.95 0.95
0.55 0.55
1.60
mm
0.25
0.5
1.0
0.2 0.12 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
99-12-27
00-01-19
SOT313-2
136E05
MS-026
2000 Feb 18
24
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
UAA3522HL
SOLDERING
The footprint must incorporate solder thieves at the
downstream end.
Introduction to soldering surface mount packages
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
2000 Feb 18
25
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
UAA3522HL
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
BGA, LFBGA, SQFP, TFBGA
WAVE
not suitable
REFLOW(1)
suitable
suitable
suitable
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS
PLCC(3), SO, SOJ
not suitable(2)
suitable
LQFP, QFP, TQFP
not recommended(3)(4) suitable
not recommended(5)
suitable
SSOP, TSSOP, VSO
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
2000 Feb 18
26
Philips Semiconductors
Objective specification
Low power dual-band GSM transceiver
with an image rejecting front-end
UAA3522HL
NOTES
2000 Feb 18
27
Philips Semiconductors – a worldwide company
Argentina: see South America
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,
Tel. +61 2 9704 8141, Fax. +61 2 9704 8139
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210
Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773
Pakistan: see Singapore
Belgium: see The Netherlands
Brazil: see South America
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 68 9211, Fax. +359 2 68 9102
Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
Tel. +48 22 5710 000, Fax. +48 22 5710 001
Portugal: see Spain
Romania: see Italy
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. +852 2319 7888, Fax. +852 2319 7700
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Colombia: see South America
Czech Republic: see Austria
Tel. +65 350 2538, Fax. +65 251 6500
Slovakia: see Austria
Slovenia: see Italy
Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,
Tel. +45 33 29 3333, Fax. +45 33 29 3905
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. +27 11 471 5401, Fax. +27 11 471 5398
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
Tel. +358 9 615 800, Fax. +358 9 6158 0920
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,
Tel. +33 1 4099 6161, Fax. +33 1 4099 6427
South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 821 2382
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 2353 60, Fax. +49 40 2353 6300
Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 93 301 6312, Fax. +34 93 301 4107
Hungary: see Austria
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745
India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263
Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813
Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),
Tel. +39 039 203 6838, Fax +39 039 203 6800
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Uruguay: see South America
Vietnam: see Singapore
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Middle East: see Italy
Tel. +381 11 3341 299, Fax.+381 11 3342 553
For all other countries apply to: Philips Semiconductors,
Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
69
SCA
© Philips Electronics N.V. 2000
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
403506/01/pp28
Date of release: 2000 Feb 18
Document order number: 9397 750 06451
相关型号:
UAA3545HL/C1,118
IC TELECOM, CORDLESS, RF AND BASEBAND CIRCUIT, PQFP32, 5 X 5 X 1.40 MM, PLASTIC, LQFP-32, Cordless Telephone IC
NXP
©2020 ICPDF网 联系我们和版权申明