EFC2J004NUZTDG [ONSEMI]
Dual N-Channel Power MOSFET for 1-Cell Lithium-ion Battery Protection, 12 V, 14 A, 7.1 mΩ;
| 型号： | EFC2J004NUZTDG |
| 厂家： | 
ONSEMI |
| 描述： | Dual N-Channel Power MOSFET for 1-Cell Lithium-ion Battery Protection, 12 V, 14 A, 7.1 mΩ 电池 |
| 文件： | 总8页 (文件大小：190K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
www.onsemi.com
MOSFET – Power, Dual,
N-Channel, for 1-Cell
Lithium-ion Battery
Protection
V
R
Max
I Max
SSS
SS(on)
S
7.1 mꢁ @ 4.5 V
7.7 mꢁ @ 3.8 V
9.5 mꢁ @ 3.1 V
12.4 mꢁ @ 2.5 V
12 V
14 A
12 V, 7.1 mW, 14 A
ELECTRICAL CONNECTION
N-Channel
EFC2J004NUZ
This Power MOSFET features a low on−state resistance. This
device is suitable for applications such as power switches of portable
machines. Best suited for 1−cell lithium−ion battery applications.
4, 6
5
Features
• 2.5 V Drive
1: Source1
2: Gate1
3: Source1
4: Source 2
5: Gate2
• 2 kV ESD HBM
2
• Common-Drain Type
• ESD Diode-Protected Gate
• Pb−Free, Halide Free and RoHS Compliant
6: Source2
1, 3
Applications
• 1-Cell Lithium-ion Battery Charging and Discharging Switch
MARKING
DIAGRAM
Specifications
NA
AYWZZ
G
ABSOLUTE MAXIMUM RATINGS (T = 25°C)
A
WLCSP6,
2.11x1.18x0.10
CASE 567NP
Parameter
Source to Source Voltage
Gate to Source Voltage
Source Current (DC)
Symbol
Value
12
Unit
V
V
SSS
GSS
NA = Device Code
V
8
V
A
Y
= Assembly Location
= Year
I
S
14
A
W
= Work Week
Source Current (Pulse)
PW ≤ 100 ꢀ s, duty cycle ≤ 1%
I
SP
60
A
ZZ = Assembly Lot Number
G
= Pb−Free Package
Total Dissipation (Note 1)
Junction Temperature
Storage Temperature
P
1.5
150
W
°C
°C
T
T
j
PIN CONNECTIONS
T
stg
−55 to +150
1: Source1
2: Gate1
3: Source1
4: Source 2
5: Gate2
1
6
2
3
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL RESISTANCE RATINGS
6: Source2
5
4
Parameter
Symbol
Value
Unit
Junction to Ambient (Note 1)
R
83
°C/W
θ
JA
ORDERING INFORMATION
See detailed ordering and shipping information on page 6 of
this data sheet.
2
1. Surface mounted on ceramic substrate (5000 mm × 0.8 mm).
© Semiconductor Components Industries, LLC, 2022
1
Publication Order Number:
October, 2022 − Rev. 2
EFC2J004NUZ/D
EFC2J004NUZ
ELECTRICAL CHARACTERISTICS (T = 25°C) (Note 2)
A
Parameter
Symbol
Conditions
I = 1 mA, V = 0 V (Figure 1)
Min
12
−
Typ
−
Max
−
Unit
V
Source to Source Breakdown Voltage
Zero-Gate Voltage Source Current
Gate to Source Leakage Current
Gate Threshold Voltage
V
(BR)SSS
S
GS
I
V
= 10 V, V = 0 V (Figure 1)
−
1
ꢀ A
ꢀ A
V
SSS
GSS
SS
GS
SS
GS
I
V
V
=
8 V, V = 0 V (Figure 2)
−
−
1
SS
V
R
(th)
= 6 V, I = 1 mA (Figure 3)
0.4
3.7
4.1
4.6
5.8
−
−
1.3
7.1
7.7
9.5
12.4
−
GS
S
Static Source to Source On-State
Resistance (Note 2)
(on)
I = 5 A, V = 4.5 V (Figure 4)
5.4
5.9
6.7
8.4
15
35
100
75
36
mꢁ
mꢁ
mꢁ
mꢁ
SS
S
GS
I = 5 A, V = 3.8 V (Figure 4)
S
GS
I = 5 A, V = 3.1 V (Figure 4)
S
GS
I = 5 A, V = 2.5 V (Figure 4)
S
GS
Turn-ON Delay Time
Rise Time
t (on)
d
V
= 5 V, V = 3.8 V, I = 5 A,
ꢀ
s
SS
g
GS
S
R = 10 k
ꢁ
(Figure 5)
t
r
−
−
ꢀ s
ꢀ s
ꢀ s
nC
Turn-OFF Delay Time
Fall Time
t (off)
d
−
−
t
f
−
−
Total Gate Charge
Qg
V
SS
= 6 V, V = 4.5 V, I = 14 A
−
−
GS
S
(Figure 6)
Forward Source to Source Voltage
V
F(S-S)
I = 3 A, V = 0 V
(Figure 7)
−
0.76
−
V
S
GS
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Mounted on onsemi board.
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2
EFC2J004NUZ
Test Circuits are Example of Measuring FET1 Side
/ I
V
I
(BR)SSS SSS
GSS
S2
S2
S1
G2
G1
G2
A
G1
A
V
SS
When FET1 is measured,
Gate and Source of FET2
are short−circuited.
V
GS
S1
Figure 1. Test Circuit 1
Figure 2. Test Circuit 2
V
GS
(th)
R
(on)
SS
IS
S2
S1
S2
S1
G2
G1
G2
G1
A
When FET1 is measured,
Gate and Source of FET2
are short−circuited.
V
V
SS
V
GS
V
GS
Figure 3. Test Circuit 3
t (on), t , t (off), t
Figure 4. Test Circuit 4
Qg
S2
G2
d
r
d
f
S2
RL
A
G2
When FET1 is measured,
Gate and Source of FET2
are short−circuited.
V
I
G
= 1 mA
G1
RL
G1
Rg
V
SS
S1
S1
V
SS
PG
When FET1 is measured,
Gate and Source of FET2
are short−circuited.
DC
Figure 5. Test Circuit 5
Figure 6. Test Circuit 6
V
F(S−S)
S2
I
S
G2
G1
VGS = 0 V
V
When FET1 is measured,
S1
+4.5 V is added to V
of FET2.
GS
Figure 7. Test Circuit 7
NOTE: When FET2 is measured, the position of FET1 and FET2 is switched.
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3
EFC2J004NUZ
6.0
5.0
4.0
3.0
15
12
9
3.1 V
4.5 V
T = 25°C
A
V
SS
= 6 V
T = 75°C
A
3.8 V
25°C
V
GS
= 2.5 V
6
3
0
2.0
1.0
−25°C
0
0
0.01
0.02
0.03
0.04
0.05
0.06
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8. 2.0
V
SS
, SOURCE−TO−SOURCE VOLTAGE (V)
Figure 8. IS − VSS
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
Figure 9. IS − VGS
10
9
14
12
T = 25°C
S
A
I
= 5 A
V
GS
= 2.5 V, I = 5 A
S
8
10
8
V
GS
= 3.1 V, I = 5 A
S
7
6
6
4
2
5
4
3
V
= 4.5 V, I = 5 A
S
GS
V
= 3.8 V, I = 5 A
S
GS
1
2
3
5
6
7
8
0
40
4
−60 −40 −20
20
60 80 100 120 140 160
T , AMBIENT TEMPERATURE (°C)
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
Figure 10. RSS(on) − VGS
A
Figure 11. RSS(on) − Ta
10
7
1000
100
10
7
5
V
GS
= 0 V
5
3
2
3
2
T = 75°C
A
1.0
7
5
7
5
3
3
2
td(off)
25°C
0.1
7
2
tf
tr
5
3
2
−25°C
7
5
0.01
7
5
V
V
= 5 V
= 3.8 V
td(on)
SS
3
2
3
2
GS
I
= 5 A
S
0.001
1.0
1.0
2
3
5
7
10
2
0
0.2
0.4
0.6
0.8
1.0
1.2
R , GATE RESISTANCE (kΩ)
g
V , FORWARD SOURCE TO SOURCE VOLTAGE (V)
F(S-S)
Figure 12. IS − VF(S−S)
Figure 13. SW Time − Rg
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4
EFC2J004NUZ
100
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
7
V
I
= 6 V
= 14 A
SS
5
3
2
I
I
= 60 A (PW ≤ 100 ꢀ s)
= 14 A
10 μs
100 μs
1 ms
SP
S
S
10
7
5
10 ms
100 ms
3
2
Operation in this area
1.0
7
is limited by R (on).
SS
DC Operation
(T = 25°C)
5
3
2
A
0.1
T
= 25°C
7
A
5
Single Pulse
When mounted on ceramic substrate
(5000 mm x 0.8 mm)
3
2
2
0.01
0.01
7 0.1
7 10
2
3
5
2
3
71.0
2
3
5
2
3
5
0
5
10
15
20
25
30
35
40
V
SS
, SOURCE TO SOURCE VOLTAGE (V)
Q , TOTAL GATE CHARGE (nC)
g
Figure 14. VGS − Qg
Figure 15. SOA
1.6
1.4
Surface mounted on ceramic substrate
(5000 mm x 0.8 mm)
2
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
25
50
75
100 125 150 175 200
T , AMBIENT TEMPERATURE (°C)
A
Figure 16. PT − Ta
100
7
Duty Cycle = 0.5
0.2
5
3
2
0.1
10
7
0.05
5
3
2
0.02
0.01
1.0
7
5
Single Pulse
3
2
Surface mounted on ceramic substrate
(5000 mm x 0.8 mm)
2
0.1
2
3
5
7
5
7
2
3
5
7
2
3
2
3
5
7
2
3
5
7
2
3
5
7
0.0001
0.01
0.1
1.0
10
0.00001
0.001
P , PULSE TIME (S)
T
Figure 17. RqJA − Pulse Time
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5
EFC2J004NUZ
ORDERING INFORMATION
Device
†
Marking
Package
Shipping (Qty / Packing)
EFC2J004NUZTDG
NA
WLCSP6, 2.11x1.18x0.10
(Pb−Free / Halogen Free)
5000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Note on usage: Since the EFC2J004NUZ is a MOSFET product, please avoid using this device in the vicinity of highly charged objects. Please contact sales
for use except the designated application.
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6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WLCSP6, 2.11x1.18x0.10
CASE 567NP
ISSUE B
SCALE 4:1
DATE 22 DEC 2016
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
D
A
B
E
2. CONTROLLING DIMENSION: MILLIMETERS.
MILLIMETERS
DIM
A
b
b1
b2
D
E
e
e2
MIN
0.08
0.22
0.27
0.575
NOM
0.10
0.25
0.30
0.605
2.11 BSC
1.18 BSC
0.55 BSC
0.6775 BSC
MAX
0.12
0.28
0.33
0.635
PIN A1
REFERENCE
2X
0.05
0.05
C
C
2X
TOP VIEW
SIDE VIEW
A
0.05
0.05
C
GENERIC
MARKING DIAGRAM*
C
SEATING
C
PLANE
XXXXXG
AYWZZG
4X b2
0.05
e2
A
Y
= Assembly Location
= Year
M
C A B
1
2
3
W
= Work Week
e
ZZ = Assembly Lot
G
= Pb−Free Package
(Note: Microdot may be in either location)
6
5
4
2X
4X b1
C A B
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
b
M
M
0.05
0.05
BOTTOM VIEW
C A B
RECOMMENDED
SOLDERING FOOTPRINT*
4X
0.605
2X
0.25
PACKAGE
OUTLINE
0.55
PITCH
4X
0.30
1
0.678
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON10195G
WLCSP6, 2.11X1.18X0.10
PAGE 1 OF 1
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