FAN53840UC00X [ONSEMI]
Four Channel Load-Switch/LDO Configurable PMIC;
| 型号： | FAN53840UC00X |
| 厂家： | 
ONSEMI |
| 描述： | Four Channel Load-Switch/LDO Configurable PMIC 集成电源管理电路 |
| 文件： | 总42页 (文件大小：1546K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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Four Channel Load-Switch /
LDO Configurable PMIC
1
WLCSP16 1.52x1.52x0.432
CASE 567ZM
FAN53840, FAN53841
General Description
MARKING DIAGRAM
The FAN53840 family are low Iq PMICs intended for mobile power
application camera modules. The PMIC contains a high−power
regulated channel for digital rails which can operate with an input as
low as 1.0 V. Three channels are designed for ultra−low noise and high
PSRR for sensitive analog/RF circuit loads. Each channel can be
configured to operate as a pass−through load−switch, which reduces
the input to output voltage drop and operating currents in critical low
power applications.
LRKK
XYZ
1
LR
KK
X
Y
Z
= Specific Device Code
= Lot Run Code
= Alphabetical Year Code
= 2−weeks Date Code
= Assembly Plant Code
The device is available in 16−bump, 0.35 mm pitch, Wafer−Level
Chip−Scale Package (WLCSP).
Features
• LDO1:
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
♦ 1.2 A Output Current Capability
♦ Programmable Output Voltage 0.8 V to 1.504 V in 8 mV Steps
♦ 1.0 V to 2.0 V Input Voltage Range
♦ 1.1% to −1.5% Accuracy
• LDO2, LDO3, and LDO4:
♦ 300 mA Output Current Capability
♦ Programmable Output Voltage 1.5 V to 3.412 V in 8 mV Steps
♦ 1.9 V to 5.5 V Input Voltage Range
♦ Less than 20 mV (typ) Noise
• Load−Switch Operation:
♦ 100/200 mW Maximum Channel Resistance
♦ Low Operating Currents
♦ Input Voltages Down to 1.0 V and 1.8 V
• Operation Guaranteed with System Voltage Down to 2.6 V
• Soft−Start Function (SS) to Limit Inrush Current
• Current Limit to Protect Against Short Circuit
2
• I C Protection Fault (UVLO and OCP in LDO Operation) Registers
2
• I C Serial Control to Program Output Voltage and Features
• System UVLO and Thermal Global Shutdown Protection for LDOs
• Pb−Free Devices
Applications
• Smart Phones
• Wearables
• Smart Watch
• Health Monitoring
• Sensor Drive
• Energy Harvesting
• Utility and Safety Modules
• RF Modules
© Semiconductor Components Industries, LLC, 2021
1
Publication Order Number:
July, 2022 − Rev. 6
FAN53840/D
FAN53840, FAN53841
ORDERING INFORMATION
2
I/O Logic
Level
I C
Address LDO1 LDO2
Mark-
ing
LDO3
VOUT
LDO4
VOUT
Interrupt Pin
Polarity
Temperature
Range
†
Shipping
Part Number
FAN53840UC00X
FAN53841UC00X
(Note 1)
(Note 2) VOUT
VOUT
Package
O
LR
L9
1.8 V
1.2 V
7’h20 1.2 V
2.85 V
1.8 V
1.8 V
Active Low
−40 C to
20−Bump 3000 / Tape &
O
+85 C
WLCSP
(Pb−Free)
Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
1. RESET_B, SDA, SCL (open drain type pins)
2. I2C address is configurable. See I2C section for more information on setting the device address
APPLICATION CIRCUIT
Application Circuit Diagram
VSYS
VSYS
ADDR
INT_B
floating
C
SYS
RESET_B
OUT1
SCL
SDA
VIN1
D
VDD
FAN5384x
C
LDO1
A
OUT2
OUT3
VDD
C
VIN2
VIN3
VIN4
LDO2
C
VIN1
A
V18_1
C
VIN2
C
LDO3
A
V18_2
OUT4
C
C
VIN3
C
LDO4
VIN4
DGND
AGND
Figure 1. LDO Mode
VSYS
VSYS
ADDR
floating
C
SYS
INT_B
RESET_B
OUT1
SCL
SDA
VIN1
FAN5384x
C
LS1
OUT2
OUT3
OUT4
VIN2
VIN3
VIN4
C
C
LS2
VIN1
C
VIN2
C
LS3
C
VIN3
C
C
LS4
VIN4
DGND
AGND
Figure 2. Load Switch Mode
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2
FAN53840, FAN53841
Application Circuit Components
Table 1. RECOMMENDED EXTERNAL COMPONENTS
Component
, C , C ,
VIN3
Manufacturer
Part Number
Value
Case Size
Voltage Rating
C
Murata
GRM033R61A105ME15
1.0 mF
0201/0603 (0.6 mm x 0.3 mm)
10 V
VIN1
VIN2
C
VIN4
C
C
Murata
Taiyo Yuden
Murata
GRM033R61A105ME15
JMK105CBJ106MV−F
GRM033R60J225ME47D
GRM033R60J104KE19
1.0 mF
10 mF
2.2 mF
0.1 mF
0201/0503 (0.5 mm x 0.3 mm)
0402/1005 (1.0 mm x 0.5 mm)
0201/0603 (0.6 mm x 0.3 mm)
0201/0603 (0.6 mm x 0.3 mm)
10 V
6.3 V
6.3 V
6.3 V
VSYS
LDO1
LDO3
C
, C
, C
LDO4
LDO2
C
, C , C , C
LS4
Murata
LS1
LS2
LS3
PRODUCT PIN ASSIGNMENTS
OUT4
VIN4
A2
VIN3
OUT3
A4
OUT3
A4
VIN3
A3
VIN4
A2
OUT4
A1
A1
A3
OUT1
B1
SCL
B2
SDA
B3
RESET_B
B4
RESET_B
B4
SDA
B3
SCL
B2
OUT1
B1
VIN1
C1
INT_B
C2
ADDR
C3
VIN2
C4
VIN2
C4
ADDR
C3
INT_B
C2
VIN1
C1
DGND
D1
VSYS
D2
AGND
D3
OUT2
D4
OUT2
D4
AGND
D3
VSYS
D2
DGND
D1
Top View (Bumps Down)
Bottom View (Bumps Up)
Figure 3. Pin Configuration
PIN DEFINITIONS
Pin
A1
A2
Pin Name
OUT4
Description
(or C ) as close to this pin as possible.
This is the output pin for Channel 4. Place C
LDO4
LS4
VIN4
Input power pin for Channel 4. Place C
recommended to tie to VSYS.
as close to this pin as possible. If Channel 4 is unused, it is
VIN4
A3
VIN3
This is the input power pin for Channel 3. Place C
it is recommended to tie to VSYS.
as close to this pin as possible. If Channel 3 is unused,
VIN3
A4
B1
B2
B3
B4
OUT3
OUT1
This is the output pin for Channel 3. Place C
(or C ) as close to this pin as possible.
LS3
LDO3
This is the output pin for Channel 1. Place C
(or C ) as close to this pin as possible.
LS1
LDO1
2
SCL
I C Clock pin. Node should be tied high through a pull−up resistor.
2
SDA
I C Data pin. Node should be tied high through a pull−up resistor.
RESET_B
RESET_B pin is used to enable basic circuits necessary for controlling the PMIC. The RESET_B pin has an
internal 4 MW (typ) pull−down and should always be connected to a logic high or low.
C1
C2
VIN1
Input power pin for Channel 1. Place C
as close to this pin as possible. If Channel 1 is unused, it is
VIN1
recommended to tie to VSYS.
INT_B
Fault interrupt pin is an open−drain configuration and pulls low to indicate an interrupt event has occurred. This
2
pin returns to Hi−Z when all I C interrupt bits equal 0. An external pull−up resistor is required.
2
2
C3
C4
ADDR
VIN2
I C address select pin. Either tie to ground, VSYS, or leave unconnected for desired I C address.
Input power pin for Channel 2. Place C
recommended to tie to VSYS.
as close to this pin as possible. If Channel 2 is unused, it is
VIN2
D1
D2
DGND
VSYS
Digital/Analog ground connection. If used as separate return for Channel 1 load, connect the return plane to
AGND at a via on a plane below the AGND plane.
System power pin. Route trace from system to this pin. Connect the C
the pin.
capacitor as close as possible to
VSYS
D3
D4
AGND
OUT2
Digital/Analog ground connection. Tie to power plane.
This is the output pin for Channel 2. Place C
(or C ) as close to this pin as possible.
LS2
LDO2
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3
FAN53840, FAN53841
PRODUCT BLOCK DIAGRAM
Block Diagram
OUT1
OUT2
VIN1
uvlo1
Vin1_ref
Ldo1_ocp
+
−
Ldo1_ilim
OUT1 Control
FAN53840
VIN2
uvlo2
Vin2_ref
Ldo2_ocp
+
−
Ldo2_ilim
OUT2 Control
OUT3 Control
VIN3
VIN4
OUT3
OUT4
uvlo3
Vin3_ref
Ldo3_ocp
+
−
Ldo3_ilim
uvlo4
Vin4_ref
Ldo4_ocp
+
−
OUT4 Control
Digital
Ldo4_ilim
POR
Control
uvlos
Core
Analog
Block
uvlo1
VSYS
uvlo2
uvlo3
uvlos
Twrn
Vsys_ref
uvlo4
Temp
Detect
Tsd
Ldo1_ocp
Ldo2_ocp
Ldo3_ocp
Ldo4_ocp
RESET_B
INT_B
2
ADDR
SDA
I C
AGND
SCL
DGND
AGND
Figure 4. Block Diagram
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4
FAN53840, FAN53841
MAXIMUM RATINGS
Symbol
Parameter
Conditions
Min
−0.3
−0.3
−0.3
Typ
−
Max
6.0
6.0
6.0
Unit
V
V
System Supply Voltage Range
Low−Voltage Supply Range
High−Voltage Supply Range
SYS
V
−
V
IN1
V
, V
IN3
IN4
,
−
V
IN2
V
V
SDA, SCL, and RESET_B
INT_B
−0.3
−0.3
−0.3
−
−
−
6.0
6.0
V
V
V
CTRL
V
INTB
OUT1/2/3/4
V
All Supply Output Pins
V
IN1/2/3/4
+ 0.3 V
Ipin_max
ESD
Pin Current
−
−
−
2.0
500
−
1.5
A
ESD − HBM
Human Body Model
−
kV
V
ESD
ESD − CDM
Charged Device Model
−
−
T
J
Junction Temperature
Storage Temperature
Soldering Temperature
−40
−65
−
+150
+150
+260
°C
°C
°C
T
STG
−
T
L
−
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
THERMAL CHARACTERISTICS
Symbol
Characteristic
Conditions
Min
−
Typ
126
45
Max
−
Unit
°C/W
°C/W
q
q
Thermal Resistance Junction/Air
Thermal Resistance Junction/Board
1S PCB @ 0.5 W Dissipation
JA
JB
2S2P w/ Vias @0.5 W
Dissipation
−
−
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V
SYS
Supply Voltage Range – CHAN1
VSYS relative to OUT1
V
+
−
5.5
V
OUT1
1.95 V
V
Supply Voltage Range – CHAN2/3/4
CHAN1 Input Supply Voltage Range
CHAN1 LDO Mode Headroom
VSYS relative to OUT2/3/4
LDO and LS Modes
2.6
−
−
−
−
5.5
2.0
V
V
SYS
V
1.0
IN1
V
V
VIN1
− V
200
1.9
mV
V
IN1
OUT1
V
V
CHAN2/3/4 LDO Mode Supply
Voltage Range
5.5
IN2/3/4
CHAN2/3/4 LDO Mode Headroom
V
V
− V
− V
VIN4
,
,
300
−
−
mV
IN2/3/4
VIN2
VIN3
OUT2
OUT3
and V
− V
OUT4
V
CHAN2/3/4 LS Mode Supply
Voltage Range (Note 3)
Any Channel in LDO Mode
CHAN1/2/3/4 = LS Mode
1.8
1.7
−
−
−
−
5.0
5.0
V
V
IN2/3/4
P
D
Max Power Dissipation
P
D
= (125°C − 85°C) / 45°C/W
0.88
W
= 0.88 W
T
Ambient Temperature
Junction Temperature
−40
−40
−
−
+85
°C
°C
A
T
+125
J
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
3. Please refer to the Under Voltage Lockout (UVLO) section in Device Operation for details.
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FAN53840, FAN53841
ELECTRICAL CHARACTERISTICS
Unless otherwise noted, the device is characterized for minimums and maximums across the ranges listed in the Recommended
Operating Conditions. All limits are characterized using components from Recommended External Components table.
Production testing and testing for typical values is performed at T = 25°C, For LDO Mode: V
= 3.45 V, V
VIN1
= 1.8 V and V
= 1.3 V,
= 5.0 V.
A
VSYS
V
VIN2
= 3.45 V, V
and V
= 1.95 V; For LS Mode: V
= 3.80 V, V
= V
= V
VIN3
VIN4
VSYS
VIN1
VIN3
VIN4 VIN2
Symbol
POWER SUPPLY UVLO
Parameter
Conditions
Min
Typ
Max
Unit
V
System Under−Voltage Lockout Rising V
2.30
2.35
2.25
0.95
0.85
1.85
1.75
2.40
2.30
1.00
0.92
1.90
1.80
V
V
V
V
V
V
SYS UVLO_RS
VSYS
VSYS
VIN1
Threshold
V
System Under−Voltage Lockout Falling V
Threshold
2.20
0.90
0.80
1.80
1.70
SYS UVLO_FL
V
Channel 1 Under−Voltage
Rising V
Falling V
Rising V
Falling V
VIN1 UVLO_RS
Lockout Threshold
V
Channel 1 Under−Voltage
Lockout Threshold
VIN1 UVLO_FL
VIN1
V
Channel 2/3/4 Under−Voltage
Lockout Threshold
VIN_H UVLO_RS
VIN2/3/4
VIN2/3/4
V
Channel 2/3/4 Under−Voltage
Lockout Threshold
VIN_H UVLO_FL
CHANNEL 1 QUIESCENT CURRENT
IQ
Quiescent Current, LDO Mode
I
I
= 0 A, total I and
VSYS
−
−
67
75
mA
mA
LD1
OUT1
VIN1
currents when
LDO_LS1_SELECT = 0,
CHAN1_EN = 1 and all other
channels disabled.
IQ
Quiescent Current, LS Mode
I
I
= 0 A, total I
and
1.29
3.0
LS1
OUT1
VIN1
VSYS
currents when all
LDO_LSx_SELECT = 1,
CHAN1_EN = 1 and all other
channels are disabled.
CHANNEL 1 OUTPUT VOLTAGE
VO
LDO1 Output Voltage Accuracy
LDO1 Dropout Voltage (Note 4)
LDO1 Dropout Voltage (Note 4)
I
V
V
= 1 mA and 1200 mA,
−1.5
−
−
50
77
+1.1
85
%
L1_ACC
OUT1
VIN1
= 2.0 V, V
= 3.45 V,
VSYS
= 0.8 to 1.5 V
OUT1
V
I
= 600 mA,
mV
mV
L1_DO_600
OUT1
V
= 1.20 V,
OUT1
and V
= 3.00 V
VSYS
V
I
= 1000 mA,
−
125
L1_DO_1000
OUT1
V
= 1.05 V,
OUT1
and V
= 3.00 V
VSYS
CHANNEL 1 DRAIN−SOURCE ON RESISTANCE
RDS LS1 R
V
= 1.8 V, V = 3.2 V,
VSYS
−
76
175
mW
ON1
DS(on)
VIN1
all LDO_LSx_SELECT = 1,
CHAN1_EN = 1,
and I
= 50 mA
OUT1
CHANNEL 1 CURRENT LIMIT
I
Current Limit
V
VIN1
V
VIN1
V
VSYS
≥ V +300 mV and
OUT1
1250
1400
1700
mA
LIM_H1
= 1.1 to 2.0 V,
≥ V + 1.95 V
OUT1
T
T
Over−Current Restart Timer
−
−
20
−
−
ms
ms
L1 OC_RST
2
Over−Current Debounce Timer
I C Register 0x07h = 11
1.0
L1 OC_DEB
CHANNEL 1 OUTPUT PROTECTION
Output Discharge
R
80
100
120
W
L1_DCHG
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FAN53840, FAN53841
ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise noted, the device is characterized for minimums and maximums across the ranges listed in the Recommended
Operating Conditions. All limits are characterized using components from Recommended External Components table.
Production testing and testing for typical values is performed at T = 25°C, For LDO Mode: V
= 3.45 V, V
VIN1
= 1.8 V and V
= 1.3 V,
= 5.0 V.
A
VSYS
V
VIN2
= 3.45 V, V
and V
= 1.95 V; For LS Mode: V
= 3.80 V, V
= V
= V
VIN3
VIN4
VSYS
VIN1
VIN3
VIN4 VIN2
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
CHANNEL 2 QUIESCENT CURRENT
IQ
Quiescent Current, LDO Mode
Quiescent Current, LS Mode
I
I
= 0 A, total I and
VSYS
−
55
63
mA
LD2
LS2
OUT2
VIN2
currents when
LDO_LS2_SELECT = 0,
CHAN2_EN = 1 and all other
channels disabled.
IQ
I
I
= 0 A, total I
and
−
1.32
3.5
mA
OUT2
VIN2
VSYS
currents when all
LDO_LSx_SELECT = 1,
CHAN2_EN = 1 and all other
channels are disabled.
CHANNEL 2 OUTPUT VOLTAGE
VO
LDO2 Output Voltage Accuracy
IOUT = 1 mA and 300 mA,
VSYS = 3.45 V, VIN2 ≥3.45 V
and VIN2 ≥ VOUT + 300 mV,
VOUT = 1.5 to 3.412 V
−1.3
−
+1.0
100
%
L2_ACC
V
L2_DO
LDO2 Dropout Voltage (Note 4)
V
V
OUT2
= 1.8 V,
−
−
66
mV
OUT2
VSYS
= 3.45 V,
I
= 300 mA
CHANNEL 2 DRAIN−SOURCE ON RESISTANCE
RDS LS2 R
V
VIN2
= 5 V, V = 3.2 V,
VSYS
76
100
mW
ON2
DS(on)
all LDO_LSx_SELECT = 1,
CHAN2_EN = 1,
I
= 50 mA
OUT2
CHANNEL 2 CURRENT LIMIT
I
Current Limit
V
VIN2
V
VIN2
V
VSYS
≥ V + 500 mV and
OUT2
320
400
480
mA
LIM_L2
= 2.0 to 5.5 V,
= 3.45 V
T
T
Over−Current Restart Timer
−
−
20
−
−
ms
ms
L2 OC_RST
2
Over−Current Debounce Timer
I C Register 0x07h = 11
1.0
L2 OC_DEB
CHANNEL 2 OUTPUT PROTECTION
Output Discharge
CHANNEL 3/4 QUIESCENT CURRENT
R
80
100
55
120
63
W
L2_DCHG
IQ
Quiescent Current, LDO Mode
I
I
= 0 A, total I and
VSYS
currents when
−
mA
LD3/4
OUT3
VIN3
LDO_LS3/4_SELECT = 0,
CHAN3/4_EN = 1 and all other
channels disabled.
IQ
Quiescent Current, LS Mode
I
I
= 0 A, total I
and
−
2.62
8
mA
LS3/4
OUT3
VIN3
VSYS
currents when all
LDO_LSx_SELECT = 1,
CHAN3/4_EN = 1 and all other
channels are disabled.
CHANNEL 3/4 OUTPUT VOLTAGE
VO
LDO3/4 Output Voltage
Accuracy
I
= 1 mA and 300 mA,
= 3.45 V,
−1.0
−
+1.0
100
%
L3/4_ACC
OUT3/4
VSYS
V
V
V
V
≥ 3.45 V and ≥
VIN3/4
OUT3/4
OUT3/4
+300 mV,
= 1.5 to 3.412 V
V
LDO3/4 Dropout Voltage
(Note 4)
V
V
= 1.8 V,
−
68
mV
L3/4_DO
OUT3/4
= 3.45 V,
= 300 mA
VSYS
I
OUT3/4
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FAN53840, FAN53841
ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise noted, the device is characterized for minimums and maximums across the ranges listed in the Recommended
Operating Conditions. All limits are characterized using components from Recommended External Components table.
Production testing and testing for typical values is performed at T = 25°C, For LDO Mode: V
= 3.45 V, V
VIN1
= 1.8 V and V
= 1.3 V,
= 5.0 V.
A
VSYS
V
VIN2
= 3.45 V, V
and V
= 1.95 V; For LS Mode: V
= 3.80 V, V
= V
= V
VIN3
VIN4
VSYS
VIN1
VIN3
VIN4 VIN2
Symbol
CHANNEL 3/4 DRAIN−SOURCE ON RESISTANCE
RDS LS3/4 R
Parameter
Conditions
Min
Typ
Max
Unit
V
= 1.8 V, V = 3.2 V,
VSYS
−
76
100
mW
ON3/4
DS(on)
VIN3/4
all LDO_LSx_SELECT = 1,
CHAN3/4_EN = 1,
I
= 50 mA
OUT3/4
CHANNEL 3/4 CURRENT LIMIT
I
Current Limit
V
≥ V + 500 mV
OUT3/4
VIN3/4
= 3.45 V
320
400
480
mA
LIM_L3/4
VIN3/4
and V
= 2.0 to 5.5 V,
V
VSYS
T
T
Over−Current Restart Timer
−
−
20
−
−
ms
ms
L3/4 OC_RST
2
Over−Current Debounce Timer
I C Register 0x07h = 11
1.0
L3/4 OC_DEB
CHANNEL 3/4 OUTPUT PROTECTION
R
Output Discharge
80
100
120
W
L3/4_DCHG
I/O LEVELS
V
RESET_B Logic Low Threshold
RESET_B Logic High Threshold
FAN53840
FAN53841
FAN53840
FAN53841
0.4
V
IL
0.325
V
IH
1.2
0.825
−
V
IN
IN
V
V
INT_B V
I = 3 mA
sink
−
0.3
V
OL_INT_B
OLmax
I
INT_B Leakage
ADDR Input Resistance
ADDR Current
ADDR High
V
INT_B
V
VSYS
V
VSYS
= 5.5 V
−
−
−
893
1.57
80
0.5
−
mA
kW
mA
INT_B
R
= 2.6 to 5.5 V
= 2.6 to 5.5 V
ADDR
ADDR
I
−
−
ADDR
−
93
−
%V
VIH
VSYS
VSYS
ADDR
ADDR Low
8.0
20
%V
VIL
IQ CONDITIONS
I
System Shutdown Current
I
when V = 5.5 V,
VSYS
−
−
−
−
−
−
3.0
0.3
2.5
mA
mA
mA
Q VSYS_SD
VSYS
all CHANx_EN bits = 0,
RESET_B = SDA = SCL =
Low, and T = 85_C
J
I
Channel 1 Shutdown Current
I
when V
= 2.0 V,
Q VIN1_SD
VIN1
VIN1
all CHANx_EN bits = 0,
RESET_B = SDA = SCL =
Low, T = 85_C
J
I
Channel 2/3/4 Shutdown
Current
I
when V
= 5.5 V;
Q VIN2/3/4_SD
VIN2
VIN2
or I
or I
when V
= 5.5 V;
VIN3
VIN4
VIN3
VIN4
when V
= 5.5 V.
All CHANx_EN bits = 0,
RESET_B = SDA = SCL =
Low, T = 85_C
All channels configured as
LDO, all enabled with no load.
(Note 5)
J
I
LDO Mode Standby Current
LS Mode Standby Current
−
−
200
5
230
mA
mA
Q_STBY_LDO
I
All channels configured as LS,
all enabled with no load.
(Note 6)
13.0
Q_STBY_LS
www.onsemi.com
8
FAN53840, FAN53841
ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise noted, the device is characterized for minimums and maximums across the ranges listed in the Recommended
Operating Conditions. All limits are characterized using components from Recommended External Components table.
Production testing and testing for typical values is performed at T = 25°C, For LDO Mode: V
= 3.45 V, V
VIN1
= 1.8 V and V
= 1.3 V,
= 5.0 V.
A
VSYS
V
VIN2
= 3.45 V, V
and V
= 1.95 V; For LS Mode: V
= 3.80 V, V
= V
= V
VIN3
VIN4
VSYS
VIN1
VIN3
VIN4 VIN2
Symbol
IQ CONDITIONS
Parameter
Conditions
Min
Typ
Max
Unit
I
LDO Mode Sleep Current
LS Mode Sleep Current
All channels configured as
LDO, all disabled with no load.
(Note 7)
−
−
9.8
20
mA
SLP_LDO
I
All channels configured as LS,
all disabled with no load.
(Note 8)
1.3
5
mA
SLP_LS
2
I C TIMING AND PERFORMANCE*
V
SDA and SCL Low Threshold
FAN53840
FAN53841
FAN53840
FAN53841
3 mA Sink
−0.5
−0.5
0.7 V
−
−
−
−
−
−
−
−
0.3 V
V
V
IL
DD
0.325
5.5
5.5
0.24
−
V
IH
SDA and SCL High Threshold
V
DD
0.825
−
V
V
OL
SDA Logic Low Output
SDA Sink Current
V
I
OL
20
mA
kHz
ms
f
SCL Clock Frequency
Fast Mode Plus
−
1000
−
SCL
BUF
t
Bus−Free Time Between STOP Fast Mode Plus
and START Conditions
0.5
t
t
Start or Repeated Start Hold
Time
Fast Mode Plus
260
−
−
ns
HD;STA
t
SCL Low Period
Fast Mode Plus
Fast Mode−Plus
Fast Mode−Plus
Fast Mode Plus
Fast Mode Plus
Fast Mode Plus
Fast Mode Plus
Fast Mode Plus
0.5
260
260
50
−
−
−
−
−
−
−
−
−
−
−
ms
ns
ns
ns
ns
ns
ns
ns
LOW
t
SCL High Period
HIGH
Repeated Start Setup Time
Data Setup Time
−
SU;STA
SU;DAT
VD;DAT
VD;ACK
t
t
−
Data Valid Time
450
450
120
120
t
Data Valid Acknowledge Time
SDA and SCL Rise Time
SCL and SDA Fall Time
−
t
R
−
t
F
20 x V
/
DD
5.5 V
260
−
t
Stop Condition Setup Time
Input Capacitance
Fast Mode Plus
−
−
−
−
10
ns
pF
pF
SU;STO
C
i
C
Capacitive Load for SDA and
SCL
−
550
b
t
SP
Pulse width of spikes which
must be suppressed by input
filter
SCL, SDA only
0
−
50
ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. LDOx Dropout Voltage is measured by lowering V
until V
= VOUT_TARGET – 50 mV.
VINx
OUTx
5. Total I
6. Total I
7. Total I
8. Total I
, I
, I
, I
, and I
, and I
, and I
, and I
when RESET_B = High, all CHANx_EN = 1, and all LDO_LSx_SELECT = 0.
VSYS VIN1 VIN2 VIN3
VSYS VIN1 VIN2 VIN3
VIN4
VIN4
VIN4
VIN4
, I
, I
, I
when RESET_B = High, all CHANx_EN = 1, and all LDO_LSx_SELECT = 1.
when RESET_B = High, SCL = SDA = Low, all CHANx_EN = 0, and all LDO_LSx_SELECT = 0.
when RESET_B = High, SCL = SDA = Low, all CHANx_EN = 0, and all LDO_LSx_SELECT = 1.
, I
, I
, I
VSYS VIN1 VIN2 VIN3
, I
, I
, I
VSYS VIN1 VIN2 VIN3
Guarantee Levels:
*Guaranteed by Design Only. Not Characterized or Production Tested.
www.onsemi.com
9
FAN53840, FAN53841
SYSTEM CHARACTERISTICS
Unless otherwise noted, the device is characterized for minimums and maximums across the ranges listed in the Recommended
Operating Conditions. All limits are characterized using components from Recommended External Components table.
Production testing and testing for typical values is performed at T = 25°C, For LDO Mode: V
= 3.45 V, V
VIN1
= 1.8 V and V
= 1.3 V,
= 5.0 V.
A
VSYS
V
VIN2
= 3.45 V, V
and V
= 1.95 V; For LS Mode: V
= 3.80 V, V
= V
= V
VIN3
VIN4
VSYS
VIN1
VIN3
VIN4 VIN2
Symbol
CHANNEL 1 STARTUP
Parameter
Conditions
Min
Typ
Max
Unit
T
LDO1 StartUp Time
Measured from CHAN1_EN
bit = High to 90% of
−
−
185
−
ms
SS_LDO1
V
= 1.20 V with
OUT1
OUT1
I
= 10 mA
T
LS1 Startup Time
Measured from CHAN1_EN
bit = High to 90% of
55
−
ms
SS_LS1
V
OUT1
= 1.8 V with
= 10 mA
VIN1
I
CHANNEL 1 PSRR & NOISE
PSRR
Power Supply Rejection Ratio
on LDO1
(Note 9) Freq = 100 kHz
= 1.3 V, V = 1.2,
−
−
25
23
−
dB
L1_VIN
V
N_L1
LDO1 Output Noise
V
35
mV
rms
VIN1
OUT1
Freq: 10 Hz to 100 kHz,
I
= 100 mA
OUT1
CHANNEL 1 REGULATION & TRANSIENT PERFORMANCE
REG
LDO1 Load Regulation
I
V
V
= 1 mA to 1000 mA,
−0.5
−
+0.5
%
L1_LD
OUT1
= 3.45 V, V
= 1.3 V,
VSYS
OUT1
VIN1
= 1.05 V, Load used for
comparison = 500 mA.
REG
LDO1 Line Regulation
LDO1 Load Transient
V
V
OUT1
= 3.45 to 4.5 V,
−0.05
−40
−
−
+0.05
+40
%
L1_LN
VSYS
OUT1
+ 300 mV ≤ V
≤ 2.0,
VIN1
I
= 50 mA
V
I
= 1mA <−> 1000 mA,
mV
L1 TR_LD
OUT1
150 mA/ms,
V
V
V
V
≥ V
+ 1.95 V,
= 1.0 to 1.7 V and
≥ V + 200 mV;
VSYS
VIN1
VIN1
OUT1
OUT1
= 0.8 to 1.5 V
OUT1
CHANNEL 2 STARTUP
T
LDO2 Startup Time
Measured from CHAN2_EN
bit = High to 90% of
−
−
150
75
−
−
ms
ms
SS_LDO2
V
= 2.85 V with
OUT2
OUT2
I
= 10 mA
T
LS2 Startup Time
Measured from CHAN2_EN
bit = High to 90% of
SS_LS2
V
OUT2
= 5.0 V with
= 10 mA
VIN2
I
CHANNEL 2 PSRR & NOISE
PSRR
Power Supply Rejection Ratio
on LDO2
(Note 10). Freq = 100 kHz
= 3.45 V, V = 2.85,
−
−
55
20
−
−
dB
L2_VIN
V
N_L2
LDO2 Output Noise
V
mV
rms
VIN2
OUT2
Freq: 10 Hz to 100 kHz,
I
= 300 mA
OUT2
CHANNEL 2 REGULATION & TRANSIENT PERFORMANCE
REG LDO2 Load Regulation
I
= 100 mA to 300 mA,
−0.1
−
+0.1
%
L2_LD
OUT2
V
= V
= 3.45 V, V
VSYS
VIN2 OUT2
= 2.85 V, Load used for com-
parison = 150 mA.
www.onsemi.com
10
FAN53840, FAN53841
SYSTEM CHARACTERISTICS (continued)
Unless otherwise noted, the device is characterized for minimums and maximums across the ranges listed in the Recommended
Operating Conditions. All limits are characterized using components from Recommended External Components table.
Production testing and testing for typical values is performed at T = 25°C, For LDO Mode: V
= 3.45 V, V
VIN1
= 1.8 V and V
= 1.3 V,
= 5.0 V.
A
VSYS
V
VIN2
= 3.45 V, V
and V
= 1.95 V; For LS Mode: V
= 3.80 V, V
= V
= V
VIN3
VIN4
VSYS
VIN1
VIN3
VIN4 VIN2
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
CHANNEL 2 REGULATION & TRANSIENT PERFORMANCE
REG
LDO2 Line Regulation
LDO1 Load Transient
V
V
V
V
= 2.85 V,
−0.10
−
+0.10
%
L2_LN
OUT2
VSYS
VIN2
= 2.6 to 5.5 V,
= 3.15 V and
+ 300 mV ≤ V
≤
OUT2
VIN2
5.5 V, V
= 3.45 V,
VSYS
V
OUT2
= 1.5 to 3.412,
OUT2
I
= 50 mA
V
I
= 1 mA <−> 300 mA,
= 3.45 V,
−26
−
+20
mV
L2 TR_LD
OUT2
50 mA/ms, V
VSYS
V
VIN2
V
VIN2
V
OUT2
≥ 3.00 V to 5.5 V and
≥ V
+ 300 mV,
OUT2
= 2.7 to 3.4 V
CHANNEL 3 STARTUP
T
LDO3 Startup Time
Measured from CHAN3_EN
bit = High to 90% of
−
−
150
150
−
−
ms
ms
SS_LDO3
V
= 1.8 V with
OUT3
OUT3
I
= 10 mA
T
LS3 Startup Time
Measured from CHAN3_EN
bit = High to 90% of
SS_LS3
V
VIN3
= 1.8 V, I
= 10 mA
OUT3
CHANNEL 3 PSRR & NOISE
PSRR
Power Supply Rejection Ratio
on LDO3
(Note 11) Freq = 100 kHz
Freq: 10 Hz to 100 kHz,
−
−
41
20
−
−
dB
L3_VIN
V
N_L3
LDO3 Output Noise
mV
rms
I
= 300 mA
OUT
CHANNEL 3 REGULATION & TRANSIENT PERFORMANCE
REG
REG
LDO3 Load Regulation
I
V
V
= 100 mA to 300 mA,
−0.1
−
−
+0.1
%
L3_LD
OUT3
= 3.45 V,
VSYS
= 1.95 V, V
= 1.8 V,
VIN3
OUT3
Load used for
comparison = 150 mA.
LDO3 Line Regulation
V
V
V
V
V
= 1.8 V,
−0.10
+0.10
%
L3_LN
OUT3
VSYS
VIN3
VSYS
VIN3
= 2.6 to 5.5 V,
= 2.3 V and
= 3.45 V,
= 2.3 to 5.5 V,
= 50 mA
I
OUT3
V
LDO3 Load Transient
I
= 1 mA <−> 300 mA,
≥ 9 V &
−30
−
+15
mV
L3 TR_LD
OUT3
50 mA/ms, V
VIN3
V
V
≥ V
+ 200 mV,
VIN3
OUT3
= 1.5 to 3.4 V
OUT3
CHANNEL 4 STARTUP
T
LDO4 Startup Time
Measured to CHAN4_EN
bit = High to 90% of
−
−
175
150
−
−
ms
ms
SS_LDO4
V
= 1.80 V, I
= 10 mA
OUT4
OUT4
T
LS4 Startup Time
Measured to CHAN4_EN
bit = High to 90% of
SS_LS4
V
VIN4
= 1.8 V, I
= 10 mA
OUT4
CHANNEL 4 PSRR & NOISE
PSRR
Power Supply Rejection Ratio
on LDO4
(Note 12) Freq = 100 kHz
−
41
−
dB
L4_VIN
www.onsemi.com
11
FAN53840, FAN53841
SYSTEM CHARACTERISTICS (continued)
Unless otherwise noted, the device is characterized for minimums and maximums across the ranges listed in the Recommended
Operating Conditions. All limits are characterized using components from Recommended External Components table.
Production testing and testing for typical values is performed at T = 25°C, For LDO Mode: V
= 3.45 V, V
VIN1
= 1.8 V and V
= 1.3 V,
= 5.0 V.
A
VSYS
V
VIN2
= 3.45 V, V
and V
= 1.95 V; For LS Mode: V
= 3.80 V, V
= V
= V
VIN3
VIN4
VSYS
VIN1
VIN3
VIN4 VIN2
Symbol
CHANNEL 4 PSRR & NOISE
LDO4 Output Noise
Parameter
Conditions
Min
Typ
Max
Unit
V
N_L4
Freq: 10 Hz to 100 kHz,
= 300 mA
−
20
−
mV
rms
I
OUT4
CHANNEL 4 REGULATION & TRANSIENT PERFORMANCE
REG
REG
LDO4 Load Regulation
I
= 100 mA to 300 mA,
−0.1
−
−
+0.1
%
L4_LD
L4_LN
OUT4
VIN4
V
V
V
= 1.95 V,
= 3.45 V,
= 1.8 V, Load used for
VSYS
OUT4
comparison = 150 mA.
LDO4 Line Regulation
V
V
V
V
V
= 1.8 V,
−0.10
−30
+0.10
%
OUT4
VSYS
VIN4
VSYS
VIN4
= 2.6 to 5.5 V,
= 2.3 V and
= 3.45 V,
= 2.3 to 5.5 V,
= 50 mA
I
OUT4
V
LDO3 Load Transient
I
= 1 mA <−> 300 mA,
−
+15
mV
L4 TR_LD
OUT4
50 mA/ms, V
≥ 1.9 V &
VIN4
OUT4
V
V
≥ V
+ 200 mV,
VIN4
= 1.5 to 3.4 V
OUT4
THERMAL PROTECTION
T
Thermal Warning
Thermal Shutdown
Thermal Hysteresis
115
125
15
125
140
20
135
155
25
°C
°C
°C
WRN
T
SD
T
HYS
9. V
10.V
11. V
12.V
= 1.3 V, V
= 3.45 V, V
= 1.2 V, I
= 150 mA, C
= 1.0 mF, C
VIN2
= 10 mF.
LDO2
VIN1
VIN2
VIN3
VIN4
VSYS
OUT1
OUT1
VIN1
LDO1
= 3.45 V, V
= 1.95 V, V
= 1.95 V, V
= 3.45 V, V
= 3.45 V, V
= 3.45 V, V
= 2.85 V, I
= 100 mA, C
= 1.0 mF, C
= 2.2 mF.
VSYS
VSYS
VSYS
OUT2
OUT3
OUT4
OUT2
= 1.8 V, I
= 1.8 V, I
= 100 mA, C
= 100 mA, C
= 1.0 mF, C
= 1.0 mF, C
= 2.2 mF.
= 2.2 mF.
OUT3
OUT4
VIN3
VIN4
LDO3
LDO4
www.onsemi.com
12
FAN53840, FAN53841
TYPICAL CHARACTERISTICS
(Unless otherwise noted, T = 25°C, For LDO Mode: V
= 3.45 V, V
= 1.3 V, V
= 3.45 V, V
and V
= 1.95 V; For LS
A
VSYS
VIN1
VIN2
VIN3
VIN4
Mode: V
= 3.80 V, V
= V
= V
= 1.8 V and V = 5.0 V. Using components from Recommended External Components.)
VIN2
VSYS
VIN1
VIN3
VIN4
0
0
−0.1
−0.2
−0.3
−0.4
−0.5
−0.1
−0.2
−0.3
−0.4
−0.5
−0.6
−0.7
−0.8
−0.6
2.0 VIN1
1.7 VIN1
1.3 VIN1
2.0 VIN1
1.3 VIN1
1.2 VIN1
−0.7
−0.8
0
200
400
600
800
1000
1200
0
200
400
600
800
1000 1200
OUT1 Load Current (mA)
OUT1 Load Current (mA)
Figure 5. LDO1 Output Voltage Accuracy vs.
Load Current and Input Voltage,
Figure 6. LDO1 Output Voltage Accuracy vs.
Load Current and Input Voltage, VOUT1 = 1.2 V
V
OUT1 = 1.05 V
0.3
0
−0.02
−0.04
−0.06
−0.08
−0.1
5.5 VIN3/4
3.7 VIN3/4
2.1 VIN3/4
0.25
0.2
0.15
0.1
0.05
0
−0.12
−0.14
−0.16
−0.18
5.5 VIN2
3.45 VIN2
3.15 VIN2
−0.05
−0.1
0
50
100
150
200
250
300
0
50
100
150
200
250
300
OUT2 Load Current (mA)
OUT3/4 Load Current (mA)
Figure 7. LDO2 Output Voltage Accuracy vs.
Load Current and Input Voltage, VOUT2 = 2.85 V
Figure 8. LDO3/4 Output Voltage Accuracy vs.
Load Current and Input Voltage, VOUT3/4 = 1.8 V
0
0.05
5.5 VSYS
4.5 VSYS
3.45 VSYS
−0.01
0.03
0.01
−0.02
−0.03
−0.04
−0.05
−0.06
−0.07
−0.08
−0.01
−0.03
−0.05
1.2 V OUT1
1.5 V OUT1
0.8 V OUT1
1.4
1.5
1.6
1.7
1.8
1.9
2
1.1
1.3
1.5
1.7
1.9
VIN1 Input Voltage (V)
VIN1 Input Voltage (V)
Figure 9. LDO1 Output Voltage Accuracy vs.
Input and System Voltage, VOUT1 = 1.2 V and
Figure 10. LDO1 Output Voltage Accuracy vs.
Input and Output Voltage, IOUT1 = 50 mA
IOUT1 = 50 mA
www.onsemi.com
13
FAN53840, FAN53841
TYPICAL CHARACTERISTICS (continued)
(Unless otherwise noted, T = 25°C, For LDO Mode: V
= 3.45 V, V
= 1.3 V, V
= 3.45 V, V
and V
= 1.95 V; For LS
A
VSYS
VIN1
VIN2
VIN3
VIN4
Mode: V
= 3.80 V, V
= sV
= V
= 1.8 V and V = 5.0 V. Using components from Recommended External Components.)
VIN2
VSYS
VIN1
VIN3
VIN4
0
0.2
0.15
0.1
2.85 V OUT2
1.5 V OUT2
3.4 V OUT2
−0.02
−0.04
−0.06
−0.08
−0.1
0.05
0
−0.05
1.5 V OUT3/4
1.8 V OUT3/4
3.4 V OUT3/4
−0.1
−0.15
−0.2
−0.12
1.9
2.9
3.9
4.9
1.9
2.9
3.9
4.9
VIN2 Input Voltage (V)
VIN3/4 Input Voltage (V)
Figure 11. LDO2 Output Voltage Accuracy vs.
Input and Output Voltage, IOUT2 = 50 mA
Figure 12. LDO3/4 Output Voltage
Accuracy vs. Input and Output Voltage,
IOUT3/4 = 50 mA
1.5
1.4
1.3
1.2
1.1
1
0.94
0.92
0.90
0.88
0.86
0.84
0.82
0.80
0.78
0.76
0.74
85°C
25°C
−40°C
−40°C
25°C
85°C
0.9
0.8
1.8
2.8
3.8
4.8
1
1.2
1.4
1.6
1.8
2
VIN2 Input Voltage (V)
VIN1 Input Voltage (V)
Figure 13. LS1 Quiescent Current vs.
Input Voltage and Temperature
Figure 14. LS2 Quiescent Current vs.
Input Voltage and Temperature
6.5
5.5
4.5
3.5
2.5
1.5
0.5
85°C
25°C
−40°C
1.8
2.8
3.8
4.8
VIN3/4 Input Voltage (V)
Figure 15. LS3/4 Quiescent Current vs.
Input Voltage and Temperature
www.onsemi.com
14
FAN53840, FAN53841
TYPICAL CHARACTERISTICS (continued)
(Unless otherwise noted, T = 25°C, For LDO Mode: V
= 3.45 V, V
= 1.3 V, V
= 3.45 V, V
and V
= 1.95 V; For LS
A
VSYS
VIN1
VIN2
VIN3
VIN4
Mode: V
= 3.80 V, V
= V
= V
= 1.8 V and V = 5.0 V. Using components from Recommended External Components.)
VIN2
VSYS
VIN1
VIN3
VIN4
Figure 16. LDO1 Load Transient, VVSYS = 3.45 V,
Figure 17. LDO2 Load Transient, VVSYS = 3.45 V,
V
VIN1 = 1.4 V, VOUT1 = 1.2 V, 1 mA <−> 1000 mA,
6 ms Edge
V
VIN2 = 3.45 V, VOUT2 = 2.85 V, 1 mA <−> 300 mA,
6 ms Edge
Figure 18. LDO3/4 Load Transient,
V
VSYS = 3.45 V, VVIN3/4 = 2.0 V, VOUT3/4 = 1.8 V,
1 mA <−> 300 mA, 6 ms Edge
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15
FAN53840, FAN53841
TYPICAL CHARACTERISTICS (continued)
(Unless otherwise noted, T = 25°C, For LDO Mode: V
= 3.45 V, V
= 1.3 V, V
= 3.45 V, V
and V
= 1.95 V; For LS
A
VSYS
VIN1
VIN2
VIN3
VIN4
Mode: V
= 3.80 V, V
= V
= V
= 1.8 V and V = 5.0 V. Using components from Recommended External Components.)
VIN2
VSYS
VIN1
VIN3
VIN4
Figure 19. LDO1 PSRR vs. Frequency,
OUT1 = 1.2 V, IOUT1 = 150 mA
Figure 20. LDO1 PSRR vs. Frequency,
VOUT1 = 1.05 V, IOUT1 = 150 mA
V
Figure 21. LDO2 PSRR vs. Frequency,
VOUT2 = 2.85 V, IOUT2 = 100 mA
Figure 22. LDO3/4 PSRR vs. Frequency,
VOUT3/4 = 1.8 V, IOUT3/4 = 100 mA
www.onsemi.com
16
FAN53840, FAN53841
FUNCTIONAL SPECIFICATIONS
2
Device Operation
channels will be disabled but I C communication will
remain. The status bit will remain set until the die
Overview
temperature drops to T
upon shutdown.
. The chip suspension bit is set
WRN
The FAN53840 PMIC is optimized to supply different sub
systems of battery powered mobile and IoT applications. It
integrates four channels that can be set to operate as LDOs
or Load−Switches (LS). The LDOs are low−dropout
regulators: one high−current and three high PSRR/low noise
After the die temperature falls below T
, the thermal
WRN
status and chip suspension bits will be cleared, and the
device will return to the operating conditions prior to the
thermal−shutdown event. Individual LDOs are permanently
disabled after four cumulative faults including thermal
faults. If the four cumulative faults are a combination of
thermal−shutdown and system UVLO faults, then prior to
enabling the LDOs, RESET_B pin needs to be toggled from
low to high.
LDOs. The LS are very low R
currents.
and operate at low
DS(on)
The features of the FAN53840 can be programmed
2
through an I C interface.
Under Voltage Lockout (UVLO)
The device features system and LDO UVLO protections.
When all channels are not selected as LDOs and LS, if the
system voltage (V ) falls below its UVLO falling
threshold, system UVLO interrupt and status bits will be set
and INT_B asserted low. The status bit will remain set until
Similarly to system UVLO, selecting all LS will render
thermal protection faults inactive.
sys
Enabling/Disabling
The channels can be enabled and disabled independently
with the ldox_en bits. To enable LDOs, with RESET_B set
high, select desired ldox_en bits while setting all ldo_lsx bits
to “0”. The LDOs have internal soft−start which limits the
inrush current to the current−limit setting of the LDO. The
LDOs will ignore faults during the first 1.5 ms while
starting−up.
To enable LS, with RESET_B set high, select desired
ldox_en bits while setting all ldo_lsx bits to “1”. The ldox_en
and ldo_lsx bits can be found in the ENABLE and
LDO_LS_SELECT registers, respectively.
The device features active discharge. This feature is
enabled through the ldox_discharge_enabled bits. A 100 W
resistor is connected internally between channel outputs and
GND to discharge the output capacitors. The
ldox_discharge_enabled bits can be found in the ENABLE
register.
V
sys
rises above its UVLO rising threshold. If all LS are
selected (By selecting all ldo_lsx bits), no bits will be set;
selecting all LS disables system UVLO protection faults. In
this state it is possible to operate the four load−switches with
their V below the range stated in the Recommended
IN
Operating Conditions table. This is likely to increase LS
RDS
and therefore output current derating should be
ON2
expected.
When enabling LDOs, if V is above the Power On Reset
(POR) voltage of 2 V but below its UVLO rising threshold,
sys
or, if V is above its UVLO rising threshold but LDO input
sys
voltages are below their UVLO rising thresholds,
corresponding UVLO interrupt and status bits will be set and
INT_B asserted low. The status bits remain set as long the
UVLO fault condition is present.
Similarly, bits and INT_B will be set and asserted low,
respectively, when V falls below its UVLO falling
To do a global shutdown of all channels, set RESET_B pin
to low.
sys
threshold and channels are not all configured as LS, or, V
sys
It is not recommended to change configuration from LS
to LDO operation while the output is loaded. The channel
will attempt a restart and the output may drop significantly.
It is recommended to first de−select the channels (with
ldox_en bits), de−select all ldo_lsx bits, then select the
channels for LDO operation.
is above its UVLO rising threshold but LDO input voltages
fall below their UVLO falling threshold.
In the cases above, the LDOs will not be restarted for a
minimum of 20ms and until V rises above its rising
sys
threshold. Individual LDOs are permanently disabled after
four cumulative faults including UVLO faults. The LDOs
need to be enabled to return to operation. If the four
cumulative faults are a combination of thermal−shutdown
and system UVLO faults, then prior to enabling the LDOs,
RESET_B pin needs to be toggled from low to high.
Over−Current Protection (OCP)
The LDOs are protected from short−circuits and
excessive loads. When a short−circuit or excessive load
condition occurs on an output, the current is limited to the
Current Limit value of the LDO and, depending on the
difference between input and programmed output voltage,
the output voltage may drop. The resultant output voltage is
the product of Current Limit and load impedance.
When a current−limit event is detected, the LDOs’
associated OCP status bit is set. If the LDO remains in
current−limit for 1 ms, the corresponding interrupt bit is set
and INT_B asserted low. The LDO will be shutdown and
a restarts attempted every 20 ms. Individual LDOs are
Thermal Management
When the die temperature rises to the Thermal Warning
(T
) threshold, interrupt and status bits indicating
WRN
thermal−warning are set and INT_B asserted low. The status
bit remains set until the die temperature drops to a nominal
105°C.
If the die temperature continues to rise to the Thermal
Shutdown threshold, interrupt and status bits indicating
thermal−shutdown will be set and INT_B asserted low. All
www.onsemi.com
17
FAN53840, FAN53841
permanently disabled after four cumulative faults including
OCP faults. The LDOs need to be enabled to return to
operation.
I2C Slave Address
2
The FAN53840 provides three different I C addresses.
The addresses can be set by connecting the ADDR pin
according to the settings in Table 2. Depending on the
setting of the ADDR Pin when RESET_B is asserted high,
the device address will be selected. To reset the address,
disable the device by pulling RESET_B low. Reconfigure
the ADDR pin to the desired setting then enable the device
by asserting RESET_B high.
Multiple Fault Shutdown
To prevent repetitive starting and faulting of an LDO or of
the IC itself, detection of four faults will result in a complete
shutdown of an LDO or, if system faults, the IC will
shutdown.
Individual LDO Fault: the LDO will be shutdown after the
fourth fault for any combination of UVLO and/or OCP
faults. The LDO will automatically be de−selected and will
require enabling to return to operation.
System Fault: all channels will be shutdown after the
fourth chip fault for any combination of thermal−shutdown
and/or system UVLO faults. All channels will automatically
be de−selected. Enabling of the channels will require
RESET_B pin to be toggled from low to high first.
2
The I C is accessible approximately 300 ms after enabling
the device through asserting RESET_B high. For reliable
reads of the ADDR pin setting, it is recommended for
ADDR pin not to change states during the 300 ms detection
period. Providing the system power pin voltage does not fall
below POR level, register values will be retained while
RESET_B pin is maintained low.
A
precautionary measure: registers should be
reprogrammed to desired values anytime a system UVLO
fault is detected.
Other default slave addresses can be accommodated by
contacting an onsemi representative.
Reset
When the RESET_B pin is pulled LOW, the
INTERRUPTx and STATUSx bits will be cleared. All the
other registers will remain set to their programmed values,
2
but I C communication with the device is disabled.
Table 2. I2C SLAVE ADDRESS
Additionally, all internal fault counters will reset to 0.
C3, ADDR Pin Connected to
Address
7’h72
2
When the RESET_B pin is pulled HIGH, the I C block is
VSYS
Floating
Ground
turned on. The Reset_B pin should not be asserted high
2
while there is data transmission on the I C bus. This will
7’h61
ensure the FAN53840 doesn’t mis−interpret a logic low on
SDA as a falling edge and inadvertently create a “Start”
condition, and unintended data written to the FAN53840
registers. It is recommended that the FAN53840 is enabled
7’h20
Bus Timing
As shown in Figure 23, data is normally transferred when
SCL is LOW. Data is clocked in on the rising edge of SCL.
Typically, data transitions shortly at or after the falling edge
of SCL to allow ample time for the data to set up before the
next SCL rising edge.
2
when there is a brief break in I C data transmissions.
The SOFT_RESET bits in the RESET register can be used
to clear all registers to their default values.
No Fault Shutdown
When No Fault Shutdown feature is selected, LDOs are
prevented from shutting down during an OCP event but are
not prevented from shutting down due to a UVLO fault
event. When these events occur, the interrupt and status bits
will indicate a fault but the fault counter will not be
incremented.
Data change allowed
SDA
tH
This feature is activated by setting no_fault_shudown bit
in RESET register to “1”.
tSU
SCL
I2C Functionality
Figure 23. Data Transfer Timing
2
I C Interface
Each bus transaction begins and ends with SDA and SCL
HIGH. A transaction begins with a START condition, which
is defined as SDA transitioning from 1 to 0 with SCL HIGH,
as shown in Figure 24.
The FAN53840 serial interface is compatible with
Standard, Fast and Fast Plus Mode I C Bus specifications.
2
The SCL line is an input and its SDA line is a bi−directional
open−drain output; it can only pull down the bus when
active. The SDA line only pulls LOW during data reads and
when signaling ACK. All data is shifted in MSB (bit 7) first.
Please refer to the Reset section for guidance on
RESET_B LOW to HIGH pin timing for proper enabling of
2
the I C block.
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18
FAN53840, FAN53841
Read and Write Transactions
The figures below outline the sequences for data read and
write. Bus control is signified by the shading of the packet,
tHD;STA
Slave Address
MS Bit
SDA
SCL
Master Drives Bus
Slave Drives Bus
defined as
and
.
All addresses and data are MSB first.
Multi−Byte (Sequential) Read and Write Transactions
Figure 24. Start Bit
Sequential Write (Figure 29)
Transactions end with a STOP condition, which is SDA
transitioning from 0 to 1 with SCL HIGH, as shown in
Figure 25.
The Slave Address, Reg Addr address, and the first data
byte are transmitted to the FAN53840 in the same way as in
a single−byte write (Figure 27). However, instead of
generating a Stop condition, the master transmits additional
bytes that are written to consecutive sequential registers
after the falling edge of the eighth bit. After the last byte
written and its ACK bit received, the master issues a STOP
bit. The IC contains an 8−bit counter that increments the
address pointer after each byte is written.
Slave Releases
Master Drives
tSU;STO
ACK(0) or
NACK(1)
SDA
SCL
Sequential Read (Figure 30)
Sequential reads are initiated in the same way as
a single−byte read (Figure 28), except that once the slave
transmits the first data byte, the master issues an
acknowledge instead of a STOP condition. This directs the
slave’s I C logic to transmit the next sequentially addressed
8−bit word. The FAN53840 contains an 8−bit counter that
Figure 25. Stop Bit
During a read from the FAN53840, the master issues
a Repeated Start after sending the register address and
before resending the slave address. The Repeated Start is
a 1−to−0 transition on SDA while SCL is HIGH, as shown
in Figure 26.
2
increments the address pointer after each byte is read, which
2
allows the entire memory contents to be read during one I C
transaction.
t
SU;STA
Slave Release
t
HD;SDA
ACK(0) or
NACK(1)
SLAVE ADDR
MS Bit
SDA
SCL
t
VD;DAT
Figure 26. Repeated Start Timing
Figure 27. Single−Byte Write Transaction
Figure 28. Single−Byte Read Transaction
Figure 29. Multi−Byte (Sequential) Write Transaction
Figure 30. Multi−Byte (Sequential) Read Transaction
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19
FAN53840, FAN53841
REGISTER MAPPING TABLE
Table 3. REGISTER MAPPING
Read Only
Bit[4]
Write Only
Bit[3]
Read/Write
Bit[2]
Read/Clear
Bit[1]
Write/Clear
Bit[0]
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
Name
PRODUCT ID
SILICON REV ID
ENABLE
Bit[7]
Bit[6]
Bit[5]
Product ID
Revision
OUT4_DIS
UNUSED
OUT3_DIS
OUT2_DIS
OUT1_DIS
CHAN4_EN
CHAN3_EN
CHAN2_EN
CHAN1_EN
CHAN1
LDO1_VOUT
CHAN2
LDO2_VOUT
CHAN3
LDO3_VOUT
LDO4_VOUT
CHAN4
RESET
SOFT_RESET
LDO4_COMP_SEL LDO3_COMP_SEL
UNUSED UNUSED
UNUSED
OCP_TIMER
FLT_SD_B
LDO_COMP0
INTERRUPT1
LDO2_COMP_SEL
LDO1_COMP_SEL
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
TSD_INT
UNUSED
TSD_STAT
UNUSED
UNUSED
MASK_TSD
LDO4_OCP_ LDO3_OCP_ LDO2_OCP_ LDO1_OCP_
INT
INT
INT
INT
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
INTERRUPT2
STATUS1
STATUS2
STATUS3
MINT1
TSD_WRN_ VSYS_UVLO_
CHAN4_
UVLO_INT
CHAN3_
UVLO_INT
CHAN2_
UVLO_INT
CHAN1_
UVLO_INT
INT
INT
UNUSED
UNUSED
LDO4_OCP_ LDO3_OCP_ LDO2_OCP_ LDO1_OCP_
STAT
STAT
STAT
STAT
TSD_WRN_ VSYS_UVLO_
CHAN4_
CHAN3_
CHAN2_
CHAN1_
STAT
STAT
UVLO_STAT UVLO_STAT UVLO_STAT UVLO_STAT
UNUSED
CHIP_SUSD
CHAN4_
SUSD
CHAN3_
SUSD
CHAN2_
SUSD
CHAN1_
SUSD
UNUSED
UNUSED
MASK_
LDO4_OCP
MASK_
LDO3_OCP
MASK_
LDO2_OCP
MASK_
LDO1_OCP
MINT2
MASK_
TSD_WRN
MASK_
VSYS_UVLO
MASK_
CHAN4_
UVLO
MASK_
CHAN3_
UVLO
MASK_
CHAN2_
UVLO
MASK_
CHAN1_
UVLO
0x10
LDO_LS_
SELECT
UNUSED
UNUSED
UNUSED
UNUSED
LDO_LS4_
SELECT
LDO_LS3_
SELECT
LDO_LS2_
SELECT
LDO_LS1_
SELECT
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20
FAN53840, FAN53841
REGISTER DETAILS
Table 4. REGISTER DETAILS − 0x00 PRODUCT ID
0x00 PRODUCT ID
Default = 00000001
Description
Bit
Name
Product ID
Default
Type
7:0
00000001
Read
Allows Customers to Identify Manufacturer and Version
Product ID Table
Code
Product
−
00000000
00000001
00000010
00000011
00000100
00000101
00000110
00000111
00001000
00001001
00001010
00001011
00001100
00001101
00001110
00001111
FAN53840
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Table 5. REGISTER DETAILS − 0X01 SILICON REV ID
0x01 SILICON REV ID
Default = 00000000
Description
Bit
Name
Default
Type
7:0
Revision
00000000
Read
Provides the Silicon Revision
REG 84 [3:0]
INTERNAL
REVISION
REG 01 [7:0]
SILICON REV ID
Revision
00000000
00000001
00000010
00000011
00000100
0000
0001
0010
0011
0100
A_REVA
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21
FAN53840, FAN53841
Table 6. REGISTER DETAILS − 0X02 ENABLE
0x02 ENABLE
Default = 00000000
Description
Bit
Name
Default
Type
7
OUT4_DIS
OUT3_DIS
OUT2_DIS
OUT1_DIS
0
R/W
Code
Discharge Enabled/Disabled
0
OUT4 Active Discharge feature is
disabled. Pull down will not be
activated when OUT4 is disabled
by any event.
1
OUT4 Active Discharge feature is
enabled. See description of Active
Pulldowns in the Device Operation.
6
5
4
0
0
0
R/W
R/W
R/W
Code
Discharge Enabled/Disabled
0
OUT3 Active Discharge feature is
disabled. Pull down will not be
activated when LDO3 is disabled
by any event.
1
OUT3 Active Discharge feature is
enabled. See description of Active
Pulldowns in the Device Operation.
Code
Discharge Enabled/Disabled
0
OUT2 Active Discharge feature is
disabled. Pull down will not be
activated when LDO2 is disabled
by any event.
1
OUT2 Active Discharge feature is
enabled. See description of Active
Pulldowns in the Device Operation.
Code
Discharge Enabled/Disabled
0
OUT1 Active Discharge feature is
disabled. Pull down will not be
activated when LDO1 is disabled
by any event.
1
OUT1 Active Discharge feature is
enabled. See description of Active
Pulldowns in the Device Operation.
3
2
1
0
CHAN4_EN
CHAN3_EN
CHAN2_EN
CHAN1_EN
0
0
0
0
R/W
R/W
R/W
R/W
Enable bit for CHAN #4.
Code
Status of CHAN4
Disabled
0
1
Enabled
Enable bit for CHAN #3.
Code
Status of CHAN3
Disabled
0
1
Enabled
Enable bit for CHAN #2.
Code
Status of CHAN2
Disabled
0
1
Enabled
Enable bit for CHAN #1.
Code
Status of CHAN1
Disabled
0
1
Enabled
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22
FAN53840, FAN53841
Table 7. REGISTER DETAILS − 0X03 CHAN1
0x03 CHAN1
Default = 00000000
Description
Bit
7
Name
Default
0
Type
UNUSED
Read
6:0
LDO1_VOUT
0000000
R/W
When LDO_LS1_SELECT bit is set to “0”, these register bits sets LDO1
regulation target voltage.
Equation: Vout = 0.800 V + [(d − 35) * 8 mV];
Where d is the decimal value of the register.
The Default (0000000) points to the OTP programmed default value. If
this register is not reprogrammed, a read of the register will return 00h.
Hex
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
VOUT
Hex
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
VOUT
DEFAULT
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1.032 V
1.040 V
1.048 V
1.056 V
1.064 V
1.072 V
1.080 V
1.088 V
1.096 V
1.104 V
1.112 V
1.120 V
1.128 V
1.136 V
1.144 V
1.152 V
1.160 V
1.168 V
1.176 V
1.184 V
1.192 V
1.200 V
1.208 V
1.216 V
1.224 V
1.232 V
1.240 V
1.248 V
1.256 V
1.264 V
1.272 V
1.280 V
1.288 V
1.296 V
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
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23
FAN53840, FAN53841
Table 7. REGISTER DETAILS − 0X03 CHAN1 (continued)
0x03 CHAN1
Default = 00000000
Description
Bit
Name
LDO1_VOUT
Default
Type
6:0
0000000
R/W
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
Reserved
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
1.304 V
1.312 V
1.320 V
1.328 V
1.336 V
1.344 V
1.352 V
1.360 V
1.368 V
1.376 V
1.384 V
1.392 V
1.400 V
1.408 V
1.416 V
1.424 V
1.432 V
1.440 V
1.448 V
1.456 V
1.464 V
1.472 V
1.480 V
1.488 V
1.496 V
1.504 V
Reserved
Reserved
Reserved
Reserved
0.800 V
0.808 V
0.816 V
0.824 V
0.832 V
0.840 V
0.848 V
0.856 V
0.864 V
0.872 V
0.880 V
0.888 V
0.896 V
0.904 V
0.912 V
0.920 V
0.928 V
0.936 V
0.944 V
0.952 V
0.960 V
0.968 V
0.976 V
0.984 V
0.992 V
1.000 V
1.008 V
1.016 V
1.024 V
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24
FAN53840, FAN53841
Table 8. REGISTER DETAILS − 0X04 CHAN2
0x04 CHAN2
Default = 00000000
Description
Bit
Name
Default
Type
7:0
LDO2_VOUT
00000000
R/W
When LDO_LS2_SELECT bit is set to “0”, these register bits
sets LDO2 regulation target voltage.
Equation: Vout = 1.500 V + [(d − 16) * 8 mV];
where d is the decimal value of the register.
The Default (00h) points to the OTP programmed default value. If this
register is not reprogrammed, a read of the register will return 00h.
Hex
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
VOUT
DEFAULT
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1.500 V
Hex
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
VOUT
1.884 V
1.892 V
1.900 V
1.908 V
1.916 V
1.924 V
1.932 V
1.940 V
1.948 V
1.956 V
1.964 V
1.972 V
1.980 V
1.988 V
1.996 V
2.004 V
2.012 V
2.020 V
2.028 V
2.036 V
2.044 V
2.052 V
2.060 V
2.068 V
2.076 V
2.084 V
2.092 V
2.100 V
2.108 V
2.116 V
2.124 V
2.132 V
2.140 V
2.148 V
2.156 V
2.164 V
2.172 V
2.180 V
Hex
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
VOUT
Hex
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
VOUT
2.908 V
2.916 V
2.924 V
2.932 V
2.940 V
2.948 V
2.956 V
2.964 V
2.972 V
2.980 V
2.988 V
2.996 V
3.004 V
3.012 V
3.020 V
3.028 V
3.036 V
3.044 V
3.052 V
3.060 V
3.068 V
3.076 V
3.084 V
3.092 V
3.100 V
3.108 V
3.116 V
3.124 V
3.132 V
3.140 V
3.148 V
3.156 V
3.164 V
3.172 V
3.180 V
3.188 V
3.196 V
3.204 V
2.396 V
2.404 V
2.412 V
2.420 V
2.428 V
2.436 V
2.444 V
2.452 V
2.460 V
2.468 V
2.476 V
2.484 V
2.492 V
2.500 V
2.508 V
2.516 V
2.524 V
2.532 V
2.540 V
2.548 V
2.556 V
2.564 V
2.572 V
2.580 V
2.588 V
2.596 V
2.604 V
2.612 V
2.620 V
2.628 V
2.636 V
2.644 V
2.652 V
2.660 V
2.668 V
2.676 V
2.684 V
2.692 V
1.508 V
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
1.516 V
1.524 V
1.532 V
1.540 V
1.548 V
1.556 V
1.564 V
1.572 V
1.580 V
1.588 V
1.596 V
1.604 V
1.612 V
1.620 V
1.628 V
1.636 V
1.644 V
1.652 V
1.660 V
1.668 V
www.onsemi.com
25
FAN53840, FAN53841
Table 8. REGISTER DETAILS − 0X04 CHAN2 (continued)
0x04 CHAN2
Default
Default = 00000000
Description
Bit
Name
Type
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
1.676 V
1.684 V
1.692 V
1.700 V
1.708 V
1.716 V
1.724 V
1.732 V
1.740 V
1.748 V
1.756 V
1.764 V
1.772 V
1.780 V
1.788 V
1.796 V
1.804 V
1.812 V
1.820 V
1.828 V
1.836 V
1.844 V
1.852 V
1.860 V
1.868 V
1.876 V
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
2.188 V
2.196 V
2.204 V
2.212 V
2.220 V
2.228 V
2.236 V
2.244 V
2.252 V
2.260 V
2.268 V
2.276 V
2.284 V
2.292 V
2.300 V
2.308 V
2.316 V
2.324 V
2.332 V
2.340 V
2.348 V
2.356 V
2.364 V
2.372 V
2.380 V
2.388 V
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
2.700 V
2.708 V
2.716 V
2.724 V
2.732 V
2.740 V
2.748 V
2.756 V
2.764 V
2.772 V
2.780 V
2.788 V
2.796 V
2.804 V
2.812 V
2.820 V
2.828 V
2.836 V
2.844 V
2.852 V
2.860 V
2.868 V
2.876 V
2.884 V
2.892 V
2.900 V
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
3.212 V
3.220 V
3.228 V
3.236 V
3.244 V
3.252 V
3.260 V
3.268 V
3.276 V
3.284 V
3.292 V
3.300 V
3.308 V
3.316 V
3.324 V
3.332 V
3.340 V
3.348 V
3.356 V
3.364 V
3.372 V
3.380 V
3.388 V
3.396 V
3.404 V
3.412 V
www.onsemi.com
26
FAN53840, FAN53841
Table 9. REGISTER DETAILS − 0X05 CHAN3
0x05 CHAN3
Default = 00000000
Description
Bit
Name
Default
Type
7:0
LDO3_VOUT
00000000
R/W
When LDO_LS3_SELECT bit is set to “0”, these register bits sets
LDO3 regulation target voltage.
Equation: Vout = 1.500 V + [(d − 16) * 8 mV];
where d is the decimal value of the register.
The Default (00h) points to the OTP programmed default value. If this
register is not reprogrammed, a read of the register will return 00h.
Hex
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
VOUT
DEFAULT
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1.500 V
Hex
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
VOUT
1.884 V
1.892 V
1.900 V
1.908 V
1.916 V
1.924 V
1.932 V
1.940 V
1.948 V
1.956 V
1.964 V
1.972 V
1.980 V
1.988 V
1.996 V
2.004 V
2.012 V
2.020 V
2.028 V
2.036 V
2.044 V
2.052 V
2.060 V
2.068 V
2.076 V
2.084 V
2.092 V
2.100 V
2.108 V
2.116 V
2.124 V
2.132 V
2.140 V
2.148 V
2.156 V
2.164 V
2.172 V
2.180 V
Hex
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
VOUT
Hex
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
VOUT
2.908 V
2.916 V
2.924 V
2.932 V
2.940 V
2.948 V
2.956 V
2.964 V
2.972 V
2.980 V
2.988 V
2.996 V
3.004 V
3.012 V
3.020 V
3.028 V
3.036 V
3.044 V
3.052 V
3.060 V
3.068 V
3.076 V
3.084 V
3.092 V
3.100 V
3.108 V
3.116 V
3.124 V
3.132 V
3.140 V
3.148 V
3.156 V
3.164 V
3.172 V
3.180 V
3.188 V
3.196 V
3.204 V
2.396 V
2.404 V
2.412 V
2.420 V
2.428 V
2.436 V
2.444 V
2.452 V
2.460 V
2.468 V
2.476 V
2.484 V
2.492 V
2.500 V
2.508 V
2.516 V
2.524 V
2.532 V
2.540 V
2.548 V
2.556 V
2.564 V
2.572 V
2.580 V
2.588 V
2.596 V
2.604 V
2.612 V
2.620 V
2.628 V
2.636 V
2.644 V
2.652 V
2.660 V
2.668 V
2.676 V
2.684 V
2.692 V
1.508 V
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
1.516 V
1.524 V
1.532 V
1.540 V
1.548 V
1.556 V
1.564 V
1.572 V
1.580 V
1.588 V
1.596 V
1.604 V
1.612 V
1.620 V
1.628 V
1.636 V
1.644 V
1.652 V
1.660 V
1.668 V
www.onsemi.com
27
FAN53840, FAN53841
Table 9. REGISTER DETAILS − 0X05 CHAN3 (continued)
0x05 CHAN3
Default
Default = 00000000
Description
Bit
Name
Type
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
1.676 V
1.684 V
1.692 V
1.700 V
1.708 V
1.716 V
1.724 V
1.732 V
1.740 V
1.748 V
1.756 V
1.764 V
1.772 V
1.780 V
1.788 V
1.796 V
1.804 V
1.812 V
1.820 V
1.828 V
1.836 V
1.844 V
1.852 V
1.860 V
1.868 V
1.876 V
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
2.188 V
2.196 V
2.204 V
2.212 V
2.220 V
2.228 V
2.236 V
2.244 V
2.252 V
2.260 V
2.268 V
2.276 V
2.284 V
2.292 V
2.300 V
2.308 V
2.316 V
2.324 V
2.332 V
2.340 V
2.348 V
2.356 V
2.364 V
2.372 V
2.380 V
2.388 V
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
2.700 V
2.708 V
2.716 V
2.724 V
2.732 V
2.740 V
2.748 V
2.756 V
2.764 V
2.772 V
2.780 V
2.788 V
2.796 V
2.804 V
2.812 V
2.820 V
2.828 V
2.836 V
2.844 V
2.852 V
2.860 V
2.868 V
2.876 V
2.884 V
2.892 V
2.900 V
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
3.212 V
3.220 V
3.228 V
3.236 V
3.244 V
3.252 V
3.260 V
3.268 V
3.276 V
3.284 V
3.292 V
3.300 V
3.308 V
3.316 V
3.324 V
3.332 V
3.340 V
3.348 V
3.356 V
3.364 V
3.372 V
3.380 V
3.388 V
3.396 V
3.404 V
3.412 V
www.onsemi.com
28
FAN53840, FAN53841
Table 10. REGISTER DETAILS − 0X06 CHAN4
0x06 CHAN4
Default = 00000000
Description
Bit
Name
Default
Type
7:0
LDO4_VOUT
00000000
R/W
When LDO_LS4_SELECT bit is set to “0”, these register bits sets
LDO4 regulation target voltage.
Equation: Vout = 1.500 V + [(d − 16) * 8 mV],
where d is the decimal value of the register.
The Default (00h) points to the OTP programmed default value. If this
register is not reprogrammed, a read of the register will return 00h.
Hex
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
VOUT
DEFAULT
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1.500 V
Hex
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
VOUT
1.884 V
1.892 V
1.900 V
1.908 V
1.916 V
1.924 V
1.932 V
1.940 V
1.948 V
1.956 V
1.964 V
1.972 V
1.980 V
1.988 V
1.996 V
2.004 V
2.012 V
2.020 V
2.028 V
2.036 V
2.044 V
2.052 V
2.060 V
2.068 V
2.076 V
2.084 V
2.092 V
2.100 V
2.108 V
2.116 V
2.124 V
2.132 V
2.140 V
2.148 V
2.156 V
2.164 V
2.172 V
2.180 V
Hex
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
VOUT
Hex
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
VOUT
2.908 V
2.916 V
2.924 V
2.932 V
2.940 V
2.948 V
2.956 V
2.964 V
2.972 V
2.980 V
2.988 V
2.996 V
3.004 V
3.012 V
3.020 V
3.028 V
3.036 V
3.044 V
3.052 V
3.060 V
3.068 V
3.076 V
3.084 V
3.092 V
3.100 V
3.108 V
3.116 V
3.124 V
3.132 V
3.140 V
3.148 V
3.156 V
3.164 V
3.172 V
3.180 V
3.188 V
3.196 V
3.204 V
2.396 V
2.404 V
2.412 V
2.420 V
2.428 V
2.436 V
2.444 V
2.452 V
2.460 V
2.468 V
2.476 V
2.484 V
2.492 V
2.500 V
2.508 V
2.516 V
2.524 V
2.532 V
2.540 V
2.548 V
2.556 V
2.564 V
2.572 V
2.580 V
2.588 V
2.596 V
2.604 V
2.612 V
2.620 V
2.628 V
2.636 V
2.644 V
2.652 V
2.660 V
2.668 V
2.676 V
2.684 V
2.692 V
1.508 V
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
1.516 V
1.524 V
1.532 V
1.540 V
1.548 V
1.556 V
1.564 V
1.572 V
1.580 V
1.588 V
1.596 V
1.604 V
1.612 V
1.620 V
1.628 V
1.636 V
1.644 V
1.652 V
1.660 V
1.668 V
www.onsemi.com
29
FAN53840, FAN53841
Table 10. REGISTER DETAILS − 0X06 CHAN4 (continued)
0x06 CHAN4
Default
Default = 00000000
Description
Bit
Name
Type
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
1.676 V
1.684 V
1.692 V
1.700 V
1.708 V
1.716 V
1.724 V
1.732 V
1.740 V
1.748 V
1.756 V
1.764 V
1.772 V
1.780 V
1.788 V
1.796 V
1.804 V
1.812 V
1.820 V
1.828 V
1.836 V
1.844 V
1.852 V
1.860 V
1.868 V
1.876 V
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
2.188 V
2.196 V
2.204 V
2.212 V
2.220 V
2.228 V
2.236 V
2.244 V
2.252 V
2.260 V
2.268 V
2.276 V
2.284 V
2.292 V
2.300 V
2.308 V
2.316 V
2.324 V
2.332 V
2.340 V
2.348 V
2.356 V
2.364 V
2.372 V
2.380 V
2.388 V
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
2.700 V
2.708 V
2.716 V
2.724 V
2.732 V
2.740 V
2.748 V
2.756 V
2.764 V
2.772 V
2.780 V
2.788 V
2.796 V
2.804 V
2.812 V
2.820 V
2.828 V
2.836 V
2.844 V
2.852 V
2.860 V
2.868 V
2.876 V
2.884 V
2.892 V
2.900 V
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
3.212 V
3.220 V
3.228 V
3.236 V
3.244 V
3.252 V
3.260 V
3.268 V
3.276 V
3.284 V
3.292 V
3.300 V
3.308 V
3.316 V
3.324 V
3.332 V
3.340 V
3.348 V
3.356 V
3.364 V
3.372 V
3.380 V
3.388 V
3.396 V
3.404 V
3.412 V
www.onsemi.com
30
FAN53840, FAN53841
Table 11. REGISTER DETAILS − 0X07 RESET
0X07 RESET
Default = 00000110
Description
Bit
Name
Default
Type
7:4
SOFT_RESET
0000
Write
Code
Software Reset
1011
Writing a “1011” begins a soft reset of the device
2
I C registers to their default values. These bits
are cleared upon execution of the Reset function.
Any other value than “1011” will be ignored.
3
UNUSED
0
Read
R/W
2:1
OCP_TIMER
11
Option bits to control the length of the deglitch timer for current limit on
all LDOs before a fault is triggered.
Code
00
Deglitch Timer
125 ms
01
250 ms
10
500 ms
1 ms
11
0
FLT_SD_B
0
R/W
Code
0
Prevents Shutdown When a Fault Occurs
LDO is shutdown if a OCP event occurs or if the
LDO’s input VIN1, VIN2, VIN3, or VIN4 have
a UVLO event.
1
LDO is not shutdown if a OCP event occurs. If
the LDO’s input VIN1, VIN2, VIN3, or VIN4 have
a UVLO event, the associated LDO will be
shutdown until the supply returns, but the fault
will not be counted.
Note: If this bit function is desired, FLT_SD_B should be set to “1” prior
to enabling any LDOs after a Power−On−Reset.
www.onsemi.com
31
FAN53840, FAN53841
Table 12. REGISTER DETAILS − 0x08 LDO_COMP0
0x08 LDO_COMP0
Default = 00000001
Description
Bit
Name
LDO4_COMP_SEL
Default
Type
7:6
00
R/W
The LDO4 Compensation is selected by modifying these bits to account
for different COUT values.
The Cout_min and Cout_max values are nominal 0DCV bias
capacitance values utilized with the following DC de−rating:
Code
00
Cout_min
1.0 mF
4.7 mF
15 mF
Cout_max
< 4.7 mF
< 15 mF
< 47 mF
NA
01
10
11
NA
5:4
LDO3_COMP_SEL
00
R/W
The LDO3 Compensation is selected by modifying these bits to account
for different COUT value.
The Cout_min and Cout_max values are nominal 0DCV bias
capacitance values utilized with the following DC de−rating:
Code
00
Cout_min
1.0 mF
4.7 mF
15 mF
Cout_max
< 4.7 mF
< 15 mF
< 47 mF
NA
01
10
11
NA
3:2
LDO2_COMP_SEL
00
R/W
The LDO2 Compensation is selected by modifying these bits to
account for different COUT value.
Code
00
Cout_min
1.0 mF
4.7 mF
15 mF
Cout_max
< 4.7 mF
< 15 mF
< 47 mF
NA
01
10
11
NA
1:0
LDO1_COMP_SEL
01
R/W
The LDO1 Compensation is selected by modifying these bits to
account for different COUT value.
Code
00
Cout_min
Cout_max
< 5.5 mF
17 mF
−
01
5.5 mF
17 mF
−
10
34 mF
11
> 34 mF
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32
FAN53840, FAN53841
Table 13. REGISTER DETAILS − 0X09 INTERRUPT1
0X09 INTERRUPT1
Name Default
Default = 00000000
Description
Bit
7
Type
Read
Read
Read
Read
R/CLR
UNUSED
UNUSED
0
0
0
0
0
6
5
UNUSED
4
UNUSED
3
LDO4_OCP_INT
Code
LDO4 OCP Interrupt
0
1
Clear
Over−Current event detected on LDO4 output or
that a successful restart has occurred after an
OCP event.
2
1
0
LDO3_OCP_INT
LDO2_OCP_INT
LDO1_OCP_INT
0
0
0
R/CLR
R/CLR
R/CLR
Code
LDO3 OCP Interrupt
0
1
Clear
Over−Current event detected on LDO3 output or
that a successful restart has occurred after an
OCP event.
Code
LDO2 OCP Interrupt
0
1
Clear
Over−Current event detected on LDO2 output or
that a successful restart has occurred after an
OCP event.
Code
LDO1 OCP Interrupt
0
1
Clear
Over−Current event detected on LDO1 output or
that a successful restart has occurred after an
OCP event.
Table 14. REGISTER DETAILS − 0X0A INTERRUPT2
0X0A INTERRUPT2
Default = 00000000
Description
Bit
7
Name
Default
Type
Read
UNUSED
TSD_INT
0
0
6
R/CLR
Code
Thermal Shutdown Interrupt
0
Clear
A Thermal Shutdown event detected or that the
temperature has fallen below the hysteresis
level.
1
5
4
TSD_WRN_INT
0
0
R/CLR
R/CLR
Code
Thermal Warning Interrupt
0
Clear
Thermal Shutdown Warning threshold was
surpassed or that the temperature has fallen
below the hysteresis level.
1
VSYS_UVLO_INT
Code
VSYS Under−Voltage−Lock−Out Interrupt
0
Normal operation
Indicates that the VSYS power fell below the
UVLO input threshold or that the supplies have
risen above the rising thresholds after a UVLO
fault.
1
Reading the the associated status bit provides present state of the input
voltage.
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33
FAN53840, FAN53841
Table 14. REGISTER DETAILS − 0X0A INTERRUPT2 (continued)
0X0A INTERRUPT2
Name Default
Default = 00000000
Bit
Type
Description
3
CHAN4_UVLO_INT
CHAN3_UVLO_INT
CHAN2_UVLO_INT
CHAN1_UVLO_INT
0
0
0
0
R/CLR
Code
VIN4 Under−Voltage−Lock−Out Interrupt
Normal Operation
0
Indicates VIN4 fell below the UVLO threshold
while CHAN4 was enabled or that the supply
has risen above the rising thresholds after
a UVLO fault.
1
Reading the associated status bit provides
present state of the input voltage.
2
1
0
R/CLR
R/CLR
R/CLR
Code
VIN3 Under−Voltage−Lock−Out Interrupt
0
Normal Operation
Indicates VIN3 fell below the UVLO threshold
while CHAN3 was enabled or that the supply
has risen above the rising thresholds after
a UVLO fault.
1
Reading the associated status bit provides
present state of the input voltage.
Code
VIN2 Under−Voltage−Lock−Out Interrupt
0
Normal Operation
Indicates that the VIN2 fell below the UVLO
threshold while CHAN2 was enabled or that the
supply has risen above the rising thresholds
after a UVLO fault.
1
Reading the associated status bit provides
present state of the input voltage.
Code
VIN1 Under−Voltage−Lock−Out Interrupt
0
Normal operation
Indicates VIN1 fell below the UVLO threshold
while CHAN1 is enabled or that the supply has
risen above the rising thresholds after a UVLO
fault.
1
Reading the associated status bit provides
present state of the input voltage.
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34
FAN53840, FAN53841
Table 15. REGISTER DETAILS − 0X0B STATUS1
0X0B STATUS1
Default = 00000000
Description
Bit
7
Name
Default
Type
Read
Read
Read
Read
Read
UNUSED
UNUSED
0
0
0
0
0
6
5
UNUSED
4
UNUSED
3
LDO4_OCP_STAT
Code
LDO4 OCP Status
0
Clear
1
An Over−Current condition exists on LDO4 output
2
1
0
LDO3_OCP_STAT
LDO2_OCP_STAT
LDO1_OCP_STAT
0
0
0
Read
Read
Read
Code
LDO3 OCP Status
0
Clear
An Over−Current condition exists on LDO3 output
LDO2 OCP Status
1
Code
0
Clear
1
Code
0
An Over−Current condition exists on LDO2 output
LDO1 OCP Status
Clear
1
An Over−Current condition exists on LDO1 output
Table 16. REGISTER DETAILS − 0X0C STATUS2
0X0C STATUS2
Default = 00000000
Description
Bit
7
Name
Default
Type
Read
Read
UNUSED
TSD_STAT
0
0
6
Code
Temperature Shutdown Status
Normal Operation
0
1
Code
0
Device is in Thermal Shutdown
Temperature Warning Status
Normal Operation
5
TSD_WRN_STAT
0
Read
1
The temperature is above the thermal warning level
and shutdown is impending.
4
3
VSYS_UVLO_STAT
CHAN4_UVLO_STAT
0
0
Read
Read
Code
VSYS Under−Voltage−Lock−Out Status
Normal Operation
0
1
Code
0
VSYS is below the UVLO threshold.
VIN4 Under−Voltage−Lock−Out Status
Normal Operation
1
Indicates VIN4 is below the UVLO threshold while
LDO4 is enabled.
2
CHAN3_UVLO_STAT
0
Read
Code
VIN3 Under−Voltage−Lock−Out Status
0
1
Normal Operation
Indicates VIN3 is below the UVLO threshold while
LDO3 is enabled.
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35
FAN53840, FAN53841
Table 16. REGISTER DETAILS − 0X0C STATUS2 (continued)
0X0C STATUS2
Default = 00000000
Bit
Name
Default
Type
Description
1
CHAN2_UVLO_STAT
0
Read
Code
VIN2 Under−Voltage−Lock−Out Status
Normal Operation
0
1
Indicates VIN2 power rail is below the UVLO
threshold while LDO2 is enabled.
0
CHAN1_UVLO_STAT
0
Read
Code
VIN1 Under−Voltage−Lock−Out Status
0
1
Normal Operation
Indicates VIN1 is below the UVLO threshold while
LDO1 is enabled.
Table 17. REGISTER DETAILS − 0X0D STATUS3
0X0D STATUS3
Default = 00000000
Description
Bit
7
Name
UNUSED
UNUSED
UNUSED
CHIP_SUSD
Default
Type
Read
Read
Read
Read
0
0
0
0
6
5
4
Code
Chip Suspension
0
1
Chip normal state
The entire chip has been suspended due to a global
fault condition.
3
2
1
0
CHAN4_SUSD
CHAN3_SUSD
CHAN2_SUSD
CHAN1_SUSD
0
0
0
0
Read
Read
Read
Read
Code
CHAN4 Output Suspended
0
1
CHAN4 in normal state.
CHAN4 has been suspended due to a fault
condition.
Code
CHAN3 Output Suspended
0
1
CHAN3 in a normal state
CHAN3 has been suspended due to a fault
condition.
Code
CHAN2 Output Suspended
0
1
CHAN2 in normal state
CHAN2 has been suspended due to a fault
condition.
Code
CHAN1 Output Suspended
0
1
CHAN1 is in normal state
CHAN1 has been suspended due to a fault
condition.
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36
FAN53840, FAN53841
Table 18. REGISTER DETAILS − 0X0E MINT1
0X0E MINT1
Default = 00000000
Description
Bit
7
Name
UNUSED
Default
Type
Read
Read
Read
Read
0
0
0
0
0
6
UNUSED
5
UNUSED
4
UNUSED
3
MASK_LDO4_OCP
R/W
R/W
R/W
R/W
Code
LDO4 OCP MASK
0
1
No masking of interrupt.
INT(B) pin will not change states when LDO4
Over−Current interrupt occurs.
2
1
0
MASK_LDO3_OCP
MASK_LDO2_OCP
MASK_LDO1_OCP
0
0
0
Code
LDO3 OCP MASK
0
1
No masking of interrupt.
INT(B) pin will not change states when LDO3
Over−Current interrupt occurs.
Code
LDO2 OCP MASK
0
1
No masking of interrupt.
INT(B) pin will not change states when LDO2
Over−Current interrupt occurs.
Code
LDO1 OCP MASK
0
1
No masking of interrupt.
INT(B) pin will not change states when LDO1
Over−Current interrupt occurs.
Table 19. REGISTER DETAILS − 0X0F MINT2
0X0F MINT2
Default = 00000000
Description
Bit
7
Name
Default
Type
Read
R/W
UNUSED
MASK_TSD
0
0
6
Code
Thermal Shutdown MASK
0
1
No masking of interrupt.
INT(B) pin will not change states when a Thermal
Shutdown interrupt occurs.
5
4
3
MASK_TSD_WRN
MASK_VSYS_UVLO
MASK_CHAN4_UVLO
0
0
0
R/W
R/W
R/W
Code
Thermal Warning MASK
0
1
No masking of interrupt.
INT(B) pin will not change states when LDO7
Over−Current interrupt occurs.
Code
VSYS UVLO MASK
0
1
No masking of interrupt.
INT(B) pin will not change states when VSYS Input
Power Under Voltage interrupt occurs.
Code
VIN4 UVLO MASK
0
1
No masking of interrupt.
INT(B) pin will not change states when VIN4 Input
Power Under Voltage interrupt occurs
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37
FAN53840, FAN53841
Table 19. REGISTER DETAILS − 0X0F MINT2 (continued)
0X0F MINT2
Name
Default = 00000000
Description
Bit
Default
Type
2
MASK_CHAN3_UVLO
MASK_CHAN2_UVLO
MASK_CHAN1_UVLO
0
R/W
Code
VIN3 UVLO MASK
0
1
No masking of interrupt.
INT(B) pin will not change states when VIN3 Input
Power Under Voltage interrupt occurs.
1
0
0
0
R/W
R/W
Code
VIN2 UVLO MASK
0
1
No masking of interrupt.
INT(B) pin will not change states when VIN2 Input
Power Under Voltage interrupt occurs.
Code
VIN1 UVLO MASK
0
1
No masking of interrupt.
INT(B) pin will not change states when VIN1 Input
Power Under Voltage interrupt occurs.
Table 20. REGISTER DETAILS − 0X10 LDO_LS_SELECT
0X10 LDO_LS_SELECT
Default = 00000000
Description
Bit
7
Name
UNUSED
Default
Type
Read
Read
Read
Read
R/W
0
0
0
0
0
6
UNUSED
5
UNUSED
4
UNUSED
3
LDO_LS4_SELECT
Configuration of Output 4
Code
Configuration
0
1
Configured to operate as an LDO
Configured to operate as a Load Switch
Configuration of Output 3
2
1
0
LDO_LS3_SELECT
LDO_LS2_SELECT
LDO_LS1_SELECT
0
0
0
R/W
R/W
R/W
Code
Configuration
0
1
Configured to operate as an LDO
Configured to operate as a Load Switch
Configuration of Output 2
Code
Configuration
0
1
Configured to operate as an LDO
Configured to operate as a Load Switch
Configuration of Output 1
Code
Configuration
0
1
Configured to operate as an LDO
Configured to operate as a Load Switch
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38
FAN53840, FAN53841
APPLICATION GUIDELINES
LDO Input Capacitor Considerations
FAN53840, to ensure optimum performance and stability,
specify the amount of capacitance each LDO output will
have with an onsemi representative.
Use only X5R and X7R ceramic capacitors with adequate
voltage rating for the output capacitors.
If long wires are used to bring power to an evaluation
board, additional “bulk” capacitance should be placed on the
evaluation board between the local input capacitor(s)and the
power source lead(s) to reduce ringing caused by inductance
lead length. Use only X5R and X7R ceramic capacitorswith
adequate voltage rating for local input capacitors.
The effective capacitance value decreases as the voltage
across the capacitor increases due to DC bias effects. Adding
additional capacitance to the minimum recommended
ensures reliable operation.
PCB Layout Recommendations
Local input and output capacitors should be placed close
to the corresponding input and output pins. The ground
terminal of the capacitors should be connected to a good
ground plane − preferably on the surface of the board. Input
power should be routed to the input capacitor first, then to
the input pin(s) of the IC. Power from layers other than the
layer on which a capacitor sits, should be routed to the
capacitor layer with vias close to the positive terminal of the
capacitor. Power traces from outputs should be routed to the
output capacitor first, then to other layers if necessary.
LDO Output Capacitor Considerations
FAN53840 LDOs are initially set at the factory for a range
of 4.7 mF to 10 mF (unbiased) on LDO1. LDO2/3/4 are
initially set for a range of 1 mF to 4.7 mF (unbiased). All
LDOs can be trimmed at the factory for up to 47 mF total
(unbiased) capacitance. When evaluating and ordering the
OUT4
A1
VIN4
A2
VIN3
A3
OUT3
A4
OUT1
B1
SCL
B2
SDA
B3
RESET_B
B4
VIN1
C1
INT_B
C2
ADDR
C3
VIN2
C4
DGND
D1
VSYS
D2
AGND
D3
OUT2
D4
Figure 31. Recommended PCB Assembly (Top View)
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39
FAN53840, FAN53841
Figure 32. Recommended PCB Layout
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40
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WLCSP16 1.52x1.52x0.432
CASE 567ZM
ISSUE O
DATE 14 SEP 2020
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Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON22197H
WLCSP16 1.52x1.52x0.432
PAGE 1 OF 1
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