FDMA1023PZ [ONSEMI]
双 P 沟道，Power Trench® MOSFET，-20V，-3.7A，72mΩ;
| 型号： | FDMA1023PZ |
| 厂家： | 
ONSEMI |
| 描述： | 双 P 沟道，Power Trench® MOSFET，-20V，-3.7A，72mΩ 开关 光电二极管 晶体管 |
| 文件： | 总7页 (文件大小：228K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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MOSFET – Dual, P-Channel,
POWERTRENCH)
V
R
MAX
I MAX
D
DS
DS(on)
−20 V
72 mꢀ @ −4.5 V
−3.7 A
95 mꢀ @ −2.5 V
130 mꢀ @ −1.8 V
195 mꢀ @ −1.5 V
-20 V, -3.7 A, 72 mW
FDMA1023PZ
General Description
Pin 1
D1
S1
G1
This device is designed specifically as a single package solution
for the battery charge switch in cellular handset and other
ultra−portable applications. It features two independent P−Channel
MOSFETs with low on−state resistance for minimum conduction
losses. When connected in the typical common source configuration,
bi−directional current flow is possible.
The MicroFET 2x2 package offers exceptional thermal
performance for its physical size and is well suited to linear mode
applications.
D2
D2
D1
G2
S2
WDFN6 2x2, 0.65P
(MicroFET 2x2)
CASE 511DA
MARKING DIAGRAM
Features
• Max R
• Max R
• Max R
• Max R
= 72 mꢀ at V = −4.5 V, I = −3.7 A
GS D
DS(on)
DS(on)
DS(on)
DS(on)
&Z&2&K
023
= 95 mꢀ at V = −2.5 V, I = −3.2 A
GS
D
= 130 mꢀ at V = −1.8 V, I = −2.0 A
GS
D
= 195 mꢀ at V = −1.5 V, I = −1.0 A
GS
D
• Low Profile − 0.8 mm Maximum − In the New Package MicroFET
2x2 mm
&Z = Assembly Plant Code
&2 = 2−Digit Date Code
&K = 2−Digits Lot Run Traceability Code
023 = Device Code
• HBM ESD Protection Level > 2 kV (Note 3)
• Free from Halogenated Compounds and Antimony Oxides
• This Device is Pb−Free, Halide Free and is RoHS Compliant
PIN CONNECTIONS
ABSOLUTE MAXIMUM RATINGS (T = 25°C unless otherwise noted)
A
Symbol
Parameter
Drain to Source Voltage
Gate to Source Voltage
Ratings
Unit
V
D1
1
2
3
S1
G1
D2
6
5
4
V
DS
V
GS
−20
8
V
G2
S2
I
D
Drain Current
−Continuous (Note 1a)
−Pulsed
A
−3.7
−6
P
D
Power Dissipation
(Note 1a)
(Note 1b)
W
1.5
0.7
T , T
Operating and Storage Junction
Temperature Range
–55 to
+150
°C
J
STG
ORDERING INFORMATION
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
†
Shipping
Device
Package
FDMA1023PZ
WDFN6
(Pb−Free,
Halide Free)
3000 /
Tape & Reel
For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
April, 2023 − Rev. 4
FDMA1023PZ/D
FDMA1023PZ
THERMAL CHARACTERISTICS
Symbol
Parameter
Ratings
86
Unit
Thermal Resistance for Single Operation, Junction to Ambient (Note 1a)
Thermal Resistance for Single Operation, Junction to Ambient (Note 1b)
Thermal Resistance for Dual Operation, Junction to Ambient (Note 1c)
Thermal Resistance for Dual Operation, Junction to Ambient (Note 1d)
°C/W
R
R
R
R
ꢁ
ꢁ
ꢁ
ꢁ
JA
JA
JA
JA
173
69
151
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
OFF CHARACTERISTICS
BV
Drain−Source Breakdown Voltage
I
I
= −250 ꢂ A, V = 0 V
−20
−
−
−
V
DSS
D
GS
Breakdown Voltage Temperature
Coefficient
= −250 ꢂ A, referenced to 25°C
−
−11
mV/°C
ꢃ BVDSS
ꢃ TJ
D
I
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
V
V
= −16 V, V = 0 V
−
−
−
−
−1
ꢂ A
ꢂ A
DSS
GSS
DS
GS
I
=
8 V, V = 0 V
10
GS
DS
ON CHARACTERISTICS
V
Gate to Source Threshold Voltage
I
I
= −250 ꢂ A, V = V
DS
−0.4
−0.7
−1.0
V
GS(th)
D
GS
Gate to Source Threshold Voltage
Temperature Coefficient
= −250 ꢂ A, referenced to 25°C
−
2.5
−
mV/°C
ꢃ VGS(th)
ꢃ TJ
D
R
Static Drain to Source
V
V
V
V
V
= −4.5 V, I = −3.7 A
−
−
−
−
−
−
60
75
72
95
mꢀ
DS(on)
GS
GS
GS
GS
GS
D
On−Resistance
= −2.5 V, I = −3.2 A
D
= −1.8 V, I = −2.0 A
100
130
81
130
195
91
D
= −1.5 V, I = −1.0 A
D
= −4.5 V, I = −3.7 A, T = 125°C
D
J
g
FS
Forward Transconductance
I
D
= −3.7 A, V = −5 V
12
−
S
DS
DYNAMIC CHARACTERISTICS
C
Input Capacitance
V
DS
= −10 V, V = 0 V, f = 1 MHz
−
−
−
490
100
90
655
135
135
pF
pF
pF
iss
GS
C
Output Capacitance
oss
C
Reverse Transfer Capacitance
rss
SWITCHING CHARACTERISTICS
t
t
Turn−On Delay Time
Rise Time
V
V
= −10 V, I = −1 A
−
−
−
−
−
−
−
9
18
22
103
60
12
−
ns
ns
d(on)
DD
GS
D
= −4.5 V, R
= 6 ꢀ
GEN
t
r
12
64
37
8.6
0.7
2.0
Turn−Off Delay Time
Fall Time
ns
d(off)
t
f
ns
Q
Total Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
V
DD
V
GS
= −10 V, I = −3.7 A,
nC
nC
nC
g(TOT)
D
= −4.5 V
Q
Q
gs
gd
−
SWITCHING CHARACTERISTICS
Maximum Continuous Source−Drain Diode Forward Current
I
S
−
−
−
−
−
−0.8
32
−1.1
−1.2
48
A
V
V
Source to Drain Diode Forward Voltage
Reverse Recovery Time
V
= 0 V, I = −1.1 A (Note 2)
SD
GS S
t
I = −3.7 A, di/dt = 100 A/ꢂ s
F
ns
nC
rr
Q
Reverse Recovery Charge
15
23
rr
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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2
FDMA1023PZ
NOTES:
1. R
2
is determined with the device mounted on a 1 in oz. copper pad on a 1.5 x 1.5 in. board of FR−4 material. R
is guaranteed by design
ꢁ
ꢁ
JC
JA
while R
is determined by the user’s board design.
ꢁ
JA
JA
JA
JA
JA
2
a. R
b. R
c. R
d. R
= 86°C/W when mounted on a 1 in pad of 2 oz copper, 1.5” x 1.5” x 0.062” thick PCB. For single operation.
ꢁ
ꢁ
ꢁ
ꢁ
= 173°C/W when mounted on a minimum pad of 2 oz copper. For single operation.
2
= 69°C/W when mounted on a 1 in pad of 2 oz copper, 1.5” x 1.5” x 0.062” thick PCB. For dual operation.
= 151°C/W when mounted on a minimum pad of 2 oz copper. For dual operation.
a. 86°C/W when mounted on
b. 173°C/W when mounted on
2
a 1 in pad of 2 oz copper.
a minimum pad of 2 oz copper.
c. 69°C/W when mounted on
d. 151°C/W when mounted on
2
a 1 in pad of 2 oz copper.
a minimum pad of 2 oz copper.
2. Pulse Test: Pulse Width < 300 ꢂ s, Duty Cycle < 2.0%
3. The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied.
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3
FDMA1023PZ
TYPICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
2.6
6
5
V
V
= −1.8 V
= −4.5 V
= −3.0 V
= −2.5 V
GS
GS
V
GS
= −1.5 V
2.2
1.8
1.4
V
V
V
GS
GS
V
GS
= −1.8 V
V
GS
= −3.0 V
4
3
2
1
0
= −2.0 V
GS
V
= −2.0 V
= −2.5 V
GS
GS
V
= −1.5 V
GS
V
1.0
0.6
V
GS
= −4.5 V
PULSE DURATION = 300 ꢂ s
DUTY CYCLE = 2.0% MAX
PULSE DURATION = 300 ꢂ s
DUTY CYCLE = 2.0% MAX
0
1
0
0.5
1.0
1.5
2.0
2
3
4
5
6
−V , Drain to Source Voltage (V)
DS
−I , Drain Current (A)
D
Figure 2. Normalized On−Resistance vs. Drain
Figure 1. On−Region Characteristics
Current and Gate Voltage
200
1.6
1.4
1.2
1.0
0.8
0.6
PULSE DURATION = 300 ꢂ s
DUTY CYCLE = 2.0% MAX
I
V
= −3.7 A
D
= −4.5 V
GS
160
120
80
I
D
= −1.85 A
T = 125°C
J
T = 25°C
J
40
0
−50 −25
0
25
50
75
100 125 150
5
6
1
2
3
4
−V , Gate to Source Voltage (V)
GS
T , Junction Temperature (5C)
J
Figure 3. Normalized On−Resistance vs. Junction
Figure 4. On−Resistance vs. Gate to Source
Temperature
Voltage
10
1
6
PULSE DURATION = 300 ꢂ s
DUTY CYCLE = 2.0% MAX
V
GS
= 0 V
5
V
DD
= −5 V
T = 125°C
J
4
3
0.1
T = 25°C
J
T = 125°C
0.01
1E−3
1E−4
J
2
1
0
T = −55°C
J
T = 25°C
J
T = −55°C
J
0.5
0.0
1.0
1.5
2.0
0.2
0.0
0.4
0.6
0.8
1.0
1.2
1.4
−V , Gate to Source Voltage (V)
GS
−V , Body Diode Forward Voltage (V)
SD
Figure 5. Transfer Characteristics
Figure 6. Source to Drain Diode Forward Voltage
vs. Source Current
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4
FDMA1023PZ
TYPICAL CHARACTERISTICS (T = 25°C unless otherwise noted) (continued)
J
5
4
3
2
1000
I
D
= −3.7 A
V
DD
= −5 V
C
iss
V
= −10 V
DD
C
C
oss
V
= −15 V
DD
100
40
1
rss
f = 1 MHz
= 0 V
V
GS
0
0
2
4
6
8
10
0.1
10
−V , Drain to Source Voltage (V)
20
1
Q , Gate Charge (nC)
g
DS
Figure 8. Capacitance Characteristics
Figure 7. Gate Charge Characteristics
100
10
20
10
V
= −10 V
GS
T = 25°C
A
R
DS(on) LIMIT
FOR TEMPERATURES
100 ꢂ s
ABOVE 25°C DERATE PEAK
CURRENT AS FOLLOWS:
1 ms
150
* TA
1
0.1
Ǹ
ƪ ƫ
I + I25ꢀ
125
10 ms
100 ms
1 s
10 s
DC
V
= −4.5 V
GS
SINGLE PULSE
= 173°C/W
SINGLE PULSE
= 173°C/W
R
ꢁ
JA
1
R
ꢁ
JA
T = 25°C
A
T = 25°C
A
SINGLE PULSE
0.01
0.5
10
−4
−3
−2
−1
0
1
2
3
0.1
1
10
60
10
10
10
10
10
10
10
−V , Drain to Source Voltage (V)
DS
t, Pulse Width (s)
Figure 9. Forward Bias Safe Operating Area
Figure 10. Single Pulse Maximum Power
Dissipation
2
DUTY CYCLE−DESCENDING ORDER
1
D = 0.5
0.2
0.1
0.05
P(pk)
0.1
0.02
0.01
t
1
t
2
NOTES:
DUTY FACTOR: D = t / t
1
2
SINGLE PULSE
0.01
PEAK T = P
× Z
× R
+ T
JA A
ꢁ
ꢁ
J
DM
JA
0.005
−4
−3
−2
−1
0
1
2
3
10
10
10
10
10
10
10
10
t, Rectangular Pulse Duration (s)
Figure 11. Transient Thermal Response Curve
POWERTRENCH is registered trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United
States and/or other countries.
MicroFET is trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other
countries.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFN6 2x2, 0.65P
CASE 511DA
ISSUE O
DATE 31 JUL 2016
0.05
C
2.0
A
2X
B
1.80
1.72
2.0
0.80(2X)
1.00(2X)
0.21
1.41
0.05
C
2.25
TOP VIEW
2X
0.42(6X)
PIN#1 IDENT
0.42(6X)
(0.10)
0.65
0.75 0.05
RECOMMENDED
LAND PATTERN
0.10
C
0.20 0.05
C
0.08
C
0.025 0.025
SEATING
PLANE
SIDE VIEW
NOTES:
A. CONFORM TO JADEC REGISTRATIONS MO−229,
VARIATION VCCC, EXCEPT WHERE NOTED.
2.00 0.05
1.64 0.05
B. DIMENSIONS ARE IN MILLIMETERS.
0.645 0.05
0.350
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 2009.
PIN#1 IDENT
(0.185)4X
D. LAND PATTERN RECOMMENDATION IS
EXISTING INDUSTRY LAND PATTERN.
1
3
0.275 0.05
(6X)
F. NON−JEDEC DUAL DAP
0.86 0.05
2.00 0.05
(0.57)
F
6
4
0.33 0.05
(6X)
0.65
0.10
0.05
C A B
1.30
C
BOTTOM VIEW
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13615G
WDFN6 2X2, 0.65P
PAGE 1 OF 1
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, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
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