FDML7610S [ONSEMI]
30 V非对称双N沟道MOSFET PowerTrench®功率级;
| 型号： | FDML7610S |
| 厂家： | 
ONSEMI |
| 描述： | 30 V非对称双N沟道MOSFET PowerTrench®功率级 开关 脉冲 光电二极管 晶体管 |
| 文件： | 总16页 (文件大小：661K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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April 2013
FDML7610S
PowerTrench® Power Stage
Asymmetric Dual N-Channel MOSFET
Features
General Description
Q1: N-Channel
This device includes two specialized N-Channel MOSFETs in a
dual MLP package.The switch node has been internally
connected to enable easy placement and routing of synchronous
buck converters. The control MOSFET (Q1) and synchronous
SyncFETTM (Q2) have been designed to provide optimal power
efficiency.
Max rDS(on) = 7.5 mΩ at VGS = 10 V, ID = 12 A
Max rDS(on) = 12 mΩ at VGS = 4.5 V, ID = 10 A
Q2: N-Channel
Max rDS(on) = 4.2 mΩ at VGS = 10 V, ID = 17 A
Max rDS(on) = 5.5 mΩ at VGS = 4.5 V, ID = 14 A
Applications
RoHS Compliant
Computing
Communications
General Purpose Point of Load
Notebook VCORE
D1
D1
D1
Pin 1
G1
Q2
D1
D1
S2
5
6
7
8
4
3
2
1
PHASE
(S1/D2)
PHASE
D1
D1
S2
S2
G2
S2
S2
S2
G1
Q1
G2
Top
Bottom
MLP 3X4.5
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
VGS
Parameter
Q1
30
Q2
Units
Drain to Source Voltage
Gate to Source Voltage
30
±20
28
V
V
(Note 3)
TC = 25 °C
TC = 25 °C
TA = 25 °C
±20
30
Drain Current
-Continuous (Package limited)
-Continuous (Silicon limited)
-Continuous
40
121a
60
171b
ID
A
-Pulsed
40
40
Power Dissipation for Single Operation
TA = 25 °C
TA = 25 °C
2.11a
0.81c
2.21b
0.91d
PD
W
TJ, TSTG
Operating and Storage Junction Temperature Range
-55 to +150
°C
Thermal Characteristics
RθJA
RθJA
RθJC
Thermal Resistance, Junction to Ambient
601a
1501c
561b
1401d
3.5
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Case
°C/W
4
Package Marking and Ordering Information
Device Marking
Device
Package
Reel Size
13 ”
Tape Width
Quantity
FDML7610S
FDML7610S
MLP3X4.5
12 mm
3000 units
1
©2013 Fairchild Semiconductor Corporation
FDML7610S Rev.C1
www.fairchildsemi.com
Electrical Characteristics TJ = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Type
Min
Typ
Max
Units
Off Characteristics
ID = 250 μA, VGS = 0 V
ID = 1 mA, VGS = 0 V
Q1
Q2
30
30
BVDSS
Drain to Source Breakdown Voltage
V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
ID = 250 μA, referenced to 25 °C
Q1
Q2
15
14
mV/°C
I
D = 10 mA, referenced to 25 °C
Q1
Q2
1
500
μA
μA
IDSS
IGSS
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
VDS = 24 V, VGS = 0 V
VGS = 20 V, VDS= 0 V
Q1
Q2
100
100
nA
nA
On Characteristics
V
GS = VDS, ID = 250 μA
Q1
Q2
1
1
1.8
1.8
3
3
VGS(th)
Gate to Source Threshold Voltage
V
VGS = VDS, ID = 1 mA
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID = 250 μA, referenced to 25 °C
ID = 10 mA, referenced to 25 °C
Q1
Q2
-6
-5
mV/°C
V
V
GS = 10 V, ID = 12 A
GS = 4.5 V, ID = 10 A
6.0
8.5
8.3
7.5
12
12
Q1
Q2
VGS = 10 V, ID = 12 A , TJ = 125 °C
rDS(on)
Drain to Source On Resistance
mΩ
VGS = 10 V, ID = 17 A
VGS = 4.5 V, ID = 14 A
VGS = 10 V, ID = 17 A , TJ = 125 °C
3.2
4.1
4.1
4.2
5.5
6
VDS = 5 V, ID = 12 A
Q1
Q2
63
86
gFS
Forward Transconductance
S
V
DS = 5 V, ID = 17 A
Dynamic Characteristics
Q1
Q2
1315
2960
1750
3940
Q1:
Ciss
Coss
Crss
Rg
Input Capacitance
pF
pF
pF
Ω
VDS = 15 V, VGS = 0 V, f = 1 MHZ
Q1
Q2
455
1135
600
1510
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
Q2:
VDS = 15 V, VGS = 0 V, f = 1 MHZ
Q1
Q2
45
100
70
150
Q1
Q2
0.9
0.6
Switching Characteristics
Q1
Q2
8.6
13
18
23
td(on)
tr
Turn-On Delay Time
Rise Time
ns
ns
ns
Q1:
VDD = 15 V, ID = 12 A,
Q1
Q2
2.5
4
10
10
V
GS = 10 V, RGEN = 6 Ω
Q1
Q2
20
31
32
49
td(off)
Turn-Off Delay Time
Q2:
V
DD = 15 V, ID = 17 A,
Q1
Q2
2.3
3.1
10
10
VGS = 10 V, RGEN = 6 Ω
tf
Fall Time
ns
Q1
Q2
20
43
28
60
Qg
Total Gate Charge
VGS = 0 V to 10 V
Q1
nC
nC
nC
nC
VDD = 15 V,
Q1
Q2
9.3
20
13
28
Qg
Total Gate Charge
VGS = 0 V to 4.5 V
I
D = 12 A
Q1
Q2
4.3
8.9
Q2
VDD = 15 V,
ID = 17A
Qgs
Qgd
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
Q1
Q2
2.2
4.7
©2013 Fairchild Semiconductor Corporation
FDML7610S Rev.C1
www.fairchildsemi.com
2
Electrical Characteristics TJ = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Type
Min
Typ
Max
Units
Drain-Source Diode Characteristics
V
V
GS = 0 V, IS = 12 A
GS = 0 V, IS = 17 A
(Note 2) Q1
(Note 2) Q2
0.8
0.8
1.2
1.2
VSD
trr
Source to Drain Diode Forward Voltage
Reverse Recovery Time
V
Q1
Q2
27
35
43
56
Q1
ns
nC
IF = 12 A, di/dt = 100 A/μs
Q2
IF = 17 A, di/dt = 300 A/μs
Q1
Q2
10
40
18
64
Qrr
Reverse Recovery Charge
Notes:
2
1:
R
is determined with the device mounted on a 1 in pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
is guaranteed by design while R is determined
θCA
θJA
θJC
by the user's board design.
b. 56 °C/W when mounted on
a 1 in pad of 2 oz copper
a. 60 °C/W when mounted on
a 1 in pad of 2 oz copper
2
2
c. 150 °C/W when mounted on a
minimum pad of 2 oz copper
d. 140 °C/W when mounted on a
minimum pad of 2 oz copper
2: Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.
3: As an N-ch device, the negative Vgs rating is for low duty cycle pulse ocurrence only. No continuous rating is implied.
©2013 Fairchild Semiconductor Corporation
FDML7610S Rev.C1
www.fairchildsemi.com
3
Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
40
30
20
10
0
4
3
2
1
0
VGS = 10 V
= 6 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
V
GS
VGS = 4.5 V
VGS = 4 V
VGS = 3.5 V
VGS = 4 V
VGS = 4.5 V
VGS = 3.5 V
0.5
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 6 V
VGS = 10 V
0.0
1.0
1.5
2.0
0
10
20
30
40
VDS, DRAIN TO SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
Figure 1. On Region Characteristics
F i g u r e 2 . No rma li zed O n-Re si stan ce
vs Drain Current and Gate Voltage
40
1.6
1.4
1.2
1.0
0.8
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
ID = 12 A
VGS = 10 V
30
ID = 12 A
20
TJ = 125 oC
10
TJ = 25 o
C
0
2
4
6
8
10
-75 -50 -25
0
25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 3. Normalized On Resistance
vs Junction Temperature
Figure4. On-Resistance vs Gate to
Source Voltage
40
40
VGS = 0 V
PULSE DURATION = 80 μs
10
DUTY CYCLE = 0.5% MAX
30
20
10
0
VDS = 5 V
1
TJ = 150 o
C
TJ = 150 o
C
TJ = 25 oC
0.1
TJ = 25 o
C
0.01
0.001
TJ = -55 o
C
TJ = -55 o
C
1.5
2.0
2.5
3.0
3.5
4.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
VGS, GATE TO SOURCE VOLTAGE (V)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
Figure6. Source to Drain Diode
Forward Voltage vs Source Current
©2013 Fairchild Semiconductor Corporation
FDML7610S Rev.C1
www.fairchildsemi.com
4
Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
10
2000
1000
ID = 12 A
Ciss
8
VDD = 10 V
Coss
6
VDD = 15 V
100
4
VDD = 20 V
2
Crss
f = 1 MHz
= 0 V
V
GS
0
10
0.1
1
10
30
0
5
10
Q , GATE CHARGE (nC)
15
20
VDS, DRAIN TO SOURCE VOLTAGE (V)
g
Figure 7. Gate Charge Characteristics
Figure8. C a p a c i t a n c e v s D r a i n
to Source Voltage
60
100
10
RθJC = 4 oC/W
VGS = 10 V
100us
1 ms
40
20
0
VGS = 4.5 V
10 ms
1
THIS AREA IS
LIMITED BY r
100 ms
DS(on)
Limited by Package
SINGLE PULSE
TJ = MAX RATED
1s
0.1
10s
DC
R
θJA = 150 oC/W
TA = 25 oC
0.01
0.01
25
50
75
100
125
150
0.1
1
10
100
200
TC, CASE TEMPERATURE (oC)
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 9. Maximum Continuous Drain Current vs
Case Temperature
Figure 10. Forward Bias Safe Operating Area
1000
100
10
SINGLE PULSE
R
θJA = 150 oC/W
TA = 25 o
C
1
0.5
10-4
10-3
10-2
10-1
1
10
100
1000
t, PULSE WIDTH (s)
Figure 11. Single Pulse Maximum Power Dissipation
©2013 Fairchild Semiconductor Corporation
FDML7610S Rev.C1
www.fairchildsemi.com
5
Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
0.1
0.05
0.02
0.1
P
DM
0.01
t
1
0.01
t
SINGLE PULSE
θJA = 150 oC/W
(Note 1c)
2
NOTES:
DUTY FACTOR: D = t /t
R
1
2
PEAK T = P
x Z
x R
+ T
J
DM
θJA
θJA A
0.001
10-4
10-3
10-2
10-1
t, RECTANGULAR PULSE DURATION (sec)
1
10
100
1000
Figure 12. Junction-to-Ambient Transient Thermal Response Curve
©2013 Fairchild Semiconductor Corporation
FDML7610S Rev.C1
www.fairchildsemi.com
6
Typical Characteristics (Q2 N-Channel) TJ = 25 oC unlenss otherwise noted
40
30
20
10
0
6
5
4
3
2
1
0
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 10 V
VGS = 4.5 V
VGS = 3 V
VGS = 4 V
VGS = 3.5 V
VGS = 3.5 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 3 V
0.2
VGS = 4 V
VGS = 10 V
30 40
VGS = 4.5 V
0.0
0.4
0.6
0.8
0
10
20
VDS, DRAIN TO SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
Figure 13. On-Region Characteristics
Figure 14. Normalized on-Resistance vs Drain
Current and Gate Voltage
1.6
20
ID = 17 A
GS = 10 V
PULSE DURATION = 80 μs
ID = 17 A
V
DUTY CYCLE = 0.5% MAX
1.4
1.2
1.0
0.8
0.6
15
10
TJ = 125 oC
5
TJ = 25 o
C
0
-75 -50 -25
0
25 50 75 100 125 150
2
4
6
8
10
TJ, JUNCTION TEMPERATURE (oC)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 16. On-Resistance vs Gate to
Source Voltage
Figure 15. Normalized On-Resistance
vs Junction Temperature
40
40
VGS = 0 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
10
VDS = 5 V
30
20
10
0
TJ = 125 o
C
TJ = 125 o
C
1
TJ = 25 oC
TJ = 25 o
C
0.1
0.01
TJ = -55 o
C
TJ = -55 o
C
1.5
2.0
2.5
3.0
3.5
0.0
0.2
0.4
0.6
0.8
1.0
1.2
VGS, GATE TO SOURCE VOLTAGE (V)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 17. Transfer Characteristics
Figure 18. Source to Drain Diode
Forward Voltage vs Source Current
©2013 Fairchild Semiconductor Corporation
FDML7610S Rev.C1
www.fairchildsemi.com
7
Typical Characteristics (Q2 N-Channel) TJ = 25 oC unless otherwise noted
10
5000
ID = 17A
8
Ciss
VDD = 10 V
1000
6
Coss
VDD = 15 V
4
VDD = 20 V
2
f = 1 MHz
100
60
V
GS
= 0 V
Crss
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
0
0
10
20
30
40
50
0.1
1
30
Qg, GATE CHARGE (nC)
Figure 20. Capacitance vs Drain
to Source Voltage
Figure 19. Gate Charge Characteristics
80
100
10
RθJC = 3.5 oC/W
VGS = 10 V
60
40
20
0
1 ms
VGS = 4.5 V
10 ms
THIS AREA IS
1
LIMITED BY r
DS(on)
100 ms
SINGLE PULSE
TJ = MAX RATED
RθJA = 140 oC/W
TA = 25 oC
1s
0.1
10s
DC
Limited by package
50
0.01
200
100
25
75
100
125
150
0.01
0.1
1
10
TC, CASE TEMPERATURE (oC)
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 21. Maximun Continuous Drain
Current vs Case Temperature
Figure 22. Forward Bias Safe
Operating Area
300
100
SINGLE PULSE
RθJA = 140 oC/W
TA = 25 oC
10
1
0.001
0.01
0.1
1
10
100
1000
t, PULSE WIDTH (sec)
Figure 23. Single Pulse Maximum Power Dissipation
©2013 Fairchild Semiconductor Corporation
FDML7610S Rev.C1
www.fairchildsemi.com
8
Typical Characteristics (Q2 N-Channel) TJ = 25 oC unless otherwise noted
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
0.1
0.05
0.02
0.1
P
DM
0.01
t
1
0.01
t
SINGLE PULSE
θJA = 140 oC/W
Note 1d
2
NOTES:
DUTY FACTOR: D = t /t
R
1
2
PEAK T = P
J
x Z
x R
+ T
DM
θJA
θJA A
0.001
10-3
10-2
10-1
1
10
100
1000
t, RECTANGULAR PULSE DURATION (sec)
Figure24. Junction-to-Ambient Transient Thermal Response Curve
©2013 Fairchild Semiconductor Corporation
FDML7610S Rev.C1
www.fairchildsemi.com
9
Typical Characteristics (continued)
TM
SyncFET Schottky body diode
Characteristics
Fairchild’s SyncFETTM process embeds a Schottky diode in
parallel with PowerTrench MOSFET. This diode exhibits similar
characteristics to a discrete external Schottky diode in parallel
Schottky barrier diodes exhibit significant leakage at high tem-
perature and high reverse voltage. This will increase the power
in the device.
with
a MOSFET. Figure 25 shows the reverse recovery
characteristic of the FDML7610S.
10000
20
15
TJ = 125 o
C
1000
100
10
di/dt = 300 A/μs
TJ = 100 o
C
10
5
0
TJ = 25 o
C
1
-5
0
5
10
15
20
25
30
0
50
100
TIME (ns)
150
200
250
VDS, REVERSE VOLTAGE (V)
Figure 26. SyncFETTM body diode reverse
leakage versus drain-source voltage
Figure 25. FDML7610S SyncFETTM body
diode reverse recovery characteristic
©2013 Fairchild Semiconductor Corporation
FDML7610S Rev.C1
www.fairchildsemi.com
10
Application Information
1. Switch Node Ringing Suppression
Fairchild’s Power Stage products incorporate a proprietary design* that minimizes the peak overshoot, ringing voltage on the switch
node (PHASE) without the need of any external snubbing components in a buck converter. As shown in the figure 29, the Power Stage
solution rings significantly less than competitor solutions under the same set of test conditions.
Power Stage Device
Competitors solution
Figure 29. Power Stage phase node rising edge, High Side Turn on
*Patent Pending
©2013 Fairchild Semiconductor Corporation
FDML7610S Rev.C1
www.fairchildsemi.com
11
Figure 30. Shows the Power Stage in a buck converter topology
2. Recommended PCB Layout Guidelines
As a PCB designer, it is necessary to address critical issues in layout to minimize losses and optimize the performance of the power
train. Power Stage is a high power density solution and all high current flow paths, such as VIN (D1), PHASE (S1/D2) and GND (S2),
should be short and wide for better and stable current flow, heat radiation and system performance. A recommended layout proce-
dure is discussed below to maximize the electrical and thermal performance of the part.
Figure 31. Recommended PCB Layout
©2013 Fairchild Semiconductor Corporation
FDML7610S Rev.C1
www.fairchildsemi.com
12
Following is a guideline, not a requirement which the PCB designer should consider:
1. Input ceramic bypass capacitors C1 and C2 must be placed close to the D1 and S2 pins of Power Stage to help reduce parasitic
inductance and high frequency conduction loss induced by switching operation. C1 and C2 show the bypass capacitors placed close
to the part between D1 and S2. Input capacitors should be connected in parallel close to the part. Multiple input caps can be connected
depending upon the application.
2. The PHASE copper trace serves two purposes; In addition to being the current path from the Power Stage package to the output
inductor (L), it also serves as heat sink for the lower FET in the Power Stage package. The trace should be short and wide enough to
present a low resistance path for the high current flow between the Power Stage and the inductor. This is done to minimize conduction
losses and limit temperature rise. Please note that the PHASE node is a high voltage and high frequency switching node with high
noise potential. Care should be taken to minimize coupling to adjacent traces. The reference layout in figure 31 shows a good balance
between the thermal and electrical performance of Power Stage.
3. Output inductor location should be as close as possible to the Power Stage device for lower power loss due to copper trace
resistance. A shorter and wider PHASE trace to the inductor reduces the conduction loss. Preferably the Power Stage should be
directly in line (as shown in figure 31) with the inductor for space savings and compactness.
4. The PowerTrench® Technology MOSFETs used in the Power Stage are effective at minimizing phase node ringing. It allows the
part to operate well within the breakdown voltage limits. This eliminates the need to have an external snubber circuit in most cases. If
the designer chooses to use an RC snubber, it should be placed close to the part between the PHASE pad and S2 pins to dampen
the high-frequency ringing.
5. The driver IC should be placed close to the Power Stage part with the shortest possible paths for the High Side gate and Low Side
gates through a wide trace connection. This eliminates the effect of parasitic inductance and resistance between the driver and the
MOSFET and turns the devices on and off as efficiently as possible. At higher-frequency operation this impedance can limit the gate
current trying to charge the MOSFET input capacitance. This will result in slower rise and fall times and additional switching losses.
Power Stage has both the gate pins on the same side of the package which allows for back mounting of the driver IC to the board. This
provides a very compact path for the drive signals and improves efficiency of the part.
6. S2 pins should be connected to the GND plane with multiple vias for a low impedance grounding. Poor grounding can create a noise
transient offset voltage level between S2 and driver ground. This could lead to faulty operation of the gate driver and MOSFET.
7. Use multiple vias on each copper area to interconnect top, inner and bottom layers to help smooth current flow and heat conduction.
Vias should be relatively large, around 8 mils to 10 mils, and of reasonable inductance. Critical high frequency components such as
ceramic bypass caps should be located close to the part and on the same side of the PCB. If not feasible, they should be connected
from the backside via a network of low inductance vias.
©2013 Fairchild Semiconductor Corporation
FDML7610S Rev.C1
www.fairchildsemi.com
13
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