FDMS8622 [ONSEMI]
N 沟道，Power Trench® MOSFET，100V，16.5A，56mΩ;
| 型号： | FDMS8622 |
| 厂家： | 
ONSEMI |
| 描述： | N 沟道，Power Trench® MOSFET，100V，16.5A，56mΩ 开关 脉冲 光电二极管 晶体管 |
| 文件： | 总8页 (文件大小：498K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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August 2018
FDMS8622
N-Channel Shielded Gate PowerTrench® MOSFET
100 V, 16.5 A, 56 m
Features
General Description
Shielded Gate MOSFET Technology
This N-Channel MOSFET is produced using Fairchild
Semiconductor‘s advanced PowerTrench® process that
incorporates Shielded Gate technology. This process has been
optimized for rDS(on), switching performance and ruggedness.
Max rDS(on) = 56 m at VGS = 10 V, ID = 4.8 A
Max rDS(on) = 88 m at VGS = 6 V, ID = 3.9 A
High performance trench technology for extremely low rDS(on)
Applications
High power and current handling capability in a widely used
surface mount package
POE Protection Switch
DC-DC Switch
100% UIL Tested
Termination is Lead-free and RoHS Compliant
Bottom
Top
Pin 1
S
D
D
D
D
S
S
S
S
S
G
G
D
D
D
D
Power 56
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
VGS
Parameter
Ratings
Units
Drain to Source Voltage
Gate to Source Voltage
Drain Current -Continuous
-Continuous
100
±20
V
V
TC = 25 °C
TA = 25 °C
16.5
4.8
ID
(Note 1a)
(Note 3)
A
-Pulsed
30
EAS
Single Pulse Avalanche Energy
Power Dissipation
12
mJ
W
TC = 25 °C
TA = 25 °C
31
PD
Power Dissipation
(Note 1a)
2.5
TJ, TSTG
Operating and Storage Junction Temperature Range
-55 to +150
°C
Thermal Characteristics
RJC
RJA
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Ambient
(Note 1)
4
°C/W
(Note 1a)
50
Package Marking and Ordering Information
Device Marking
Device
Package
Reel Size
13 ’’
Tape Width
12 mm
Quantity
FDMS8622
FDMS8622
Power56
3000 units
©2011 Semiconductor Components Industries, LLC.
FDMS8622 Rev.2
www.onsemi.com
1
Electrical Characteristics TJ = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
ID = 250 A, VGS = 0 V
100
V
BVDSS
TJ
Breakdown Voltage Temperature
Coefficient
I
D = 250 A, referenced to 25 °C
69
mV/°C
IDSS
IGSS
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
VDS = 80 V, VGS = 0 V
VGS = ±20 V, VDS = 0 V
1
A
±100
nA
On Characteristics
VGS(th)
Gate to Source Threshold Voltage
VGS = VDS, ID = 250 A
2
3
4
V
VGS(th)
TJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID = 250 A, referenced to 25 °C
-8
mV/°C
V
GS = 10 V, ID = 4.8 A
45
62
78
9
56
88
97
rDS(on)
gFS
Static Drain to Source On Resistance
Forward Transconductance
VGS = 6 V, ID = 3.9 A
m
VGS = 10 V, ID = 4.8 A, TJ = 125 °C
VDD = 5 V, ID = 4.8 A
S
Dynamic Characteristics
Ciss
Coss
Crss
Rg
Input Capacitance
301
70
400
95
5
pF
pF
pF
V
DS = 50 V, VGS = 0 V,
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
f = 1 MHz
3.6
1.0
Switching Characteristics
td(on)
tr
td(off)
tf
Turn-On Delay Time
Rise Time
5.7
1.7
10.2
2.1
5
11
10
18
10
7
ns
ns
VDD = 50 V, ID = 4.8 A,
VGS = 10 V, RGEN = 6
Turn-Off Delay Time
Fall Time
ns
ns
Qg(TOT)
Qg(TOT)
Qgs
Total Gate Charge
Total Gate Charge
Total Gate Charge
Gate to Drain “Miller” Charge
VGS = 0 V to 10 V
nC
nC
nC
nC
VDD = 50 V,
D = 4.8 A
VGS = 0 V to 5 V
2.8
1.4
1.3
4
I
2.8
2.6
Qgd
Drain-Source Diode Characteristics
V
GS = 0 V, IS = 4.8 A
(Note 2)
(Note 2)
0.8
0.8
38
1.3
1.2
60
VSD
Source to Drain Diode Forward Voltage
V
VGS = 0 V, IS = 1.9 A
trr
Reverse Recovery Time
ns
IF = 4.8 A, di/dt = 100 A/s
Qrr
Reverse Recovery Charge
30
48
nC
Notes:
2
1. R
is determined with the device mounted on a 1in pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
is guaranteed by design while R is determined by
CA
JA
JC
the user's board design.
a)
50 °C/W when mounted on a
1 in pad of 2 oz copper
b) 125 °C/W when mounted on a
minimum pad of 2 oz copper.
2
2. Pulse Test: Pulse Width < 300 s, Duty cycle < 2.0%.
3.Starting T = 25 °C; N-ch: L = 0.1 mH, I = 16 A, V = 90 V, V = 10 V.
J
AS
DD
GS
©2011 Semiconductor Components Industries, LLC.
FDMS8622 Rev.2
www.onsemi.com
2
Typical Characteristics TJ = 25 °C unless otherwise noted
30
4
3
2
1
0
VGS = 10 V
VGS = 5 V
VGS = 7 V
VGS = 6 V
VGS = 8 V
25
VGS = 7 V
20
VGS = 6 V
15
10
5
VGS = 8 V
PULSE DURATION = 80 s
DUTY CYCLE = 0.5% MAX
VGS = 10 V
VGS = 5 V
PULSE DURATION = 80s
DUTY CYCLE = 0.5% MAX
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
5
10
15
20
25
30
35
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 1. On Region Characteristics
Figure2. N o r m a li z e d On - R e s is ta n c e
vs Drain Current and Gate Voltage
2.0
250
200
150
100
50
ID = 4.8 A
GS = 10 V
PULSE DURATION = 80s
DUTY CYCLE = 0.5% MAX
V
1.8
1.6
1.4
1.2
1.0
0.8
0.6
ID = 4.8 A
TJ = 125 o
C
TJ = 25 o
C
0
-75 -50 -25
0
25 50 75 100 125 150
4
6
8
10
o
TJ, JUNCTION TEMPERATURE ( C)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 3. Normalized On Resistance
vs Junction Temperature
Figure4. On-Resistance vs Gate to
Source Voltage
30
100
PULSE DURATION = 80 s
VGS = 0 V
TJ = 150 o
DUTY CYCLE = 0.5% MAX
25
20
15
10
5
10
C
VDS = 5 V
1
0.1
TJ = 25 o
C
TJ = 150 o
C
TJ = 25 o
C
0.01
0.001
TJ = -55 o
C
TJ = -55 o
C
0
2
3
4
5
6
7
8
9
0.2
0.4
0.6
0.8
1.0
1.2
VGS, GATE TO SOURCE VOLTAGE (V)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
Figure6. Source to Drain Diode
Forward Voltage vs Source Current
©2011 Semiconductor Components Industries, LLC.
FDMS8622 Rev.2
www.onsemi.com
3
Typical Characteristics TJ = 25 °C unless otherwise noted
10
500
100
10
ID = 4.8 A
VDD = 25 V
8
Ciss
VDD = 50 V
6
Coss
VDD = 75 V
4
2
0
f = 1 MHz
= 0 V
V
Crss
GS
1
0.1
0
2
4
6
1
10
100
VDS, DRAIN TO SOURCE VOLTAGE (V)
Q , GATE CHARGE (nC)
g
Figure 7. Gate Charge Characteristics
Figure8. C a p a c i t a n c e v s D r a i n
to Source Voltage
5
4
3
2
1
0
10
VGS = 10 V
8
6
TJ = 25 o
C
4
VGS = 6 V
TJ = 100 o
C
2
RJA = 50 oC/W
TJ = 125 o
C
1
0.01
0.1
1
10
25
50
75
100
125
150
o
tAV, TIME IN AVALANCHE (ms)
TA, AMBIENT TEMPERATURE ( C)
Figure9. U n c l a m p e d I n d u c t i v e
Switching Capability
Figure10. Maximum Continuous Drain
Current vs Ambient Temperature
100
1000
SINGLE PULSE
RJA = 125 oC/W
TA = 25 oC
10
1
100
10
1
100 us
THIS AREA IS
LIMITED BY rDS(on)
1 ms
10 ms
100 ms
1 s
SINGLE PULSE
TJ = MAX RATED
0.1
0.01
R
JA = 125 oC/W
A = 25 oC
10 s
DC
T
0.1
0.01
0.1
1
10
100
500
10-3
10-2
10-1
1
100
10
t, PULSE WIDTH (sec)
1000
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 11. Forward Bias Safe
Operating Area
Figure12. Single Pulse Maximum
Power Dissipation
©2011 Semiconductor Components Industries, LLC.
FDMS8622 Rev.2
www.onsemi.com
4
Typical Characteristics TJ = 25 °C unless otherwise noted
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
0.1
0.05
0.1
P
DM
0.02
0.01
t
1
t
2
0.01
NOTES:
DUTY FACTOR: D = t /t
SINGLE PULSE
RJA = 125 oC/W
1
2
PEAK T = P
x Z
x R
+ T
J
DM
JA
JA A
0.001
10-3
10-2
10-1
1
10
100
1000
t, RECTANGULAR PULSE DURATION (s)
Figure 13. Junction-to-Ambient Transient Thermal Response Curve
©2011 Semiconductor Components Industries, LLC.
FDMS8622 Rev.2
www.onsemi.com
5
Dimensional Outline and Pad Layout
5.20
A
5.10
3.91
4.80
SEE
DETAIL B
PKG
C
0.64
1.27
6.61
L
B
8
8
7
6
5
5
0.77
4.52
3.75
6.25
5.90
5.85
5.65
C
PKG
L
KEEP OUT
AREA
1.27
1
4
1
2
3
4
TOP VIEW
0.61
1.27
3.81
LAN D PATTERN
RECOMMEND ATION
OPTIONAL DRAFT
ANGLE MAY APPEAR
ON FOUR SIDES
SEE
DETAIL C
5.00
4.80
OF THE PACKAGE
0.35
0.15
0.10
0.08
C
0.30
0.06
0.05
0.00
SIDE VIEW
8X
C
C
0.35
0.15
1.10
0.90
SEATING
PLANE
DETAIL C
SCALE: 2:1
DETAIL B
SCALE: 2:1
3.81
1.27
0.51
0.31
(8X)
0.10
N OTES: UNLESS OTHERWISE SPECIFIED
(0.34)
A. PACKAGE STANDARD REFERENCE: JEDEC MO-240,
ISSUE A, VAR. AA, DATED OCTOBER 2002.
C
A B
1
2
3
4
B. DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH.
MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM.
C. ALL DIMENSIONS ARE IN MILLIMETERS.
0.76
0.44
(0.52)
D. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
E. IT IS RECOMMENDED TO HAVE NO TRACES OR
VIAS WITHIN THE KEEP OUT AREA.
3.78
3.38
(0.50)
4.22
3.99
F. DRAWING FILE NAME: PQFN08AREV8
(0.30)
(3.40)
(2X)
8
7
6
5
0.64
0.34
3.96
3.61
BOTTOM VIEW
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, spe-
cifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
https://www.fairchildsemi.com/evaluate/package-specifications/packageDetails.html?id=PN_PQOAM-008
©2011 Semiconductor Components Industries, LLC.
FDMS8622 Rev.2
www.onsemi.com
6
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Datasheet Identification
Product Status
Definition
Datasheet contains the design specifications for product development. Specifications
may change in any manner without notice.
Advance Information
Formative / In Design
Datasheet contains preliminary data; supplementary data will be published at a later
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Full Production
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Semiconductor. The datasheet is for reference information only.
Not In Production
Rev. I71
FDMS8622 Rev.2
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7
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