M74VHCT126ADTR2G [ONSEMI]
Quad Bus Buffer, 3-State, TTL Level;
| 型号： | M74VHCT126ADTR2G |
| 厂家： | 
ONSEMI |
| 描述： | Quad Bus Buffer, 3-State, TTL Level 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总8页 (文件大小：242K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74VHCT126A
Quad Bus Buffer
with 3−State Control Inputs
The MC74VHCT126A is a high speed CMOS quad bus buffer
fabricated with silicon gate CMOS technology. It achieves
noninverting high speed operation similar to equivalent Bipolar
Schottky TTL while maintaining CMOS low power dissipation.
The MC74VHCT126A requires the 3−state control input (OE) to be
set Low to place the output into high impedance.
The VHCT inputs are compatible with TTL levels. This device can
be used as a level converter for interfacing 3.3 V to 5.0 V, because it
has full 5.0 V CMOS level output swings.
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MARKING
DIAGRAMS
14
SOIC−14
D SUFFIX
CASE 751A
VHCT126AG
AWLYWW
The VHCT126A input structures provide protection when voltages
between 0 V and 5.5 V are applied, regardless of the supply voltage.
1
1
The output structures also provide protection when V = 0 V. These
CC
input and output structures help prevent device destruction caused by
supply voltage − input/output voltage mismatch, battery backup, hot
insertion, etc.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
14
VHCT
126A
ALYWG
G
TSSOP−14
DT SUFFIX
CASE 948G
1
1
A
= Assembly Location
WL, L = Wafer Lot
= Year
Features
Y
WW, W = Work Week
• High Speed: t = 3.8 ns (Typ) at V = 5.0 V
PD
CC
G or G = Pb−Free Package
• Low Power Dissipation: I = 4.0 mA (Max) at T = 25°C
CC
A
(Note: Microdot may be in either location)
• TTL−Compatible Inputs: V = 0.8 V; V = 2.0 V
IL
IH
See Applications Note #AND8004/D for
date code and traceability information.
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2.0 V to 5.5 V Operating Range
FUNCTION TABLE
VHCT126A
• Low Noise: V
= 0.8 V (Max)
OLP
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
Inputs
Outputs
• ESD Performance: HBM > 2000 V; Machine Model > 200 V
• Chip Complexity: 72 FETs or 18 Equivalent Gates
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
A
OE
Y
H
L
X
H
H
L
H
L
Z
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
October, 2016 − Rev. 11
MC74VHCT126A/D
MC74VHCT126A
2
1
3
6
A1
Y1
OE1
OE1
A1
1
2
14
13 OE4
12
V
CC
5
4
A2
Y2
Y3
Y1
3
4
A4
OE2
OE2
11 Y4
9
8
A3
A2
Y2
5
6
7
10 OE3
10
9
8
A3
Y3
OE3
GND
12
13
11
A4
Y4
OE4
Figure 2. PIN ASSIGNMENT
Figure 1. LOGIC DIAGRAM
Active−High Output Enables
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
DC Supply Voltage
DC Input Voltage
DC Output Voltage
V
CC
– 0.5 to + 7.0
– 0.5 to + 7.0
– 0.5 to + 7.0
V
in
V
Output in 3−State
High or Low State
V
out
V
– 0.5 to V + 0.5
CC
Input Diode Current
I
IK
− 20
20
mA
mA
mA
mA
mW
cuit. For proper operation, V and
in
V
out
should be constrained to the
Output Diode Current (V
< GND; V
> V
)
I
OK
OUT
OUT
CC
range GND v (V or V ) v V
.
in
out
CC
DC Output Current, per Pin
DC Supply Current, V and GND Pins
I
I
25
out
Unused inputs must always be
tied to an appropriate logic voltage
75
CC
CC
level (e.g., either GND or V ).
CC
Power Dissipation in Still Air,
SOIC Packages†
TSSOP Package†
P
D
500
450
Unused outputs must be left open.
Storage Temperature
T
– 65 to + 150
_C
stg
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
4.5
0
Max
5.5
5.5
5.5
Unit
V
DC Supply Voltage
DC Input Voltage
DC Output Voltage
V
CC
V
in
V
Output in 3−State
High or Low State
V
out
0
0
V
V
CC
Operating Temperature
Input Rise and Fall Time
T
− 40
0
+ 85
20
_C
A
V
CC
= 5.0 V 0.5 V
t , t
r f
ns/V
Functional operation above the stresses listed in the Recommended Operating Ranges is not
implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may
affect device reliability.
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2
MC74VHCT126A
DC ELECTRICAL CHARACTERISTICS
T
A
= 25°C
T
A
≤ 85°C
T ≤ 125°C
A
V
CC
(V)
Min Typ Max
Min
Max
Min
Max
Parameter
Test Conditions
Symbol
Unit
Minimum High−Level Input
Voltage
V
IH
3.0
4.5
5.5
1.2
2.0
2.0
1.2
2.0
2.0
1.2
2.0
2.0
V
Maximum Low−Level Input
Voltage
V
3.0
4.5
5.5
0.53
0.8
0.8
0.53
0.8
0.8
0.53
0.8
0.8
V
V
IL
Minimum High−Level Output
Voltage
V
= V or V
= − 50 mA
V
OH
3.0
4.5
2.9
4.4
3.0
4.5
2.9
4.4
2.9
4.4
IN
IH
IL
I
OH
V
IN
= V or V
IH IL
V
I
I
= V or V
IH
= − 4.0 mA
= − 8.0 mA
IN
OH
OH
IL
3.0
4.5
2.58
3.94
2.48
3.80
2.34
3.66
Maximum Low−Level Output
Voltage
V
= V or V
= 50 mA
V
OL
3.0
4.5
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
IN
IH
IL
I
OL
V
IN
= V or V
IH IL
V
I
I
= V or V
= 4.0 mA
= 8.0 mA
IN
OL
OL
IH
IL
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
Maximum Input Leakage Current
V
V
= 5.5 V or GND
I
0 to 5.5
5.5
0.1
2.0
1.0
20
1.0
40
mA
mA
IN
IN
Maximum Quiescent Supply
Current
= V or GND
I
CC
IN
CC
Quiescent Supply Current
Input: V = 3.4 V
I
5.5
5.5
1.35
1.50
2.5
1.65
2.5
mA
IN
CCT
Maximum 3−State Leakage
Current
V
V
= V or V
I
OZ
0.2
5
mA
IN
IH
I
= V or GND
OUT
CC
Output Leakage Current
V
OUT
= 5.5 V
I
0.0
0.5
5.0
10
mA
OPD
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0 ns)
r
f
T
A
= 25°C
T
A
= ≤ 85°C
T ≤ 125°C
A
Min Typ Max
Min
Max
Min
Max
Parameter
Test Conditions
= 3.3 0.3 V C = 15 pF
Symbol
Unit
Maximum Propagation Delay,
A to Y
V
V
V
t
t
t
,
5.6
8.1
8.0
11.5
1.0
1.0
9.5
13.0
12.0
16.0
ns
CC
CC
CC
L
PLH
t
C = 50 pF
L
PHL
= 5.0 0.5 V C = 15 pF
3.8
5.3
5.5
7.5
1.0
1.0
6.5
8.5
8.5
10.5
L
C = 50 pF
L
Maximum Output Enable
TIme,OE to Y
= 3.3 0.3 V C = 15 pF
,
PZL
PZH
5.4
7.9
8.0
11.5
1.0
1.0
9.5
13.0
11.5
15.0
ns
ns
ns
L
t
R = 1.0 kW
C = 50 pF
L
L
V
CC
= 5.0 0.5 V C = 15 pF
3.6
5.1
5.1
7.1
1.0
1.0
6.0
8.0
7.5
9.5
L
R = 1.0 kW
C = 50 pF
L
L
Maximum Output
Disable Time,OE to Y
V
CC
= 3.3 0.3 V C = 50 pF
,
PLZ
9.5
13.2
8.8
1.5
1.0
10
1.0
15.0
10.0
1.5
18.0
12.0
2.0
L
t
R = 1.0 kW
PHZ
L
V
CC
= 5.0 0.5 V C = 50 pF
L
R = 1.0 kW
6.1
1.0
L
Output−to−Output Skew
V
CC
= 3.3 0.3 V C = 50 pF
t
,
L
OSLH
(Note 1)
t
OSHL
V
CC
= 5.0 0.5 V C = 50 pF
1.0
1.5
L
(Note 1)
Maximum Input Capacitance
C
4
6
10
10
pF
pF
in
Maximum Three−State Output
Capacitance (Output in High
Impedance State)
C
out
Typical @ 25°C, V = 5.0V
CC
15
Power Dissipation Capacitance (Note 2)
1. Parameter guaranteed by design. t
C
pF
PD
= |t
− t
|, t
= |t
− t
PHLn
|.
OSLH
PLHm
PLHn OSHL
PHLm
2. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
no−load dynamic power consumption; P = C ꢀ V
) = C ꢀ V ꢀ f + I /4 (per buffer). C is used to determine the
CC(OPR
PD CC in CC PD
2
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
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3
MC74VHCT126A
NOISE CHARACTERISTICS (Input t = t = 3.0ns, C = 50pF, V = 5.0V)
r
f
L
CC
T
A
= 25°C
Typ
0.3
Max
0.8
Characteristic
Quiet Output Maximum Dynamic V
Symbol
Unit
V
OLP
V
OL
Quiet Output Minimum Dynamic V
V
− 0.3
− 0.8
3.5
V
V
V
OL
OLV
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
V
IHD
V
1.5
ILD
SWITCHING WAVEFORMS
3.0V
OE
1.5V
3.0V
GND
A
Y
1.5V
t
t
PZL
PLZ
GND
HIGH
IMPEDANCE
t
PHL
t
PLH
1.5V
t
Y
V
OH
V
OL
V
V
+ 0.3V
OL
1.5V
t
PZH
PHZ
- 0.3V
OH
1.5V
Y
HIGH
IMPEDANCE
Figure 3.
Figure 4.
TEST POINT
TEST POINT
CONNECT TO V WHEN
CC
1 kW
TESTING t AND t
PZL.
OUTPUT
OUTPUT
PLZ
DEVICE
UNDER
TEST
CONNECT TO GND WHEN
TESTING t AND t
DEVICE
UNDER
TEST
PHZ
PZH.
C *
L
C *
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 5. Test Circuit
Figure 6. Test Circuit
ORDERING INFORMATION
†
Device
Package
Shipping
MC74VHCT126ADR2G
SOIC−14
(Pb−Free)
2500 / Tape & Reel
M74VHCT126ADTR2G
NLVVHCT126ADTR2G*
TSSOP−14
(Pb−Free)
2500 / Tape & Reel
2500 / Tape & Reel
TSSOP−14
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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4
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE L
14
1
DATE 03 FEB 2016
SCALE 1:1
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
14
8
7
A3
E
H
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
L
DETAIL A
1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
13X b
M
M
B
0.25
A
A1
A3
b
D
E
1.35
0.10
0.19
0.35
8.55
3.80
1.75 0.054 0.068
0.25 0.004 0.010
0.25 0.008 0.010
0.49 0.014 0.019
8.75 0.337 0.344
4.00 0.150 0.157
M
S
S
B
0.25
C A
DETAIL A
h
A
X 45
_
e
H
h
L
1.27 BSC
0.050 BSC
6.20 0.228 0.244
0.50 0.010 0.019
1.25 0.016 0.049
5.80
0.25
0.40
0
0.10
M
A1
e
M
7
0
7
_
_
_
_
SEATING
PLANE
C
GENERIC
MARKING DIAGRAM*
SOLDERING FOOTPRINT*
6.50
14
14X
1.18
XXXXXXXXXG
AWLYWW
1
1
XXXXX = Specific Device Code
A
WL
Y
= Assembly Location
= Wafer Lot
= Year
1.27
PITCH
WW
G
= Work Week
= Pb−Free Package
14X
0.58
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
STYLES ON PAGE 2
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
PAGE 1 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SOIC−14
CASE 751A−03
ISSUE L
DATE 03 FEB 2016
STYLE 1:
STYLE 2:
CANCELLED
STYLE 3:
STYLE 4:
PIN 1. NO CONNECTION
2. CATHODE
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. NO CONNECTION
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. NO CONNECTION
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
PIN 1. NO CONNECTION
2. ANODE
3. ANODE
4. NO CONNECTION
5. ANODE
6. NO CONNECTION
7. ANODE
8. ANODE
9. ANODE
10. NO CONNECTION
11. ANODE
12. ANODE
13. NO CONNECTION
14. COMMON CATHODE
3. CATHODE
4. NO CONNECTION
5. CATHODE
6. NO CONNECTION
7. CATHODE
8. CATHODE
9. CATHODE
10. NO CONNECTION
11. CATHODE
12. CATHODE
13. NO CONNECTION
14. COMMON ANODE
STYLE 5:
STYLE 6:
STYLE 7:
STYLE 8:
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. NO CONNECTION
7. COMMON ANODE
8. COMMON CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. ANODE/CATHODE
12. ANODE/CATHODE
13. NO CONNECTION
14. COMMON ANODE
PIN 1. CATHODE
2. CATHODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
7. CATHODE
8. ANODE
PIN 1. ANODE/CATHODE
2. COMMON ANODE
3. COMMON CATHODE
4. ANODE/CATHODE
5. ANODE/CATHODE
6. ANODE/CATHODE
7. ANODE/CATHODE
8. ANODE/CATHODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. COMMON CATHODE
12. COMMON ANODE
13. ANODE/CATHODE
14. ANODE/CATHODE
PIN 1. COMMON CATHODE
2. ANODE/CATHODE
3. ANODE/CATHODE
4. NO CONNECTION
5. ANODE/CATHODE
6. ANODE/CATHODE
7. COMMON ANODE
8. COMMON ANODE
9. ANODE/CATHODE
10. ANODE/CATHODE
11. NO CONNECTION
12. ANODE/CATHODE
13. ANODE/CATHODE
14. COMMON CATHODE
9. ANODE
10. ANODE
11. ANODE
12. ANODE
13. ANODE
14. ANODE
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42565B
SOIC−14 NB
PAGE 2 OF 2
onsemi and
are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP−14 WB
CASE 948G
ISSUE C
14
DATE 17 FEB 2016
1
SCALE 2:1
NOTES:
14X K REF
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
S
0.15 (0.006) T U
N
0.25 (0.010)
14
8
2X L/2
M
B
L
N
−U−
PIN 1
IDENT.
F
7
1
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
DETAIL E
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T U
A
−V−
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
K1
A
B
C
D
F
G
H
J
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
J J1
1.20
−−− 0.047
0.15 0.002 0.006
0.75 0.020 0.030
SECTION N−N
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
J1
K
−W−
C
K1 0.19
L
M
6.40 BSC
0.252 BSC
0.10 (0.004)
0
8
0
8
_
_
_
_
SEATING
PLANE
−T−
H
G
DETAIL E
D
GENERIC
MARKING DIAGRAM*
14
SOLDERING FOOTPRINT
XXXX
XXXX
ALYWG
G
7.06
1
1
A
L
= Assembly Location
= Wafer Lot
Y
W
G
= Year
= Work Week
= Pb−Free Package
0.65
PITCH
(Note: Microdot may be in either location)
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
01.34X6
14X
1.26
DIMENSIONS: MILLIMETERS
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