MTB40N10ET4 [ONSEMI]
40A, 100V, 0.04ohm, N-CHANNEL, Si, POWER, MOSFET, D2PAK-3;
| 型号： | MTB40N10ET4 |
| 厂家： | 
ONSEMI |
| 描述： | 40A, 100V, 0.04ohm, N-CHANNEL, Si, POWER, MOSFET, D2PAK-3 |
| 文件： | 总12页 (文件大小：123K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MTB40N10E
Preferred Device
Power MOSFET
40 Amps, 100 Volts
2
N–Channel D PAK
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. The energy efficient design also
offers a drain–to–source diode with a fast recovery time. Designed for
low voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
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40 AMPERES
100 VOLTS
R
= 40 mΩ
DS(on)
• Avalanche Energy Specified
• Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
N–Channel
D
• Diode is Characterized for Use in Bridge Circuits
• I
and V Specified at Elevated Temperature
DSS
DS(on)
G
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
C
Rating
Drain–to–Source Voltage
Drain–to–Gate Voltage (R
Symbol
Value
100
Unit
Vdc
Vdc
S
V
DSS
= 1.0 MΩ)
V
DGR
100
GS
4
Gate–to–Source Voltage
– Continuous
V
± 20
± 40
Vdc
Vpk
GS
2
D PAK
– Non–Repetitive (t ≤ 10 ms)
V
GSM
p
CASE 418B
STYLE 2
2
3
1
Drain Current – Continuous
Drain Current – Continuous @ 100°C
Drain Current – Single Pulse (t ≤ 10 µs)
I
I
40
29
140
Adc
D
D
I
Apk
p
DM
MARKING DIAGRAM
& PIN ASSIGNMENT
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ T = 25°C
(Note 1.)
P
169
1.35
2.5
Watts
W/°C
Watts
D
4
A
Drain
Operating and Storage Temperature
Range
T , T
stg
– 55 to
150
°C
J
T40N10E
YWW
Single Pulse Drain–to–Source Avalanche
E
AS
mJ
Energy – Starting T = 25°C
800
J
(V
= 75 Vdc, V
= 10 Vdc, Peak
DD
GS
= 40 Apk, L = 1.0 mH, R = 25 Ω)
I
L
G
1
2
3
Thermal Resistance
°C/W
°C
Gate
Drain
Source
– Junction to Case
– Junction to Ambient
– Junction to Ambient (Note 1.)
R
R
R
0.74
62.5
50
θJC
θJA
θJA
T40N10E = Device Code
Y
= Year
= Work Week
WW
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10
seconds
T
260
L
ORDERING INFORMATION
1. When surface mounted to an FR4 board using the minimum recommended
pad size.
Device
Package
Shipping
50 Units/Rail
2
D PAK
MTB40N10E
MTB40N10ET4
2
D PAK
800/Tape & Reel
Preferred devices are recommended choices for future use
and best overall value.
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
November, 2000 – Rev. 2
MTB40N10E/D
MTB40N10E
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Characteristic
OFF CHARACTERISTICS
Symbol
Min
Typ
Max
Unit
Drain–to–Source Breakdown Voltage
V
Vdc
(BR)DSS
(V
= 0 Vdc, I = 0.25 mAdc)
100
–
–
112
–
–
GS
D
Temperature Coefficient (Positive)
(Cpk ≥ 2.0) (Note 4.)
mV/°C
µAdc
Zero Gate Voltage Drain Current
I
DSS
GSS
(V
DS
(V
DS
= 100 Vdc, V
= 100 Vdc, V
= 0 Vdc)
= 0 Vdc, T = 125°C)
–
–
–
–
10
100
GS
GS
J
Gate–Body Leakage Current (V
= ± 20 Vdc, V
DS
= 0 Vdc)
I
–
–
100
nAdc
Vdc
GS
ON CHARACTERISTICS (Note 2.)
Gate Threshold Voltage
(Cpk ≥ 2.0) (Note 4.)
V
GS(th)
(V
= V , I = 250 µAdc)
2.0
–
2.9
6.7
4.0
–
DS
GS
D
Threshold Temperature Coefficient (Negative)
mV/°C
Static Drain–to–Source On–Resistance
R
V
Ohms
DS(on)
(V
GS
= 10 Vdc, I = 20 Adc)
(Cpk ≥ 2.0) (Note 4.)
–
0.033
0.04
D
Drain–to–Source On–Voltage (V
= 10 Vdc)
Vdc
GS
DS(on)
(I = 40 Adc)
–
–
–
–
1.9
1.7
D
(I = 20 Adc, T = 125°C)
D
J
Forward Transconductance (V
DS
= 8.4 Vdc, I = 20 Adc)
g
17
21
–
mhos
pF
D
FS
DYNAMIC CHARACTERISTICS
Input Capacitance
C
–
–
–
2305
620
3230
1240
290
iss
(V
DS
= 25 Vdc, V
GS
f = 1.0 MHz)
= 0 Vdc,
Output Capacitance
C
oss
Transfer Capacitance
C
205
rss
SWITCHING CHARACTERISTICS (Note 3.)
Turn–On Delay Time
t
–
–
–
–
–
–
–
–
19
165
75
97
80
15
40
29
40
330
150
190
110
–
ns
d(on)
(V
= 50 Vdc, I = 40 Adc,
D
Rise Time
DD
DS
t
r
V
= 10 Vdc,
GS
G
Turn–Off Delay Time
Fall Time
t
d(off)
R
= 9.1 Ω)
t
f
Gate Charge
(See Figure 8)
Q
T
Q
1
Q
2
Q
3
nC
(V
= 80 Vdc, I = 40 Adc,
D
V
GS
= 10 Vdc)
–
–
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
V
Vdc
ns
SD
(I = 40 Adc, V
= 0 Vdc)
–
–
0.96
0.88
1.0
–
S
GS
= 0 Vdc, T = 125°C)
(I = 40 Adc, V
S
GS
J
Reverse Recovery Time
(See Figure 14)
t
–
–
–
–
152
117
35
–
–
–
–
rr
t
a
(I = 40 Adc, V
= 0 Vdc,
S
GS
dI /dt = 100 A/µs)
t
b
S
Reverse Recovery Stored
Charge
Q
1.0
µC
RR
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)
L
D
nH
–
–
3.5
4.5
–
–
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
L
S
–
7.5
–
2. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
3. Switching characteristics are independent of operating junction temperature.
Max limit – Typ
3 sigma
4. Reflects typical values.
Cpk + Ť
Ť
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MTB40N10E
TYPICAL ELECTRICAL CHARACTERISTICS
80
70
60
50
40
30
20
80
V
GS
= 10 V
T = 25°C
8 V
9 V
100°C
J
V
DS
≥ 10 V
70
60
50
40
30
20
25°C
7 V
T = -55°C
J
6 V
5 V
9
10
0
10
0
0
1
2
3
4
5
6
7
8
10
2
3
4
5
6
7
8
V
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
V
, GATE-TO-SOURCE VOLTAGE (VOLTS)
DS
Figure 1. On–Region Characteristics
GS
Figure 2. Transfer Characteristics
0.07
0.06
0.05
0.04
0.03
0.02
0.050
V
GS
= 10 V
T = 25°C
J
0.045
0.040
0.035
0.030
T = 100°C
J
V
GS
= 10 V
25°C
15 V
0.025
0.020
-55°C
0.01
0
0.015
0.010
0
10
20
30
40
50
60
70
80
0
10
20
30
40
50
60
70
80
I , DRAIN CURRENT (AMPS)
D
I , DRAIN CURRENT (AMPS)
D
Figure 3. On–Resistance versus Drain Current
and Temperature
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
1000
100
2.0
1.8
1.6
V
GS
= 0 V
T = 125°C
V
I
= 10 V
J
GS
= 20 A
D
1.4
1.2
1.0
0.8
0.6
0.4
100°C
10
0.2
0
1.0
0
10
20
30
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
DS
40
50
60
70
80
90 100
-50 -25
0
25
50
75
100
125
150
T , JUNCTION TEMPERATURE (°C)
J
V
Figure 5. On–Resistance Variation with
Temperature
Figure 6. Drain–To–Source Leakage
Current versus Voltage
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MTB40N10E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (∆t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain–gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
The capacitance (C ) is read from the capacitance curve at
a voltage corresponding to the off–state condition when
iss
calculating t
and is read at a voltage corresponding to the
on–state when calculating t
d(on)
.
d(off)
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
average input current (I
) can be made from a
G(AV)
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V remains virtually constant at a level
GS
known as the plateau voltage, V
. Therefore, rise and fall
SGP
times may be approximated by the following:
t = Q x R /(V
– V )
GSP
r
2
G
GG
t = Q x R /V
f
2
G
GSP
where
V
= the gate drive voltage, which varies from zero to V
GG
= the gate drive resistance
GG
R
G
and Q and V
are read from the gate charge curve.
2
GSP
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
t
= R
= R
C
C
In [V /(V
GG GG
iss GG GSP
– V
)
)]
GSP
d(on)
d(off)
G
G
iss
In (V /V
8000
7000
6000
5000
4000
3000
2000
V
DS
= 0 V
V
GS
= 0 V
T = 25°C
J
C
iss
C
rss
C
iss
C
oss
1000
0
C
V
rss
-10
-5
0
5
10
15
20
25
V
GS
DS
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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MTB40N10E
10,000
10
9
80
72
64
56
48
40
32
24
16
V
GS
V
I
= 50 V
DD
QT
Q2
= 40 A
D
8
V
= 10 V
GS
T = 25°C
J
7
1000
6
Q1
5
t
r
t
f
4
100
10
3
I
= 40 A
D
t
T = 25°C
d(off)
J
2
V
DS
8
0
1
0
t
Q3
d(on)
1.0
10
R , GATE RESISTANCE (OHMS)
100
0
10
20
30
40
50
60
70
80
Q , TOTAL GATE CHARGE (nC)
G
G
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
40
V
= 0 V
GS
T = 25°C
35
30
25
20
15
10
J
5
0
0.60 0.65
0.70
0.75
0.80
0.85
0.90
0.95
1.0
V , SOURCE-TO-DRAIN VOLTAGE (VOLTS)
SD
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction
temperature.
junction temperature and a case temperature (T ) of 25°C.
C
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed
in
AN569,
“Transient
Thermal
Resistance–General Data and Its Use.”
Switching between the off–state and the on–state may
traverse any load line provided neither rated peak current
Although many E–FETs can withstand the stress of
drain–to–source avalanche at currents up to rated pulsed
current (I
), the energy rating is specified at rated
DM
(I
) nor rated voltage (V
) is exceeded and the
continuous current (I ), in accordance with industry
DM DSS
D
transition time (t ,t ) do not exceed 10 µs. In addition the total
power averaged over a complete switching cycle must not
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 12). Maximum
r f
exceed (T
– T )/(R
).
energy at currents below rated continuous I can safely be
assumed to equal the values indicated.
J(MAX)
C
θJC
D
A Power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For
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MTB40N10E
SAFE OPERATING AREA
800
1000
100
R
LIMIT
V
= 20 V
DS(on)
THERMAL LIMIT
PACKAGE LIMIT
GS
SINGLE PULSE
= 25°C
I
D
= 40 A
700
600
500
400
300
200
T
C
10 ms
100 ms
1.0 ms
10
10 ms
100
0
dc
1.0
100
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
0.1
1.0
10
1000
25
50
75
100
125
150
V
DS
T , STARTING JUNCTION TEMPERATURE (°C)
J
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
1.0
D = 0.5
0.2
0.1
P
(pk)
0.1
R
(t) = r(t) R
0.05
0.02
θJC
θJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
t
READ TIME AT t
1
1
t
T
- T = P
C
R
(t)
2
DUTY CYCLE, D = t /t
J(pk)
(pk) θJC
0.0
1 2
SINGLE PULSE
0.01
1.0E-05
1.0E-04
1.0E-03
1.0E-02
t, TIME (seconds)
1.0E-01
1.0E+00
1.0E+01
Figure 13. Thermal Response
3
R
= 50°C/W
θJA
Board material = 0.065 mil FR–4
Mounted on the minimum recommended footprint
Collector/Drain Pad Size ≈ 450 mils x 350 mils
2.5
2.0
1.5
1
di/dt
I
S
t
rr
t
a
t
b
TIME
0.5
0.25 I
t
p
S
0
25
50
75
100
125
150
I
S
T , AMBIENT TEMPERATURE (°C)
A
2
Figure 15. D PAK Power Derating Curve
Figure 14. Diode Reverse Recovery Waveform
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MTB40N10E
2
INFORMATION FOR USING THE D PAK SURFACE MOUNT PACKAGE
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the
total design. The footprint for the semiconductor packages
must be the correct size to ensure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
0.33
8.38
0.08
2.032
0.24
0.42
10.66
6.096
0.04
1.016
0.12
3.05
0.63
17.02
inches
mm
POWER DISSIPATION FOR A SURFACE MOUNT DEVICE
150°C – 25°C
50°C/W
The power dissipation for a surface mount device is a
function of the drain pad size. These can vary from the
minimum pad size for soldering to a pad size given for
maximum power dissipation. Power dissipation for a
= 2.5 Watts
P
=
D
2
The 50°C/W for the D PAK package assumes the use of
the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 2.5 Watts. There are
other alternatives to achieving higher power dissipation
from the surface mount packages. One is to increase the
area of the drain pad. By increasing the area of the drain
pad, the power dissipation can be increased. Although one
can almost double the power dissipation with this method,
one will be giving up area on the printed circuit board
which can defeat the purpose of using surface mount
surface mount device is determined by T
maximum rated junction temperature of the die, R
, the
, the
J(max)
θJA
thermal resistance from the device junction to ambient, and
the operating temperature, T . Using the values provided
A
on the data sheet, P can be calculated as follows:
D
T
– T
A
J(max)
P
=
D
R
θJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values
technology. For example, a graph of R
area is shown in Figure 16.
versus drain pad
θJA
into the equation for an ambient temperature T of 25°C,
A
one can calculate the power dissipation of the device. For a
2
D PAK device, P is calculated as follows.
D
70
Board Material = 0.0625″
G-10/FR-4, 2 oz Copper
T = 25°C
A
60
50
2.5 Watts
3.5 Watts
40
30
5 Watts
20
0
2
4
6
8
10
12
14
16
A, AREA (SQUARE INCHES)
Figure 16. Thermal Resistance versus Drain Pad
2
Area for the D PAK Package (Typical)
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MTB40N10E
Another alternative would be to use a ceramic substrate
board, the power dissipation can be doubled using the same
footprint.
or an aluminum core board such as Thermal Cladt. Using
a board material such as Thermal Clad, an aluminum core
SOLDER STENCIL GUIDELINES
Prior to placing surface mount components onto a printed
circuit board, solder paste must be applied to the pads.
Solder stencils are used to screen the optimum amount.
These stencils are typically 0.008 inches thick and may be
made of brass or stainless steel. For packages such as the
SC–59, SC–70/SOT–323, SOD–123, SOT–23, SOT–143,
SOT–223, SO–8, SO–14, SO–16, and SMB/SMC diode
packages, the stencil opening should be the same as the pad
size or a 1:1 registration. This is not the case with the DPAK
pattern of the opening in the stencil for the drain pad is not
critical as long as it allows approximately 50% of the pad to
be covered with paste.
SOLDER PASTE
OPENINGS
2
and D PAK packages. If one uses a 1:1 opening to screen
STENCIL
solder onto the drain pad, misalignment and/or
“tombstoning” may occur due to an excess of solder. For
these two packages, the opening in the stencil for the paste
should be approximately 50% of the tab area. The opening
for the leads is still a 1:1 registration. Figure 17 shows a
Figure 17. Typical Stencil for DPAK and
2
D PAK Packages
2
typical stencil for the DPAK and D PAK packages. The
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
• Always preheat the device.
• The delta temperature between the preheat and
soldering should be 100°C or less.*
• When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied
during cooling.
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10°C.
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
* Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.
* Due to shadowing and the inability to set the wave height
2
to incorporate other surface mount components, the D PAK
is not recommended for wave soldering.
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MTB40N10E
TYPICAL SOLDER HEATING PROFILE
For any given circuit board, there will be a group of
The line on the graph shows the actual temperature that
might be experienced on the surface of a test board at or
near a central solder joint. The two profiles are based on a
high density and a low density board. The Vitronics
SMD310 convection/infrared reflow soldering system was
used to generate this profile. The type of solder used was
62/36/2 Tin Lead Silver with a melting point between
177–189°C. When this type of furnace is used for solder
reflow work, the circuit boards and solder joints tend to
heat first. The components on the board are then heated by
conduction. The circuit board, because it has a large surface
area, absorbs the thermal energy more efficiently, then
distributes this energy to the components. Because of this
effect, the main body of a component may be up to 30
degrees cooler than the adjacent solder joints.
control settings that will give the desired heat pattern. The
operator must set temperatures for several heating zones,
and a figure for belt speed. Taken together, these control
settings make up a heating “profile” for that particular
circuit board. On machines controlled by a computer, the
computer remembers these profiles from one operating
session to the next. Figure 18 shows a typical heating
profile for use when soldering a surface mount device to a
printed circuit board. This profile will vary among
soldering systems but it is a good starting point. Factors that
can affect the profile include the type of soldering system in
use, density and types of components on the board, type of
solder used, and the type of board or substrate material
being used. This profile shows temperature versus time.
STEP 1
PREHEAT
ZONE 1
“RAMP”
STEP 2
VENT
“SOAK” ZONES 2 & 5
“RAMP”
STEP 3
HEATING
STEP 4
HEATING
ZONES 3 & 6
“SOAK”
STEP 5
HEATING
ZONES 4 & 7
“SPIKE”
STEP 6
VENT
STEP 7
COOLING
205° TO 219°C
PEAK AT
SOLDER
JOINT
170°C
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
200°C
150°C
100°C
5°C
160°C
150°C
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
100°C
140°C
MASS OF ASSEMBLY)
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
TIME (3 TO 7 MINUTES TOTAL)
T
MAX
Figure 18. Typical Solder Heating Profile
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9
MTB40N10E
PACKAGE DIMENSIONS
2
D PAK
CASE 418B–03
ISSUE D
C
E
V
–B–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
4
2. CONTROLLING DIMENSION: INCH.
INCHES
DIM MIN MAX
MILLIMETERS
A
MIN
8.64
9.65
4.06
0.51
1.14
MAX
9.65
10.29
4.83
0.89
1.40
A
B
C
D
E
G
H
J
0.340
0.380
0.160
0.020
0.045
0.380
0.405
0.190
0.035
0.055
S
1
2
3
–T–
SEATING
PLANE
K
0.100 BSC
2.54 BSC
0.080
0.018
0.090
0.575
0.045
0.110
0.025
0.110
0.625
0.055
2.03
0.46
2.79
0.64
J
G
K
S
V
2.29
14.60
1.14
2.79
15.88
1.40
H
D 3 PL
M
M
T B
0.13 (0.005)
STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
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10
MTB40N10E
Notes
http://onsemi.com
11
MTB40N10E
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