NB7NPQ7021MMUTXG [ONSEMI]
3.3V USB 3.1 Dual Channel Linear Redriver;
| 型号： | NB7NPQ7021MMUTXG |
| 厂家： | 
ONSEMI |
| 描述： | 3.3V USB 3.1 Dual Channel Linear Redriver |
| 文件： | 总9页 (文件大小：109K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NB7NPQ7021M
3.3 V USB 3.1 Dual Channel
Linear Redriver
Description
The NB7NPQ7021M is a 3.3 V dual channel redriver for USB 3.1
Gen 1 and USB 3.1 Gen 2 applications that supports both 5 Gbps and
10 Gbps data rates. Signal integrity degrades from PCB traces,
transmission cables, and inter−symbol interference (ISI). The
NB7NPQ7021M compensates for these losses by engaging varying
levels of equalization at the input receiver, and flat gain amplification
on the output transmitter. The Flat Gain and Equalization are
controlled by four level control pins. Each channel has a set of
independent control pins to make signal optimization possible.
After power up, the NB7NPQ7021M periodically checks both of the
TX output pairs for a receiver connection. When the receiver is
detected on both channels the RX termination becomes enabled and
the NB7NPQ7021M is set to perform the redriver function.
The NB7NPQ7021M comes in a small 3 x 3 mm UQFN16 package
and is specified to operate across the entire industrial temperature
range of –40°C to 85°C.
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MARKING
DIAGRAM
NB7N
7021
ALYWG
G
1
UQFN16
CASE 523AF
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
Features
ORDERING INFORMATION
• 3.3 V 5% Power Supply
†
• Supports USB 3.1 Gen 1 and USB 3.1 Gen 2 Data Rates
• Automatic Receiver Termination Detection
• Integrated Input and Output Termination
• Independent, Selectable Equalization and Flat Gain
• Hot−Plug Capable
Device
Package
Shipping
NB7NPQ7021MMUTXG UQFN16
3000 /
(Pb−Free) Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
• ESD Protection 4 kV HBM
• Operating Temperature Range: –40°C to 85°C
• Small 3 x 3 x 0.5 mm UQFN16 Package, Flow Through Design that
ease PCB layout
• This is a Pb−Free Device
Typical Applications
• USB3.1 Type−C and Type−A Signal Routing
• Mobile Phone and Tablet
• Computer and Laptop
• Docking Station and Dongle
• Active Cable, Back Planes
• Gaming Console, Smart T.V.
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
December, 2017 − Rev. 1
NB7NPQ7021M/D
NB7NPQ7021M
CTRL_A1
CTRL_A0
Driver
16 15 14 13
A_RX−
A_RX+
A_TX−
A_TX+
Receiver/
Equalizer
A_RX−
A_RX+
B_TX−
B_TX+
1
2
3
4
12 A_TX−
11 A_TX+
10 B_RX−
B_TX−
B_TX+
B_RX−
B_RX+
9
B_RX+
Receiver/
Equalizer
Driver
5
6
7
8
CTRL_B0
CTRL_B1
Figure 1. Logic Diagram of NB7NPQ7021M
Figure 2. UQFN16 Package Pinout
(Top View)
Table 1. PIN DESCRIPTION
Pin Number Pin Name
Type
Description
1
2
3
4
5
A_RX-
A_RX+
B_TX−
B_TX+
VCC
DIFF IN
DIFF OUT
Power
Channel A Differential input pair for 5 / 10 Gbps USB signals. Must be externally AC−coupled.
Channel B Differential output for 5 / 10 Gbps USB signals. Must be externally AC−coupled.
3.3 V power supply. VCC pins must be externally connected to power supply to guarantee
proper operation.
LVCMOS IN Control pin “B0” for equalization and flat gain on Channel B. 4−state input with integrated pull−
up and pull−down resistors. See Table 2.
6
7
8
CTRL_B0
CTRL_B1
GND
LVCMOS IN Control pin “B1” for equalization and flat gain on Channel B. 4−state input with integrated pull−
up and pull−down resistors. See Table 2.
Reference Ground. GND pins must be externally connected to power supply to guarantee
proper operation.
GND
9
B_RX+
B_RX−
A_TX+
A_TX-
VCC
DIFF IN
Channel B Differential input pair for 5 / 10 Gbps USB signals. Must be externally AC−coupled.
10
11
12
13
DIFF OUT
Channel A Differential output for 5 / 10 Gbps USB signals. Must be externally AC−coupled.
Power
LVCMOS IN
LVCMOS IN
GND
3.3 V power supply. VCC pins must be externally connected to power supply to guarantee
proper operation.
Control pin “A0” for equalization and flat gain on Channel A. 4−state input with integrated pull−
up and pull−down resistors. See Table 2.
14
15
16
EP
CTRL_A0
CTRL_A1
GND
Control pin “A1” for equalization and flat gain on Channel A. 4−state input with integrated pull−
up and pull−down resistors. See Table 2.
Reference Ground. GND pins must be externally connected to power supply to guarantee
proper operation.
GND
GND
Exposed pad (EP). EP on the package bottom is thermally connected to the die for improved
heat transfer out of the package. The pad is not electrically connected to the die, but is recom−
mended to be soldered to GND on the PC Board.
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2
NB7NPQ7021M
DEVICE CONFIGURATION
Table 2. CONTROL PIN EFFECTS (Typical Values)
Channel A
Channel B
Equalization
Flat Gain
CTRL_A1
CTRL_A0
CTRL_B1
CTRL_B0
(dB)
5
(dB)
0
Setting #
1
L
L
L
R
F
H
L
L
L
L
R
F
H
L
2
7
0
3
L
L
8
0
4
L
L
9
0
5
R
R
R
R
F
F
F
F
H
H
H
H
R
R
R
R
F
F
F
F
H
H
H
H
10
3
0
6
R
F
H
L
R
F
H
L
2
7
4
2
8
5
2
9
7
2
10
R
F
H
L
R
F
H
L
8
2
11 (Default)
8
−1
−1
−1
−1
−1
−1
12
13
14
15
16
5
7
R
F
H
R
F
H
9
11
7
NOTE: Equalization and DC flat Gain may be set by adjusting the voltage to the control pins. There are 4 specific levels, High “H”, Low
“L”, Rexternal “R”, and Float “F”. Please see Table 7 for voltage levels.
Table 3. ATTRIBUTES
Parameter
ESD Protection
Human Body Model
Charged Device Model
≤ 4 kV
≤ 1.5 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Level 1
UL 94 V−O @ 0.125 in
20330
Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 4. ABSOLUTE MAXIMUM RATINGS Over operating free−air temperature range (unless otherwise noted)
Parameter
Description
Min
−0.5
−0.5
−0.5
−65
Max
4.6
Unit
V
Supply Voltage (Note 2)
V
CC
Voltage range at any input or output terminal
Differential I/O
1.89
V
LVCMOS inputs
V
+ 0.5
V
CC
Storage Temperature Range, T
150
125
85
°C
°C
°C
°C/W
°C
SG
Maximum Junction Temperature, T
J
Operating Ambient Temperature Range, T
−40
A
Junction−to−Ambient Thermal Resistance @ 500 lfm, q (Note 3)
34
JA
Wave Solder, Pb−Free, T
265
SOL
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. All voltage values are with respect to the GND terminals.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
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3
NB7NPQ7021M
Table 5. RECOMMENDED OPERATING CONDITIONS Over operating free−air temperature range (unless otherwise noted)
Parameter
Description
Min
3.135
−40
Nom
Max
3.465
+85
Unit
V
V
CC
Main power supply
3.3
T
A
Operating free−air temperature
AC coupling capacitor
°C
nF
C
75
100
265
AC
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
Table 6. POWER SUPPLY CHARACTERISTICS
Typ
(Note 4)
Parameter
Test Conditions
Min
Max
Unit
mA
mA
mA
I
Active
130
Link in U0 with Super Speed Plus data transmission
Link in U2 or U3 power saving state
CC
U2/U3
2
No USB Connection
No connection state, termination disabled
560
4. TYP values use VCC = 3.3 V, TA = 25_C.
Table 7. LVCMOS CONTROL PIN CHARACTERISTICS 4−State LVCMOS Inputs (CTRL_A0, CTRL_A1, CTRL_B0, CTRL_B1)
Parameter
Test Conditions
Min
Typ
Max
0.1*V
Unit
V
V
IL
DC Input Setting “L”
DC Input Setting “R”
Input pin connected to GND
GND
CC
V
IR
A specified resistor must be applied
between pin and GND
0.23*V
0.56*V
0.33*V
0.43*V
V
CC
CC
CC
V
IF
DC Input Setting “F”
DC Input Setting “H”
Input pin is left floating
0.66*V
0.76*V
V
CC
CC
CC
V
IH
Input pin connected to V
V
CC
V
CC
R
R
Internal pull−up resistance
Internal pull−down resistance
High−level input current
100
200
kW
kW
mA
mA
kW
PU
PD
IH
I
V
V
= 3.465 V
25
IN
I
Low−level input current
= GND, VCC = 3.465 V
−45
IL
IN
R
External Resistor for input setting “R”
68
ext
5. Floating refers to a pin left in an open state, with no external connections.
Table 8. RECEIVER AC/DC CHARACTERISTICS Over operating free−air temperature range (unless otherwise noted)
Parameter
Test Conditions
Min
Typ
Max
Unit
V
Input differential voltage swing
AC−coupled, peak−to−peak differ-
ential
100
1200
mV
PP
RX−DIFF−pp
V
Common−mode voltage bias in the
receiver (DC)
V
W
V
RX−CM
CC
Z
Differential input Resistance (DC)
Present after an USB device is
detected on TX+/TX−
80
20
100
25
120
30
RX−DIFF
Z
Common−mode input Resistance (DC) Present after an USB device is
detected on TX+/TX−
W
RX−CM
Z
Common−mode input Resistance with Present when no USB device is
25
190
200
kW
RX−HIGH−IMP
termination disabled (DC)
detected on TX+
V
Output voltage is considered
squelched below 25 mV.
100
Low Frequency Periodic Signaling
(LFPS) Detect Threshold
mV
PP
300
TH−LFPS−pp
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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4
NB7NPQ7021M
Table 9. TRANSMITTER AC/DC CHARACTERISTICS Over operating free−air temperature range (unless otherwise noted)
Parameter
Test Conditions
Min
Typ
Max
Unit
V
−1 dB compression point Output 100 MHz Sine Wave
swing at 100 MHz
1200
mV
sw_100M
PPd
V
sw_5G
−1 dB compression point Output 5 GHz Sine Wave
swing at 5 GHz
900
mV
PPd
C
TX input capacitance to GND
At 2.5 GHz
1.25
100
pF
TX
Z
Differential output impedance
(DC)
Present after an USB device is detected
on TX+/TX−
80
20
120
30
W
TX−DIFF
Z
Common−mode output imped-
ance (DC)
Present after an USB device is detected
on TX+/TX−
25
40
W
TX−CM
I
TX short circuit current
TX+ or TX− shorted to GND
mA
V
TX−SC
V
Common−mode voltage bias in
the transmitter (DC)
100 mV, 50 MHz, 5 Gbps and 10 Gbps,
prbs 2^7
V
CC
−
V
CC
TX−CM
0.8
V
AC common−mode peak−to−peak Within U0 and at 50 MHz (LFPS)
Voltage swing in active mode
100
10
mV
TX−CM−ACpp
PP
V
Differential voltage swing during
electrical idle
Tested with a high−pass filter
0
mV
TX−IDLE−DIFF−ACpp
PP
V
Voltage change to allow receiver The change in voltage that triggers de-
325
35
600
mV
TX−RXDET
detect
tection of a receiver.
t , t
Output rise, fall time
20% − 80% of differential voltage mea-
sured 1 inch from the output pin, 1 GHz
clock, 800 mV differential amplitude
ps
R
F
t
Output rise, Fall time mismatch
Differential propagation delay
Idle exit time
20% − 80% of differential voltage mea-
sured 1 inch from the output pin
10
ps
ps
ns
ps
RF−MM
t
, t
Propagation delay between 50% level at
input and output
110
10
diff−LH diff−HL
t
50 MHz clock signal, EQ an FG setting
“11 (Default)”
idleExit
t
Idle entry time
50 MHz clock signal, EQ an FG setting
“11 (Default)”
60
idleEntry
Table 10. TIMING AND JITTER CHARACTERISTICS
Parameter
Test Conditions
Min
Typ
Max
Unit
TIMING
Apply 0 V to V , connect USB ter−
mination to TX , apply 3.3 V to
100
ms
t
Time from power applied until
RX termination is enabled
CC
READY
V
CC
, and measure when Z
RX−DIFF
is enabled
JITTER FOR 5 Gbps
T
Total jitter (Notes 6, 7)
Deterministic jitter (Note 7)
Random jitter (Note 7)
EQ = 5 dB, FG = 0 dB,
EQ and FG Setting “LL”
0.20
0.10
0.07
UI
UI
UI
JTX−EYE
D
R
JTX
JTX
JITTER FOR 10 Gbps
T
Total jitter (Notes 6, 7)
Deterministic jitter (Note 7)
Random jitter (Note 7)
EQ = 5 dB, FG = 0 dB,
EQ and FG Setting “LL”
0.22
0.08
0.06
UI
UI
UI
JTX−EYE
D
R
JTX
JTX
−12
6. Includes RJ at 10
.
7. Measured at the ends of reference channel with a K28.5 pattern, VID = 1000 mVpp, −3.5 dB de−emphasis from source.
8. 5 Gbps, UI = 200 ps for 10 Gbps, UI = 100 ps
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5
NB7NPQ7021M
PARAMETER MEASUREMENT DIAGRAMS
Rx−
Rx+
t
VOH
VOL
tdiff−HL
80%
diff−LH
Tx−
20%
t
t
F
R
Tx+
Figure 3. Propagation Delay
Figure 4. Output Rise and Fall Times
APPLICATION GUIDELINES
LFPS Compliance Testing
bias the control pins to the correct voltage to achieve this if
the pin is not connected to a voltage source. The low setting
“L” can be set by pulling the control pin to ground. Likewise
the high setting “H” can be set by pulling the pin high to
As part of USB 3.1 compliance test, the host or peripheral
must transmit a LFPS signal that adheres to the spec
parameters. The NB7NPQ7021M is tested as a part of a USB
compliant system to ensure that it maintains compliance
while increasing system performance.
VCC. The R
setting can be set by adding a 68 K
external
resistor from the control pin to ground. This will bias the
Redriver internal voltage to 33% of VCC.
LFPS Functionality
USB 3.1, Gen1 and Gen2 use Low Frequency Periodic
Signaling (LFPS) to implement functions like exiting
low−power modes, performing warm resets and providing
link training between host and peripheral devices. LFPS
signaling consists of bursts of frequencies ranging between
10 to 50 MHz and can have specific burst lengths or repeat
rates.
Linear Equalization
The linear equalization that the NB7NPQ7021M provides
compensates for losses that occur naturally along board
traces and cable lines. Linear Equalization boosts high
frequencies and lower frequencies linearly so when
transmitting at varying frequencies, the voltage amplitude
will remain consistent. This compensation electrically
counters losses and allows for longer traces to be possible
when routing.
Ping.LFPS for TX Compliance
During the transmitter compliance, the system under test
must transmit certain compliance patterns as defined by the
USB−IF. In order to toggle through these patterns for various
tests, the receiver must receive a ping. LFPS signal from
either the test suite or a separate pattern generator. The
standard signal comprises of a single burst period of 100 ns
at 20 MHz.
DC Flat Gain
DC flat gain equally boosts high and low frequency
signals, and is essential for countering low frequency losses.
DC flat gain can also be used to simulate a higher input
signal from a USB Controller. If a USB controller can only
provide 800 mV differential to a receiver, it can be boosted
to 1128 mV using 3 dB of flat gain.
Control Pin Settings
Control pins A1, A0, B1, and B0 control the flat gain and
the equalization of channels A and B of the NB7NPQ7021M
Device.
The Float (Default) Setting “F” can be set by leaving the
control pins in a floating state. The Redriver will internally
Total Gain
When using Flat Gain with Equalization in a USB
application it is important to make sure that the total voltage
does not exceed 1200 mV. Total gain can be calculated by
adding the EQ gain to the Flat Gain.
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6
NB7NPQ7021M
TYPICAL APPLICATION
Up to 11 inches of FR4
Up to 3 inches of FR4
NB7NPQ7021M
A RX
A TX
100nF
100nF
100nF
100nF
USB 3.1
Receptacle
(Type-C or Type-A)
Receiver/
Equalizer
USB 3.1
Controller
Driver
ESD
Protection
100nF
100nF
330-470nF
330-470nF
Receiver/
Equalizer
220K
Driver
220K
B TX
B RX
Figure 5. USB 3.1 Host Side NB7NPQ7021M Application
Table 11. DESIGN REQUIREMENTS
Design Parameter
Value
3.3 V nominal, (3.135 V to 3.465 V)
Supply Voltage
Operation Mode (Control Pin Selection)
AC Coupling Capacitors
Floating by Default, adjust for application losses See Table 2
100 nF nominal, 75 nF to 265 nF, see Figure 5
68 kW, 10%
R
external
RX Pull Down Resistors at Receptacle
Power Supply Capacitors
200 KW to 220 KW
100 nF to GND close to each Vcc pin, and 10 mF to GND on the Vcc plane
Trace loss of FR4 before NB7NPQ7021M
Trace loss of FR4 after NB7NPQ7021M
Linear Range at 5GHz
Up to 11 inches
Up To 3 inches. Keep as short as possible for best performance.
900 mV differential
−1 dB, 0 dB, 2 dB
3 to 11 dB
DC Flat Gain Options
Equalization Options
Differential Trace Impedance
90 W 10%
9. Trace loss of FR4 was estimated to have 1 dB of loss per 1 inch of FR4 length with matched impedance and no VIAS.
Typical Layout Practices
plane. This will help reduce EMI and noise on the data
lines.
• RX and TX pairs should maintain as close to a 90 W
differential impedance as possible.
• Limit the number of vias used on each data line. It is
suggested that 2 or fewer are used.
• Routing angles should be obtuse angles and kept to 135
degrees or larger.
• To minimize crosstalk, TX and RX data lines should be
kept away from other high speed signals.
• Traces should be routed as straight and symmetric as
possible.
• RX and TX differential pairs should always be placed
and routed on the same layer directly above a ground
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NB7NPQ7021M
VCC Bus Requirements
Place the 100nF and
10uF capacitors to
ground on the VCC Bus
near the NB7NPQ7021M
to filter noise to the
VCC pins.
3.3V
VCC
Vcc, GND, Float, or 68KR
100n
10u
Vcc, GND, Float, or 68KR
3.3V
USB VBUS
1
2
3
8
VBUS
D−
USB Type−A Connector
U9
U2
D−
D+
USB3.1 Host
D+
1
2
3
4
12
TX−
TX+
RX−
Host SSTX−
Host SSTX+
Host SSRX−
Host SSRX+
A_RX−
A_RX+
B_TX−
B_TX+
A_TX−
SSTX−
100n
100n
100n
100n
11
9
5
6
A_TX+
SSTX+
SSRX−
SSRX+
100n
NB7NPQ7021M
10
9
B_RX−
B_RX+
330n
330n
RX+
100n
7
4
ESD8704
GND_Drain
GND
220K
220K
Vcc, GND, Float, or 68K
3.3V
Vcc, GND, Float, or 68K
RX coupling capacitors are suggested to remain 330 nF or higher. In some cases; such as when
the NB7NPQ7021M is utilized with a multiplexer, a higher capacitor value may be necessary.
Figure 6. Typical Application Diagram for Implementing a USB 3.1 Type−A Port
VCC Bus Requirements
Place the 100nF and
10uF capacitors to
ground on the VCC Bus
near the NB7NPQ7021M
to filter noise to the
VCC pins.
Control Vcc, GND, Float, or 68KR
3.3V
VCC
Control Vcc, GND, Float, or 68KR
3.3V
100n
10u
USB Type−C Connector
5
TX1−
TX1+
RX1−
RX1+
TX2−
TX2+
RX2−
RX2+
TX1−
TX1+
RX1−
RX1+
TX2−
T2X+
RX2−
RX2+
220n
220n
330n
330n
220n
220n
330n
330n
5
6
7
8
9
1
2
3
4
12
11
10
9
6
USB3_TX4_N
USB3_TX4_P
USB3_RX4_N
USB3_RX4_P
A_RX−
A_RX+
B_TX−
B_TX+
A_TX−
A_TX+
B_RX−
B_RX+
1
2
3
4
1
2
3
4
7
100n
100n
100n
100n
220n
220n
330n
330n
8
2:1 MUX
NB7NPQ7021M
9
10
11
12
10
11
12
1Meg
3.3V
ESD8704
ESD8704
220K
220K
Control Vcc, GND, Float, or 68KR
1Meg
220K
220K
Control Vcc, GND, Float, or 68KR
1Meg
1Meg
Note: For the best performance it is recommended to place two redrivers after the
multiplexer. Only the most commonly used implementation can be seen in Figure 7.
Figure 7. Typical Application Diagram for Implementing a USB 3.1 Type−C Port
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8
NB7NPQ7021M
PACKAGE DIMENSIONS
UQFN16 3x3, 0.5P
CASE 523AF
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
B
A
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L
PIN ONE
REFERENCE
DETAIL A
OPTIONAL CONSTRUCTION
2X SCALE
MILLIMETERS
E
DIM MIN
MAX
0.55
0.05
A
A1
A3
b
0.45
0.00
0.127 REF
0.20 0.30
3.00 BSC
2X
0.10
C
DETAIL B
OPTIONAL CONSTRUCTION
4X SCALE
2X
D
D2
E
1.60
3.00 BSC
1.80
0.10
C
TOP VIEW
E2
e
1.60
0.50 BSC
1.80
A
DETAIL B
K
L
0.20
0.30
−−−
0.50
0.05
0.05
C
C
A3
C
17X
SOLDERING FOOTPRINT*
A1
NOTE 4
SEATING
PLANE
0.50
PITCH
SIDE VIEW
D2
DETAIL A
16X
0.60
5
K
2X
1.55
2X
3.30
e/2
e
9
E2
1
1
16X
0.29
13
16X L
DIMENSIONS: MILLIMETERS
16X
b
0.10
0.05
C
A
B
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
C
NOTE 3
BOTTOM VIEW
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