NCV7703B [ONSEMI]
Triple Half-Bridge Driver with SPI Control; 三重半桥驱动器，带有SPI控制
| 型号： | NCV7703B |
| 厂家： | 
ONSEMI |
| 描述： | Triple Half-Bridge Driver with SPI Control |
| 文件： | 总16页 (文件大小：199K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCV7703B
Triple Half-Bridge Driver
with SPI Control
The NCV7703B is a fully protected Triple Half−Bridge Driver
designed specifically for automotive and industrial motion control
applications. The three half−bridge drivers have independent control.
This allows for high side, low side, and H−Bridge control. H−Bridge
control provides forward, reverse, brake, and high impedance states.
The drivers are controlled via a standard Serial Peripheral Interface
(SPI). This device is fully compatible with ON Semiconductor’s
NCV7708 Double Hex Driver.
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MARKING
DIAGRAM
14
SOIC−14
D2 SUFFIX
CASE 751A
Features
NCV7703BG
AWLYWW
14
• Ultra Low Quiescent Current in Sleep Mode, 1 mA for V and V
S
CC
1
• Power Supply Voltage Operation down to 5 V
1
• 3 High−Side and 3 Low−Side Drivers Connected as Half−Bridges
• Internal Free−Wheeling Diodes
NCV7703B = Specific Device Code
A
WL
Y
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
• Configurable as H−Bridge Drivers
• 0.5 A Continuous (1 A peak) Current
• R
= 0.8 W (typ)
DS(on)
• 5 MHz SPI Control with Daisy Chain Capability
• Compliance with 5 V and 3.3 V Systems
• Overvoltage and Undervoltage Lockout
• Fault Reporting
PIN CONNECTIONS
GND
OUT3
GND
OUT1
OUT2
• 1.4 A Overcurrent Threshold Detection with Optional Shutdown
• 3 A Current Limit with Auto Shutdown
V
S
CSB
SI
V
EN
CC
• Overtemperature Warning and Protection Levels
• Internally Fused Leads in SOIC−14 Package for Better Thermal
Performance
SCLK
GND
SO
GND
• ESD Protection up to 6 kV
• These are Pb−Free Devices
ORDERING INFORMATION
Device
Package
Shipping†
Typical Applications
• Automotive
NCV7703BD2G
55 Units / Rail
SOIC−14
(Pb−Free)
• Industrial
• DC Motor Management
NCV7703BD2R2G
2500 /
Tape & Reel
SOIC−14
(Pb−Free)
V
S
V
S
V
S
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
M
M
OUT1
OUT2
OUT3
Figure 1. Cascaded Application
© Semiconductor Components Industries, LLC, 2010
1
Publication Order Number:
April, 2010 − Rev. 0
NCV7703B/D
NCV7703B
V
S
DRIVE 1
V
S
V
S
EN
clk
ENABLE
OSC
clk
Charge
Pump
High−Side
Driver
Control
Logic
Waveshaping
V
CC
OUT1
Reference
& Bias
Fault
Detect
V
S
UVLO
Low−Side
Driver
Channel Enable
Waveshaping
SO
Under−Load
Overcurrent
Thermal
16 Bit
Logic
and
SI
Warning/Shutdown
SPI
SCLK
Latch
V
S
clk
DRIVE 2
Channel Enable
Fault
CSB
OUT2
OUT3
V
Undervoltage
Lockout
S
V
S
DRIVE 3
Channel Enable
Fault
clk
V
S
Overvoltage
Lockout
GND
Figure 2. Block Diagram
PACKAGE PIN DESCRIPTION
Pin #
1
Symbol
GND*
Description
Ground. Connect all grounds together.
Half Bridge Output 3.
2
OUT3
3
V
Power Supply input for the output drivers and internal supply voltage.
Chip Select Bar. Active low serial port operation.
Serial Input
S
4
CSB
SI
5
6
SCLK
GND*
GND*
SO
Serial Clock
7
Ground. Connect all grounds together.
Ground. Connect all grounds together.
Serial Output
8
9
10
11
12
13
14
EN
Enable. Logic high wakes the IC up from a sleep mode.
Power supply input for internal logic.
Half Bridge Output 2.
V
CC
OUT2
OUT1
GND*
Half Bridge Output 1.
Ground. Connect all grounds together.
*Pins 1, 7, 8, and 14 are internally shorted together. It is recommended to also short these pins externally.
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2
NCV7703B
ENABLE
VBAT
WDI
Wake Up
RESET
Vout
D1*
1N4001
NCV8518
−
D2**
Delay
120k
GND
22 mF
10 mF
V
CC
V
S
OUT1
OUT2
OUT3
EN
M
M
CSB
SI
NCV7703B
SCLK
SO
GND
GND
GND
GND
GND
* D1 optional. For use where reverse battery protection is required.
** D2 optional. For use where load dump exceeds 40V.
Figure 3. Application Circuit
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3
NCV7703B
MAXIMUM RATINGS
Rating
Value
Unit
Power Supply Voltage (V )
V
S
(DC)
−0.3 to 40
−1
(AC), t < 500 ms, Ivs > −2 A
Output Pin OUTx
(DC)
(AC), t < 500 ms, IOUTx > −2 A
V
−0.3 to 40
−1
Pin Voltage
(Logic Input pins, SI, SCLK, CSB, SO, EN, V
−0.3 to 7
V
A
)
CC
Output Current (OUTx)
(DC)
−1.8 to 1.8
(AC) (50 ms pulse, 1 s period)
Internally Limited
Electrostatic Discharge, Human Body Model,
V , OUT1, OUT2, OUT3 (Note 3)
S
6
kV
kV
V
Electrostatic Discharge, Human Body Model,
all other pins (Note 3)
2
Electrostatic Discharge, Machine Model,
V , OUT1, OUT2, OUT3 (Note 3)
S
300
200
Electrostatic Discharge, Machine Model,
all other pins (Note 3)
V
Electrostatic Discharge, Charge Device Model (Note 3)
Operating Junction Temperature
1
kV
°C
°C
−
−40 to 150
−55 to 150
MSL3
Storage Temperature Range
Moisture Sensitivity Level (MAX 260°C Processing)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Thermal Parameters
Test Conditions (Typical Value)
Unit
14 Pin Fused SOIC Package
min−pad board
1″ pad board
(Note 1)
(Note 2)
Junction−to−Lead (psi−JL8, Y ) or Pins 1, 7, 8, 14
23
22
83
°C/W
°C/W
JL8
Junction−to−Ambient (R , q
)
122
q
JA JA
2
1. 1−oz copper, 67 mm copper area, 0.062″ thick FR4.
2
2. 1−oz copper, 645 mm copper area, 0.062″ thick FR4.
3. This device series incorporates ESD protection and is tested by the following methods:
ESD HBM tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD MM tested per AEC−Q100−003 (EIA/JESD22−A115)
ESD CDM tested per EIA/JES D22/C101, Field Induced Charge Model
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4
NCV7703B
ELECTRICAL CHARACTERISTICS
(−40°C ≤ T ≤ 150°C, 5.5 V ≤ V ≤ 40 V, 3 V ≤ V ≤ 5.25 V, EN = V , unless otherwise specified)
J
S
CC
CC
Characteristic
Conditions
Min
Typ
Max
Unit
GENERAL
Supply Current (V )
V
S
= 13.2 V, OUTx = 0 V
−
1.0
5.0
mA
S
Sleep Mode (Note 5)
EN = SI = SCLK = 0 V, CSB = V
CC
0 V < V < 5.25 V
CC
(T = −40°C to 85°C)
J
V
S
= 13.2 V, OUTx = 0 V
−
−
2.0
EN = SI = SCLK = 0 V, CSB = V
0 V < V < 5.25 V, T = 25°C
CC
CC
J
Supply Current (V )
Active Mode
EN = V , 5.5 V < V < 35 V
No Load
−
−
2.0
0
4.0
2.5
mA
mA
mA
V
S
CC
S
Supply Current (V
)
V
CC
= CSB, EN = SI = SCLK = 0 V
CC
Sleep Mode (Note 6)
(T = −40°C to 85°C)
J
Supply Current (V
Active Mode
)
EN = V
−
1.5
2.80
3.0
CC
CC
V
V
Power−On−Reset Threshold
2.60
3.00
CC
Undervoltage Detection
Threshold V decreasing
4.3
100
4.7
−
5.1
400
V
mV
S
S
Hysteresis
V
Overvoltage Detection
Threshold V increasing
34.0
1.5
37.5
3.5
40.0
5.5
V
°C
S
S
Hysteresis
Thermal Warning (Note 4)
Thermal Shutdown (Note 4)
Threshold
Hysteresis
120
−
145
30
170
−
Threshold
Hysteresis
155
−
175
30
195
−
°C
Ratio of Thermal Shutdown to Thermal
Warning temperature (Note 4)
1.05
1.20
−
°C/°C
OUTPUTS
Output R
(Source)
I
= −500 mA
DS(on)
out
V
= 13.2 V, T = 25°C
−
−
−
−
−
0.8
−
0.95
1.5
1.7
−
W
W
W
W
W
S
J
V
S
= 13.2 V
8 V ≤ V ≤ 40 V
−
S
5.5 V ≤ V ≤ 8 V, T = 25°C
1.3
−
S
J
5.5 V ≤ V ≤ 8 V
2.0
S
Output R
(Sink)
I
= 500 mA
DS(on)
out
V
= 13.2 V, T = 25°C
−
−
0.8
−
0.95
1.5
1.7
−
W
W
S
J
V
S
= 13.2 V
8 V ≤ V ≤ 40 V
−
−
W
S
5.5 V ≤ V ≤ 8 V, T = 25°C
−
1.3
−
W
S
J
5.5 V ≤ V ≤ 8 V
−
2.0
−
W
S
Source Leakage Current
Sum of I(OUTx) x = 1, 2, 3
OUTx = 0 V, V = 40 V, EN = 0 V
−5.0
−
mA
S
CSB = V
CC
0 V < V < 5.25 V
CC
Sum(I(OUTx)
OUTx = 0 V, V = 40 V, EN = 0 V
−1.0
−
−
S
CSB = V
CC
0 V < V < 5.25 V, T = 25°C
CC
J
Sum(I(OUTx)
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5
NCV7703B
ELECTRICAL CHARACTERISTICS
(−40°C ≤ T ≤ 150°C, 5.5 V ≤ V ≤ 40 V, 3 V ≤ V ≤ 5.25 V, EN = V , unless otherwise specified)
J
S
CC
CC
Characteristic
Conditions
Min
Typ
Max
Unit
OUTPUTS
Sink Leakage Current
OUTx = V = 40 V, EN = 0 V
−
−
300
mA
S
CSB = V
CC
0 V < V < 5.25 V
CC
OUTx = V = 13.2 V, EN = 0 V
−
−
10
S
CSB = V
CC
0 V < V < 5.25 V, T = 25°C
CC
J
Over Current Shutdown Threshold
Current Limit
Source
Sink
−1.8
−1.4
−1.0
A
A
1.0
1.4
1.8
Source
Sink
−5.0
2.0
−3.0
3.0
−2.0
5.0
Under Load Detection Threshold
Source
Sink
−15
−7.0
−2.0
mA
V
3.0
7.0
15
Power Transistor Body Diode Forward Voltage I = 500 mA
−
0.9
1.3
f
4. Thermal characteristics are not subject to production test
5. For temperatures above 85°C, refer to Figure 4.
6. For temperatures above 85°C, refer to Figure 5.
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6
NCV7703B
ELECTRICAL CHARACTERISTICS
(−40°C ≤ T ≤ 150°C, 5.5 V ≤ V ≤ 40 V, 3 V ≤ V ≤ 5.25 V, EN = V , unless otherwise specified)
J
S
CC
CC
Characteristic
Conditions
Min
Typ
Max
Unit
LOGIC INPUTS (EN, SI, SCLK, CSB)
Input Threshold
%V
CC
High
Low
−
30
−
−
70
−
Input Hysteresis
100
5.0
−50
−
350
25
600
50
mV
mA
mA
pF
Input Pulldown Current (EN, SI, SCLK)
Input Pullup Current (CSB)
Input Capacitance (Note 7)
LOGIC OUTPUT (SO)
Output High
EN = SI = SCLK = V
CSB = 0 V
CC
−25
10
−5
15
I
I
= 1 mA
V
– 1.0
V – 0.7
CC
−
V
V
out
CC
Output Low
= −1.6 mA
−
−10
−
0.2
−
0.4
10
15
out
Tri−state Leakage
CSB = V , 0 V v SO v V
mA
pF
CC
CC
Tri−state Input Capacitance (Note 7)
TIMING SPECIFICATIONS
CSB = V
10
CC
Overcurrent Shutdown Delay Time
ms
Source
Sink
10
10
25
25
50
50
Current Limit Fault Delay
Under Load Detection Delay Time
High Side Turn On Time
High Side Turn Off Time
Low Side Turn On Time
Low Side Turn Off Time
High Side Rise Time
V
> 8 V
−
200
−
200
350
7.5
3.0
6.5
3.0
5.0
2.0
1.0
1.0
−
−
600
15
6.0
15
6.0
10
5.0
3.0
3.0
−
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
V
S
= 13.2 V, R
= 13.2 V, R
= 13.2 V, R
= 13.2 V, R
= 13.2 V, R
= 13.2 V, R
= 13.2 V, R
= 13.2 V, R
= 25 W
= 25 W
= 25 W
= 25 W
= 25 W
= 25 W
= 25 W
= 25 W
load
load
load
load
load
load
load
load
−
−
−
−
High Side Fall Time
−
Low Side Rise Time
−
Low Side Fall Time
−
NonOverlap Time
High Side Turn Off to Low Side Turn On
Low Side Turn Off to High Side Turn On
1.0
1.0
NonOverlap Time
−
−
7. Not production tested.
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7
NCV7703B
ELECTRICAL CHARACTERISTICS
(−40°C ≤ T ≤ 150°C, 5.5 V ≤ V ≤ 40 V, 3 V ≤ V ≤ 5.25 V, EN = V , unless otherwise specified)
J
S
CC
CC
SERIAL PERIPHERAL INTERFACE
Timing Chart #
(See Figure 6)
Characteristic
SCLK Frequency
Conditions
Min
Typ
Max
Unit
MHz
ns
V
V
= 5 V
= 5 V
−
−
−
5
CC
SCLK Clock Period
−
−
200
500
−
−
−
−
CC
V
CC
= 3.3 V
Maximum Input Capacitance (Note 8)
SCLK High Time
SI, SCLK
−
1
2
−
−
−
−
15
−
pF
ns
ns
ns
85
85
SCLK Low Time
−
SCLK Setup Time
3
4
85
85
−
−
−
−
SI Setup Time
SI Hold Time
11
12
50
50
−
−
−
−
ns
ns
ns
CSB Setup Time
5
6
100
100
−
−
−
−
CSB High Time (Note 9)
SO enable after CSB falling edge (Note 8)
SO disable after CSB rising edge (Note 8)
SO Rise Time
7
8
200
−
−
−
−
ns
ns
ns
ns
ns
ns
50
50
25
25
50
9
−
−
V
V
= 5 V, C
= 40 pF
= 40 pF
−
−
10
10
20
CC
load
SO Fall Time
= 5 V, C
−
−
CC
load
SO Valid Time (Note 8)
SCLK ↑ to SO 50%
10
−
8. Not tested in production.
9. Minimum high time of CSB between two successive SPI commands.
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8
NCV7703B
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
7.0
6.0
5.0
4.0
3.0
2.0
V
S
= 13.2 V
V
= 0 V
CC
V
CC
= 5.25 V
1.0
0
V
= 5.25 V
CC
0
−40 −20
0
20 40
60 80 100 120 140 160
−40 −20
0
20 40
60 80 100 120 140 160
T , TEMPERATURE (°C)
J
T , TEMPERATURE (°C)
J
Figure 4. VS Sleep Supply Current vs. Temperature
Figure 5. VCC Sleep Supply Current vs. Temperature
Detailed SPI Timing
4
7
CSB
6
5
SCLK
1
2
3
CSB
SO
8
9
SI
12
SCLK
11
10
SO
Figure 6. SPI Timing Waveforms
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NCV7703B
TYPICAL CHARACTERISTICS
140
120
100
80
1 oz Cu
2 oz Cu
60
40
20
0
0
100 200 300 400 500 600 700 800
2
COPPER HEAT SPREADING AREA (mm )
Figure 7. qJA vs. Copper Spreader Area,
14 Lead SON (fused leads)
1000
100
10
2
Cu Area = 100 mm 1.0 oz
2
200 mm 1.0 oz
2
300 mm 1.0 oz
2
400 mm 1.0 oz
2
1
500 mm 1.0 oz
0.1
0.01
0.000001 0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
TIME (sec)
Figure 8. Transient Thermal Response to a
Single Pulse 1 oz Copper (Log−Log)
140
120
2
Cu Area = 100 mm 1.0 oz
2
200 mm 1.0 oz
100
80
2
300 mm 1.0 oz
2
400 mm 1.0 oz
2
500 mm 1.0 oz
60
40
20
0
0.000001 0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
TIME (sec)
Figure 9. Transient Thermal Response to a
Single Pulse 1 oz Copper (Semi−Log)
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NCV7703B
SPI Communication
Frame Detection
Standard 16−bit communication has been implemented to
this IC to turn drivers on/off, and to report faults. (See
Figure 11). The LSB (Least Significant Bit) is clocked in
first.
Input word integrity (SI) is evaluated by the use of a frame
consistency check. The word frame length is compared to an
h x 16 bit acceptable word length before the data is latched
into the input register. This guarantees the proper word
length has been imported and allows for daisy chain
operation applications.
The frame length detector is enabled with the CSB falling
edge and the SCLK rising edge.
SCLK must be low during the CSB rising edge. The fault
register is cleared with a valid frame detection. Existing
faults are re−latched after the fault filter time.
Communication is Implemented as Follows:
1. CSB goes low to allow serial data transfer.
2. A 16 bit word is clocked (SCLK) into the SI
(Serial Input) pin.
3. CSB goes high to transfer the clocked in
information to the data registers.
NOTE: SO is tristate when CSB is high.
Frame detection starts
after the CSB falling edge
and the SCLK rising edge.
Frame detection mode ends with
CSB rising edge.
CSB
SCLK
SI
SRR OUTL1 OUTH1 OUTL2 OUTH2 OUTL3 OUTH3
X
X
X
X
X
X
OCD
14
X
OVLO
16
Internal Counter
1
2
3
4
5
6
7
8
9
10
11
12
13
15
Valid 16 bits shown
Figure 10. Frame Detection
CSB
SRR OUTL1 OUTH1 OUTL2 OUTH2 OUTL3 OUTH3
X
X
X
X
X
X
X
X
X
OCD
X
OVLO
PSF
SI
SCLK
TW
OUTL1 OUTH1 OUTL2 OUTH2 OUTL3 OUTH3
X
X
X
OLD
ULD
SO
Figure 11. SPI Communication Frame Format
Table 1 defines the programming bits and diagnostic bits.
Figure 11 displays the timing diagram associated with
Table 1. Fault information is sequentially clocked out the
SO pin of the NCV7703B as programming information is
clocked into the SI pin of the device. Daisy chain
communication between SPI compatible IC’s is possible by
connection of the Serial Output pin (SO) to the input of the
sequential IC (SI) (Reference the Daisy Chain Section).
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NCV7703B
Table 1. SPI BIT DESCRIPTION
Input Data
Output Data
Bit Number
Bit Description
Bit Status
Bit Number
Bit Description
Bit Status
0 = No Fault
1 = Fault
15
Over Voltage Lock Out
Control (OVLO)
0 = Disable
1 = Enable
15
Power Supply Fail Signal
(PSF for OVLO or UVLO)
14
13
Not Used
14
13
Under Load Detect Signal (ULD)
Over Load Detect Signal (OLD)
0 = No Fault
1 = Fault
Over Current Detection Shut
Down Control (OCD)
0 = Disable
1 = Enable
0 = No Fault
1 = Fault
12
11
10
9
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
OUTH3
12
11
10
9
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
OUTH3
8
8
7
7
6
0 = Off
1 = On
6
0 = Off
1 = On
5
4
3
2
1
0
OUTL3
OUTH2
0 = Off
5
4
3
2
1
0
OUTL3
OUTH2
0 = Off
1 = On
1 = On
0 = Off
0 = Off
1 = On
1 = On
OUTL2
0 = Off
OUTL2
0 = Off
1 = On
1 = On
OUTH1
0 = Off
OUTH1
0 = Off
1 = On
1 = On
OUTL1
0 = Off
OUTL1
0 = Off
1 = On
1 = On
Status Register Reset (SRR)
0 = No Reset
1 = Reset
Thermal Warning (TW)
0 = Not in TW
1 = In TW
DETAILED OPERATING DESCRIPTION
Power Up/Down Control
General
The NCV7703B Triple Half Bridge Driver provides drive
capability for 3 Half−Bridge configurations. Each output
drive is characterized for a 500 mA load and has a typical
1.4 A surge capability. Strict adherence to integrated circuit
die temperature is necessary, with a maximum die
temperature of 150°C. This may limit the number of drivers
enabled at one time. Output drive control and fault reporting
are handled via the SPI (Serial Peripheral Interface) port.
An Enable function (EN) provides a low quiescent sleep
current mode when the device is not being utilized. A pull
down is provided on the EN, SI and SCLK inputs to ensure
they default to a low state in the event of a severed input
signal. A pull−up is provided on the CSB input disabling SPI
communication in the event of an open CSB input.
A feature incorporated in the IC is an under voltage
lockout circuit that prevents the output drivers from turning
on unintentionally. V
and V are monitored for
CC
S
undervoltage conditions supporting a smooth turn−on
transition. All drivers are initialized in the off (high
impedance) condition, and will remain off during a V or
CC
V
S
undervoltage condition. This allows power up
sequencing of V , and V up to the user. Once V is out
CC
S
CC
of UVLO, SPI communication can begin regardless of the
voltage on V . However, drivers will remain off if V is in
S
S
an undervoltage condition. Hysteresis in the UVLO circuits
results in glitch free operation during power up/down.
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NCV7703B
H−Bridge Driver Configuration
been exceeded for a duration greater than 200 ms, regardless
of the OLD input bit status. The OUTx output bit will report
a “0” indicating which driver encountered the hard short.
The OLD status bit will be set and will remain set until a new
SRR input SPI command is executed.
The NCV7703B has the flexibility of controlling each half
bridge driver independently. This allows for high side, low
side and H−bridge control. H−bridge control provides
forward, reverse, brake and high impedance states.
Overvoltage Clamping − Driving Inductive Loads
Each output is internally clamped to ground and Vs by
internal free wheeling diodes. The diodes have ratings that
complement the FETs they protect.
Under−Load Detection (Table 3)
The under−load detection circuit monitors the current
from each output driver. A minimum load current (this is the
maximum open circuit detection threshold) is required when
the drivers are turned on. If the under−load detection
threshold has been detected for more than the under−load
delay time, the ULD bit (output bit #14) will be set to a “1”.
The under load bit is reset with SRR.
Overcurrent Shutdown Threshold Detection (Table 2)
The state of input bit 13 (OCD) selects driver reaction
when reaching overcurrent shutdown threshold. With a “0”
for input bit 13, the OLD status bit will be set to “1” when
the level exceeds the overcurrent shutdown shut−down
threshold and the driver will remain on. With a “1” for input
bit 13, the output driver shuts off when the overcurrent
shutdown threshold is exceeded and can only be turned back
on via the SPI port with a SPI command that includes an SRR
= 1. Note: high currents could cause a high rise in die
temperature. Devices will not be allowed to turn on if the die
temperature exceeds the thermal shutdown temperature.
Overvoltage Shutdown (Table 4)
Overvoltage lockout circuitry monitors the voltage on the
V pin. The response to an overvoltage condition is selected
S
by SPI input bit 15. PSF output bit 15 is set when a V
S
overvoltage condition exists. If input bit 15 (OVLO) is set
to “1”, all outputs will turn off during this overvoltage
condition. Turn On/Off status is maintained in the logic
circuitry, so that when proper input voltage level is
reestablished, the programmed outputs will turn back on.
The PSF output bit is reset with SRR.
Current Limit Fault
The current limit fault circuit will shut down the offending
output driver when the Current Limit (Source or Sink) has
Table 2. INPUT BIT 13, OVERCURRENT DETECTION SHUT DOWN CONTROL AND RESPONSE
OLD Input
Bit 13 Set
Typical Load Current
Condition
Output Bit 13 OLD Status
OUTx Status
Unchanged
0
0
0
1
1
I
L
≤ 1.4 A
0
1.4 A < I ≤ 3 A
1 (Need SRR to reset)
1 (Need SRR to reset)
0
Unchanged
L
I
≥ 3 A, for 200 ms (typ)
OUTx Latched Off (Need SRR to reset)
Unchanged
L
I
L
≤ 1.4 A
I > 1.4 A, for 25 ms (typ)
L
1 (Need SRR to reset)
OUTx Latched Off (Need SRR to reset)
Table 3. INPUT BIT 14, UNDER LOAD DETECTION SHUT DOWN
OUTx ULD Set
Output Data Bit 14, Under Load Detect (ULD) Status
OUTx Status
Unchanged
Unchanged
0
1
0
1 (Need SRR to reset)
Table 4. INPUT BIT 15, OVERVOLTAGE LOCK OUT (OVLO) SHUT DOWN
OVLO Input
Bit 15
V
OVLO
Output Data Bit 15 Power
Supply Fail (PSF) Status
S
Condition
OUTx Status
Unchanged
Unchanged
Unchanged
0
0
1
1
0
1
0
1
0
1 (Need SRR to reset)
0
1 (Need SRR to reset)
All Outputs Shut Off (Remain off until V is out of OVLO)
S
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13
NCV7703B
Thermal Shutdown
Three independent thermal shutdown circuits are featured
(one common sensor for each HS and LS transistor pair).
Each sensor has two temperature levels; Level 1, Thermal
Warning sets the “TW” status bit to a 1 and would have to
be reset with a command that includes the SRR after the IC
cools to a temperature below Level 1. The output will remain
on in this condition.
If the IC temperature reaches Level 2, Over Temperature
Shutdown, all drivers are latched off. It can be reset only
after the part cools below the shutdown temperature,
(including thermal hysteresis) with a turn−on command that
includes the SRR set bit.
software polling of this bit will allow for load control and
possible prevention of thermal shutdown conditions.
Thermal warning information can be retrieved
immediately without performing a complete SPI access
cycle. Figure 12 below displays how this is accomplished.
Bringing the CSB pin from a high to low condition
immediately displays the information on the Output Data Bit
0, thermal warning, even in the absence of an SCLK signal.
As the temperature of the NCV7703B changes from a
condition from below the thermal warning threshold to
above the thermal warning threshold, the state of the SO pin
changes and this level is available immediately when the
CSB goes low. A low on SO indicates there is no thermal
warning, while a high indicates the IC is above the thermal
warning threshold. This warning bit is reset by setting SRR
to “1”.
The output data bit 0, Thermal Warning, will latch and
remain set, even after cooling, and is reset by sending a SPI
command to reset the status register (SRR, input 0 set to
“1”). Since thermal warning precedes a thermal shutdown,
CSB
CSB
SCLK*
SCLK*
Tristate Level
SO
SO
TWH
NTW
Tristate Level
Thermal Warning High
No Thermal Warning
*SCLK can be high or low in order to maintain the thermal information on SO. Toggling SCLK will cause other output bits to shift out.
TWH = Thermal Warning High
NTW = No Thermal Warning
Figure 12. Access to Temperature Warning Information
Applications Drawing
Daisy Chain
The NCV7703B is capable of being setup in a daisy chain
configuration with other similar devices which include
additional NCV7703B devices as well as the NCV7708
Double Hex Driver. Particular attention should be focused
on the fact that the first 16 bits which are clocked out of the
SO pin when the CSB pin transitions from a high to a low
will be the Diagnostic Output Data. These are the bits
representing the status of the IC and are detailed in the SPI
Bit Description Table. Additional programming bits should
be clocked in which follow the Diagnostic Output bits. Word
length must be h x 16 due to the use of frame detection.
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14
NCV7703B
CSB SCLK
NCV7703B
CSB SCLK
CSB SCLK
NCV7708B
CSB SCLK
NCV7708B
NCV7703B
SI
SO
SI
SO
SI
SO
SI
SO
Figure 13. Daisy Chain Operation
Parallel Control
A more efficient way to control multiple SPI compatible
devices is to connect them in a parallel fashion and allow
each device to be controlled in a multiplex mode. The
diagram below shows a typical connection between the
microprocessor or microcontroller and multiple SPI
compatible devices. In a daisy chain configuration, the
programming information for the last device in the serial
string must first pass through all the previous devices. The
parallel control setup eliminates that requirement, but at the
cost of additional control pins from the microprocessor for
each individual CSB pin for each controllable device. Serial
data is only recognized by the device that is activated
through its respective CSB pin.
V
S
OUTx
NCV7703B
SI
SCLK
SI
SCLK
CSB
SO
OUT1
OUT2
OUT3
SO
OUTx
CSB
NCV7703B
SI
chip1
CSB
SCLK
CSB
SO
chip2
OUT1
OUT2
OUT3
CSB
chip3
GND
NCV7703B
SI
SCLK
CSB
SO
OUT1
OUT2
OUT3
Figure 15. High−Side / Low−Side Application Drawing
Figure 14. Parallel Control
Any combination of H−bridge and high or low−side
drivers can be designed in. This allows for flexibility in
many systems.
Additional Application Setup
In addition to the cascaded H−Bridge application shown
in Figure 1, the NCV7703B can also be used as a high−side
driver or low−side driver (Figure 15).
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15
NCV7703B
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−A−
14
8
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−B−
P 7 PL
M
M
B
0.25 (0.010)
7
1
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
F
R X 45
_
C
A
B
C
D
F
G
J
K
M
P
R
8.55
3.80
1.35
0.35
0.40
8.75 0.337 0.344
4.00 0.150 0.157
1.75 0.054 0.068
0.49 0.014 0.019
1.25 0.016 0.049
0.050 BSC
0.25 0.008 0.009
0.25 0.004 0.009
−T−
J
M
K
SEATING
1.27 BSC
D 14 PL
PLANE
0.19
0.10
0
M
S
S
0.25 (0.010)
T B
A
7
0
7
_
_
_
_
5.80
0.25
6.20 0.228 0.244
0.50 0.010 0.019
SOLDERING FOOTPRINT*
7X
7.04
14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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