NCV8411DTRKG [ONSEMI]
具有浪涌电流管理功能的自保护低压侧驱动器;
| 型号： | NCV8411DTRKG |
| 厂家： | 
ONSEMI |
| 描述： | 具有浪涌电流管理功能的自保护低压侧驱动器 驱动 驱动器 |
| 文件： | 总14页 (文件大小：317K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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www.onsemi.com
onsemi andꢀꢀꢀꢀꢀꢀꢀand other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or
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product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without
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NCV8411
Self-Protected Low Side
Driver with In-Rush Current
Management
The NCV8411 is a three terminal protected Low−Side Smart
Discrete FET. The protection features include Delta Thermal
Shutdown, overcurrent, overtemperature, ESD and integrated Drain to
Gate clamping for over voltage protection. The device also offers fault
indication via the gate pin. This device is suitable for harsh automotive
environments.
www.onsemi.com
V
I MAX
D
(Limited)
DSS
(Clamped)
R
TYP
DS(ON)
42 V
23 mW @ 10 V
45 A
Features
• Short Circuit Protection with In−Rush Current Management
• Delta Thermal Shutdown
• Thermal Shutdown with Automatic Restart
• Over Voltage Protection
• Integrated Clamp for Over Voltage Protection and Inductive
DPAK
CASE 369C
STYLE 2
Switching
• ESD Protection
• dV/dt Robustness
• Analog Drive Capability (Logic Level Input)
MARKING DIAGRAM
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
1
1 = Gate
2 = Drain
3 = Source
AYWW
NCV
8411G
2
3
A
Y
= Assembly Location
= Year
Typical Applications
WW
G
= Work Week
= Pb−Free Package
• Switch a Variety of Resistive, Inductive and Capacitive Loads
• Can Replace Electromechanical Relays and Discrete Circuits
• Automotive / Industrial
ORDERING INFORMATION
Drain
†
Device
NCV8411DTRKG
Package
Shipping
Overvoltage
Protection
DPAK
2500/Tape & Reel
Gate
Input
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
ESD Protection
Temperature
Limit
Current
Limit
Current
Sense
Source
Figure 1. Block Diagram
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
January, 2019 − Rev. 0
NCV8411/D
NCV8411
Table 1. MAXIMUM RATINGS
Rating
Symbol
Value (min)
Unit
V
Drain−to−Source Voltage Internally Clamped
Drain−to−Gate Voltage Internally Clamped
Gate−to−Source Voltage
V
DSS
42
42
14
V
DG
V
V
GS
V
Drain Current − Continuous
I
D
Internally Limited
Total Power Dissipation
P
D
W
@ T = 25°C (Note 1)
1.3
2.7
A
@ T = 25°C (Note 2)
A
Thermal Resistance
°C/W
Junction−to−Case
R
thJC
R
thJA
R
thJA
0.65
95
45
Junction−to−Ambient (Note 1)
Junction−to−Ambient (Note 2)
Single Pulse Inductive Load Switching Energy (Note 3)
E
AS
600
mJ
(L = 120 mH, T
= 150°C)
J(start)
Load Dump Voltage (V = 0 and 10 V, R = 2 W, R = 3 W) (Note 4)
U *
S
55
V
GS
G
L
Operating Junction Temperature
T
−40 to 150
−55 to 150
°C
°C
J
Storage Temperature
T
storage
ESD CHARACTERISTICS (Note 3)
Electro−Static Discharge Capability
Human Body Model (HBM)
ESD
4
kV
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Mounted onto a 2″ square FR4 board (100 sq mm, 1 oz. Cu, steady state)
2. Mounted onto a 2″ square FR4 board (645 sq mm, 1 oz. Cu, steady state)
3. Not tested in production.
4. Load Dump Test B (with centralized load dump suppression) according to ISO16750−2 standard. Guaranteed by design. Not tested in
production. Passed Class C according to ISO16750−1.
+
I
D
DRAIN
I
G
V
DS
GATE
+
SOURCE
V
GS
−
−
Figure 2. Voltage and Current Convention
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2
NCV8411
Table 2. ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Characteristic
Test Conditions
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Clamped
Breakdown Voltage
V
42
42
46
44
50
50
V
V
= 0 V, I = 250 mA
(BR)DSS
GS
D
V
GS
= 0 V, I = 250 mA,
D
T = 150°C (Note 5)
J
Zero Gate Voltage Drain Current
V
= 32 V, V = 0 V
I
−
−
1.5
5.5
5
mA
mA
DS
GS
DSS
V
DS
= 32 V, V = 0 V,
−
GS
T = 150°C (Note 5)
J
Gate Input Current
V
= 5 V, V = 0 V
I
−
50
100
GS
DS
GSS
ON CHARACTERISTICS
Gate Threshold Voltage
Threshold Temperature Coefficient
V
= V , I = 1.2 mA
V
GS(th)
1.0
−
1.8
5
2.5
−
V
GS
DS
D
V
= V , I = 1.2 mA (Note 5)
mV/°C
mW
GS
DS
D
Static Drain−to−Source
On Resistance
V
= 10 V, I = 5 A, T = 25°C
R
DS(ON)
−
23
43
29
55
GS
D
J
V
= 10 V, I = 5 A,
−
GS
D
T = 150°C (Note 5)
J
V
GS
= 5 V, I = 5 A, T = 25°C
−
−
28
50
34
60
D
J
V
= 5 V, I = 5 A,
D
GS
T = 150°C (Note 5)
J
Source Drain Forward On Voltage
I
S
= 5 A, V = 0 V
V
SD
−
0.8
1.1
V
GS
SWITCHING CHARACTERISTICS (Note 5)
Turn−On Time (10% V to 90% I )
V
DS
= 0 V to 5 V,
t
−
−
−
−
−
−
29
53
50
150
25
ms
GS
D
GS
ON
V
= 12 V, I = 1 A
D
Turn−Off Time (90% V to 10% I )
t
GS
D
OFF
Turn−On Time (10% V to 90% I )
V
GS
= 0 V to 10 V,
t
14
GS
D
ON
V
= 12 V, I = 1 A
DS
D
Turn−Off Time (90% V to 10% I )
t
80
180
2.5
GS
D
OFF
Slew Rate On (80% V to 50% V
)
DS
)
DS
V
GS
= 0 V to 10 V,
−dV /dt
DS ON
1.52
0.71
V/ms
DS
V
= 12 V, R = 4.7 W
DD
L
Slew Rate Off (50% V to 80% V
dV /dt
DS OFF
0.85
DS
SELF PROTECTION CHARACTERISTICS
Current Limit
V
= 5 V, V = 10 V
I
LIM
29
27
33
31
40
37
A
GS
DS
V
= 5 V, V = 10 V,
DS
GS
T = 150°C (Note 5)
J
V
GS
= 10 V, V = 10 V (Note 5)
23
23
34
33
46
46
DS
V
GS
= 10 V, V = 10 V,
DS
T = 150°C (Note 5)
J
Temperature Limit (Turn−Off)
Thermal Hysteresis
V
= 5 V (Note 5)
= 10 V (Note 5)
T
150
−
170
10
185
−
°C
mA
GS
LIM(OFF)
DT
LIM(ON)
Temperature Limit (Turn−Off)
Thermal Hysteresis
V
GS
T
150
−
180
10
200
−
LIM(OFF)
DT
LIM(ON)
GATE INPUT CHARACTERISTICS (Note 5)
Device ON Gate Input Current −
Normal Operation
V
= 5 V, V = 10 V, I = 1 A
I
GON
−
200
−
50
100
500
GS
DS
D
V
GS
= 10 V, V = 10 V, I = 1 A
318
DS
D
Device ON Gate Input Current −
Thermal Limit
V
GS
= 5 V, V = 10 V, I = 0 A
I
633
900
DS
D
GTL
GCL
V
GS
= 10 V, V = 10 V, I = 0 A
−
1470
245
2000
600
DS
D
Device ON Gate Input Current −
Current Limit
V
= 5 V, V = 10 V
I
−
GS
DS
V
= 10 V, V = 10 V
−
1121
1500
GS
DS
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Not tested in production.
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3
NCV8411
TYPICAL PERFORMANCE CURVES
10000
1000
100
100
T
= 25°C
J(start)
T
= 25°C
J(start)
10
T
= 150°C
J(start)
T
= 150°C
J(start)
10
1
1
10
100
1
10
100
L (mH)
L (mH)
Figure 3. Single Pulse Maximum Switch-off
Current vs. Load Inductance
Figure 4. Single Pulse Maximum Switching Energy
vs. Load Inductance
10000
1000
100
100
10
1
T
= 25°C
J(start)
T
= 25°C
J(start)
T
= 150°C
J(start)
T
= 150°C
J(start)
1
10
100
1
10
100
Time in Avalanche (ms)
Time in Avalanche (ms)
Figure 5. Single Pulse Maximum Inductive
Switch-off Current vs. Time in Avalanche
Figure 6. Single Pulse Maximum Inductive
Switching Energy vs. Time in Avalanche
45
40
35
30
25
20
15
10
5
35
7 V
8 V
−40°C
25°C
100°C
150°C
30
25
20
15
10
5
10 V
4 V
3 V
V
GS
= 2.5 V
V
DS
= 10 V
0
0
1
1.5
2
2.5
3
3.5
4
4.5
5
0
1
2
3
4
5
V
DS
(V)
V
GS
(V)
Figure 7. On-state Output Characteristics at 255C
Figure 8. Transfer Characteristics
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4
NCV8411
TYPICAL PERFORMANCE CURVES
70
60
50
40
30
20
10
45
I
= 3 A
D
150°C, V = 5 V
GS
40
35
30
25
20
15
10
150°C, V = 10 V
GS
105°C, V = 5 V
GS
105°C, V = 10 V
GS
150°C
105°C
25°C, V = 5 V
GS
25°C, V = 10 V
GS
25°C
−40°C, V = 5 V
GS
−40°C
−40°C, V = 10 V
GS
1
2
3
4
5
6
7
8
9
10
3
3.5
4
4.5
5
5.5
6
6.5
7 7.5 8 8.5 9 9.5 10
V
GS
(V)
I (A)
D
Figure 9. RDS(on) vs. Gate-Source Voltage
Figure 10. RDS(on) vs. Drain Current
2
42
40
38
36
34
32
30
V
DS
= 10 V
I
D
= 5 A
−40°C
1.75
1.5
1.25
1
25°C
100°C
V
= 5 V
GS
150°C
V
= 10 V
GS
0.75
0,5
−40 −20
0
20
40
60
80 100 120 140
5
5.5
6
6.5
7
7.5
(V)
8
8.5
9
9.5 10
T (5C)
V
J
GS
Figure 11. Normalized RDS(on) vs. Temperature
Figure 12. Current Limit vs. Gate-Source Voltage
50
45
40
35
30
25
20
100
10
V
= 0 V
V
= 10 V
GS
DS
150°C
V
GS
= 10 V
25°C
1
105°C
−40°C
V
= 5 V
GS
0.1
0.01
10
15
20
25
(V)
30
35
40
−40 −20
0
20
40
60
80 100 120 140
T (5C)
J
V
DS
Figure 13. Current Limit vs. Junction Temperature
Figure 14. Drain-to-Source Leakage Current
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5
NCV8411
TYPICAL PERFORMANCE CURVES
1.2
1.1
1
1
0.9
0.8
0.7
0.6
0.5
0.4
−40°C
25°C
0.9
0.8
0.7
0.6
105°C
I
V
= 1.2 mA
D
150°C
= V
DS
GS
V
= 0 V
9
GS
−40 −20
0
20
40
60
80 100 120 140
1
2
3
4
5
6
7
8
10
T (5C)
J
I
S
(A)
Figure 15. Normalized Threshold Voltage vs.
Temperature
Figure 16. Source-Drain Diode Forward
Characteristics
200
180
160
140
120
100
80
2.5
2
V
DD
= 25 V, I = 5 A, R = 0 W
V
DD
= 25 V, I = 5 A, R = 0 W
D
G
D
G
t
r
−dV /d
DS t(on)
1.5
1
dV /d
DS t(off)
t
d(off)
t
d(on)
60
0.5
0
40
t
f
20
0
3
4
5
6
7
8
9
10
3
4
5
6
7
8
9
10
V
GS
(V)
V
GS
(V)
Figure 17. Resistive Load Switching Time vs.
Gate-Source Voltage
Figure 18. Resistive Load Switching Drain-Source
Voltage Slope vs. Gate-Source Voltage
2
100
90
80
70
60
50
40
30
20
10
0
t
, V = 10 V
d(off) GS
V
= 25 V, I = 5 A
D
DD
1.8
−dV /d
, V = 10 V
DS t(on) GS
1.6
1.4
1.2
1
t , V = 5 V
d(off) GS
−dV /d
, V = 5 V
, V = 5 V
DS t(on) GS
t , V = 5 V
r
GS
t , V = 10 V
f
GS
dV /d
DS t(on) GS
t , V = 5 V
d(on) GS
0.8
0.6
0.4
0.2
0
dV /d
, V = 10 V
DS t(on) GS
V
DD
= 25 V, I = 5 A
D
t , V = 5 V
f
t
, V = 10 V
d(on) GS
t , V = 10 V
r GS
GS
0
200 400 600 800 1000 1200 1400 1600 1800 2000
(W)
0
200 400 600 800 1000 1200 1400 1600 1800 2000
(W)
R
R
G
G
Figure 19. Resistive Load Switching Time vs.
Gate Resistance
Figure 20. Drain-Source Voltage Slope during
Turn On and Turn Off vs. Gate Resistance
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6
NCV8411
TYPICAL PERFORMANCE CURVES
90
80
70
60
50
40
30
20
PCB Cu thickness, 1.0 oz
PCB Cu thickness, 2.0 oz
0
200
400
600
800
1000 1200 1400
2
Copper Heat Spread Area (mm )
Figure 21. RqJA vs. Copper Area
100
10
50% Duty Cycle
20%
10%
5%
1
2%
1%
0.1
Single
Pulse
0.01
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
Pulse Width (s)
Figure 22. Transient Thermal Resistance
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7
NCV8411
APPLICATION INFORMATION
Circuit Protection Features
NCV8411 establishes a slow junction temperature rise by
sensing the difference between the hot and cold sensors.
ON/OFF output cycling is designed with hysteresis that
results in a controlled saw tooth temperature profile
(Figure 23). The die temperature slowly rises (DTSD) until
the absolute temperature shutdown (TSD) is reached around
175°C.
The NCV8411 has three main protections. Current Limit,
Thermal Shutdown and Delta Thermal Shutdown. These
protections establish robustness of the NCV8411.
Current Limit and Short Circuit Protection
The NCV8411 has current sense element. In the event that
the drain current reaches designed current limit level,
integrated Current Limit protection establishes its constant
level.
Thermal Shutdown with Automatic Restart
Internal Thermal Shutdown (TSD) circuitry is provided to
protect the NCV8411 in the event that the maximum
junction temperature is exceeded. When activated at
typically 175°C, the NCV8411 turns off. This feature is
provided to prevent failures from accidental overheating.
Delta Thermal Shutdown
Delta Thermal Shutdown (DTSD) Protection increases
higher reliability of the NCV8411. DTSD consist of two
independent temperature sensors – cold and hot sensors. The
TEST CIRCUITS AND WAVEFORMS
Overtemperature
Cycling
Nominal
Load
Thermal Transient Limitation Phase
V
G
I
LIM
I
D
I
NOM
TSD
Delta TSD
Activation
T
J
Time
Figure 23. Overload Protection Behavior
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8
NCV8411
TEST CIRCUITS AND WAVEFORMS
R
L
V
IN
+
D
R
V
DD
G
−
DUT
G
S
I
DS
Figure 24. Resistive Load Switching Test Circuit
90%
10%
90%
V
IN
t
t
OFF
ON
10%
I
DS
Time
Figure 25. Resistive Load Switching Waveforms
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9
NCV8411
TEST CIRCUITS AND WAVEFORMS
L
V
DS
V
IN
+
D
R
V
DD
G
−
DUT
G
S
t
p
I
DS
Figure 26. Inductive Load Switching Test Circuit
5 V
0 V
V
IN
t
av
t
p
V
(BR)DSS
I
pk
V
DD
V
I
DS
V
DS(on)
0
DS
Time
Figure 27. Inductive Load Switching Waveform
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10
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DPAK (SINGLE GAUGE)
CASE 369C
4
ISSUE F
2
1
DATE 21 JUL 2015
3
SCALE 1:1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
MENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
A
D
E
C
A
b3
B
c2
4
2
L3
Z
DETAIL A
H
1
3
7. OPTIONAL MOLD FEATURE.
INCHES
DIM MIN MAX
0.086 0.094
A1 0.000 0.005
0.025 0.035
MILLIMETERS
L4
NOTE 7
MIN
2.18
0.00
0.63
0.72
4.57
0.46
0.46
5.97
6.35
MAX
2.38
0.13
0.89
1.14
5.46
0.61
0.61
6.22
6.73
c
b2
e
BOTTOM VIEW
A
SIDE VIEW
b
b
b2 0.028 0.045
b3 0.180 0.215
M
0.005 (0.13)
C
TOP VIEW
c
0.018 0.024
c2 0.018 0.024
Z
Z
D
E
e
0.235 0.245
0.250 0.265
0.090 BSC
H
2.29 BSC
9.40 10.41
1.40 1.78
2.90 REF
0.51 BSC
0.89 1.27
GAUGE
PLANE
SEATING
PLANE
H
L
L1
L2
0.370 0.410
0.055 0.070
0.114 REF
L2
C
0.020 BSC
L3 0.035 0.050
L
BOTTOM VIEW
A1
L4
Z
−−− 0.040
0.155 −−−
−−−
3.93
1.01
−−−
L1
ALTERNATE
CONSTRUCTIONS
DETAIL A
ROTATED 905 CW
GENERIC
MARKING DIAGRAM*
STYLE 1:
PIN 1. BASE
STYLE 2:
PIN 1. GATE
2. DRAIN
STYLE 3:
STYLE 4:
STYLE 5:
PIN 1. GATE
PIN 1. ANODE
2. CATHODE
3. ANODE
PIN 1. CATHODE
2. ANODE
2. COLLECTOR
3. EMITTER
4. COLLECTOR
2. ANODE
3. CATHODE
4. ANODE
3. SOURCE
4. DRAIN
3. GATE
4. ANODE
XXXXXXG
ALYWW
AYWW
XXX
4. CATHODE
STYLE 6:
PIN 1. MT1
2. MT2
STYLE 7:
PIN 1. GATE
STYLE 8:
PIN 1. N/C
STYLE 9:
PIN 1. ANODE
2. CATHODE
STYLE 10:
PIN 1. CATHODE
2. ANODE
XXXXXG
2. COLLECTOR
2. CATHODE
3. GATE
4. MT2
3. EMITTER
4. COLLECTOR
3. ANODE
4. CATHODE
3. RESISTOR ADJUST
4. CATHODE
3. CATHODE
4. ANODE
IC
Discrete
SOLDERING FOOTPRINT*
XXXXXX = Device Code
A
L
Y
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
6.20
0.244
3.00
0.118
2.58
0.102
*This information is generic. Please refer
to device data sheet for actual part
marking.
5.80
0.228
1.60
0.063
6.17
0.243
mm
inches
ǒ
Ǔ
SCALE 3:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
98AON10527D
DOCUMENT NUMBER:
STATUS:
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
ON SEMICONDUCTOR STANDARD
REF TO JEDEC TO−252
NEW STANDARD:
DESCRIPTION: DPAK SINGLE GAUGE SURFACE MOUNT
PAGE 1 OF2
DOCUMENT NUMBER:
98AON10527D
PAGE 2 OF 2
ISSUE
REVISION
RELEASED FOR PRODUCTION. REQ. BY L. GAN
ADDED STYLE 8. REQ. BY S. ALLEN.
DATE
O
A
B
C
D
24 SEP 2001
06 AUG 2008
16 JAN 2009
09 JUN 2009
29 JUN 2010
ADDED STYLE 9. REQ. BY D. WARNER.
ADDED STYLE 10. REQ. BY S. ALLEN.
RELABELED DRAWING TO JEDEC STANDARDS. ADDED SIDE VIEW DETAIL A.
CORRECTED MARKING INFORMATION. REQ. BY D. TRUHITTE.
E
F
ADDED ALTERNATE CONSTRUCTION BOTTOM VIEW. MODIFIED DIMENSIONS
b2 AND L1. CORRECTED MARKING DIAGRAM FOR DISCRETE. REQ. BY I. CAM-
BALIZA.
06 FEB 2014
21 JUL 2015
ADDED SECOND ALTERNATE CONSTRUCTION BOTTOM VIEW. REQ. BY K.
MUSTAFA.
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© Semiconductor Components Industries, LLC, 2015
Case Outline Number:
July, 2015 − Rev. F
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