NVD5117PL [ONSEMI]
â60 V, 16 m, â61 A, Single PâChannel; â ???? 60 V ， 16米1，A ???? 61 A单PA ????频道
| 型号： | NVD5117PL |
| 厂家： | 
ONSEMI |
| 描述： | â60 V, 16 m, â61 A, Single PâChannel |
| 文件： | 总6页 (文件大小：146K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NVD5117PL
Power MOSFET
−60 V, 16 mW, −61 A, Single P−Channel
Features
• Low R
to Minimize Conduction Losses
• High Current Capability
DS(on)
• Avalanche Energy Specified
• AEC−Q101 Qualified
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• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
V
R
I
D
(BR)DSS
DS(on)
16 mW @ −10 V
22 mW @ −4.5 V
−60 V
−61 A
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
Parameter
Drain−to−Source Voltage
Symbol
Value
−60
"20
−61
−43
118
59
Unit
V
S
V
DSS
Gate−to−Source Voltage
V
GS
V
G
Continuous Drain Cur-
T
= 25°C
= 100°C
= 25°C
I
D
A
C
P−Channel
rent R
(Note 1)
q
JC
T
C
Steady
State
Power Dissipation R
(Note 1)
T
C
P
D
W
A
q
JC
D
4
T
C
= 100°C
Continuous Drain Cur-
rent R (Notes 1 & 2)
T = 25°C
A
I
D
−11
−8
q
JA
T = 100°C
A
Steady
State
2
1
Power Dissipation R
(Notes 1 & 2)
T = 25°C
A
P
D
4.1
W
q
JA
3
T = 100°C
A
2.1
DPAK
CASE 369C
STYLE 2
Pulsed Drain Current
T = 25°C, t = 10 ms
I
−419
60
A
A
A
p
DM
I
Dmaxpkg
Current Limited by
Package (Note 3)
T = 25°C
A
Operating Junction and Storage Temperature
T , T
−55 to
°C
J
stg
MARKING DIAGRAMS
& PIN ASSIGNMENT
175
Source Current (Body Diode)
I
S
−118
A
4
Drain
Single Pulse Drain−to−Source Avalanche
E
AS
240
mJ
Energy (T = 25°C, V = 50 V, V = 10 V,
J
DD
GS
I
= 40 A, L = 0.3 mH, R = 25 W)
L(pk)
G
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
T
L
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
2
Drain
1
3
Gate Source
Y
WW
= Year
= Work Week
5117L = Device Code
= Pb−Free Package
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
G
Junction−to−Case − Steady State (Drain)
R
1.3
37
°C/W
q
JC
Junction−to−Ambient − Steady State (Note 2)
R
q
JA
ORDERING INFORMATION
1. The entire application environment impacts the thermal resistance values
shown, they are not constants and are only valid for the particular conditions
noted.
†
Device
Package
Shipping
2
2. Surface−mounted on FR4 board using a 650 mm , 2 oz. Cu pad.
NVD5117PLT4G
DPAK
(Pb−Free)
2500 / Tape &
Reel
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
September, 2011 − Rev. 0
NVD5117PL/D
NVD5117PL
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
Zero Gate Voltage Drain Current
V
V
= 0 V, I = −250 mA
−60
V
(BR)DSS
GS
D
I
T = 25°C
−1.0
−100
"100
mA
DSS
J
V
GS
= 0 V,
= −60 V
V
DS
T = 125°C
J
Gate−to−Source Leakage Current
ON CHARACTERISTICS (Note 4)
Gate Threshold Voltage
I
V
DS
= 0 V, V = "20 V
nA
GSS
GS
V
V
V
= V , I = −250 mA
−1.5
−2.5
16
V
GS(TH)
GS
DS
D
Drain−to−Source On Resistance
R
V
GS
= −10 V, I = −29 A
12
16
30
mW
DS(on)
D
= −4.5 V, I = −29 A
22
GS
D
Froward Transconductance
CHARGES AND CAPACITANCES
Input Capacitance
g
FS
V
= −15 V, I = −15 A
S
DS
D
C
V
= 0 V, f = 1.0 MHz,
4800
480
320
49
pF
iss
GS
V
DS
= −25 V
Output Capacitance
C
oss
Reverse Transfer Capacitance
Total Gate Charge
C
rss
Q
V
= −4.5 V
= −10 V
nC
G(TOT)
GS
V
I
= −48 V,
DS
D
= −29 A
V
85
GS
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
Plateau Voltage
Q
3
G(TH)
Q
13
GS
GD
GP
V
GS
= −4.5 V, V = −48 V,
DS
I
= −29 A
D
Q
V
28
3.2
V
SWITCHING CHARACTERISTICS (Notes 4)
Turn−On Delay Time
Rise Time
t
22
195
50
ns
d(on)
t
r
V
V
= −4.5 V, V = −48 V,
DS
GS
D
I
= −29 A, R = 2.5 W
G
Turn−Off Delay Time
Fall Time
t
d(off)
t
f
132
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
= 0 V,
= −29 A
T = 25°C
−0.86
−0.74
36
−1.0
V
SD
GS
J
I
S
T = 125°C
J
Reverse Recovery Time
Charge Time
t
ns
RR
t
t
19
a
V
GS
= 0 V, dl /dt = 100 A/ms,
s
I = −29 A
s
Discharge Time
17
b
Reverse Recovery Charge
Q
44
nC
RR
4. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
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2
NVD5117PL
TYPICAL CHARACTERISTICS
120
120
100
80
60
40
20
0
T = 25°C
−4.5 V
V
GS
= −10 V
J
V
DS
≥ −10 V
−4.2 V
100
80
60
40
20
0
−4 V
−3.8 V
−3.6 V
−3.4 V
−3.2 V
−3 V
T = 25°C
J
T = 125°C
J
T = −55°C
J
0
1
2
3
4
5
2
3
4
5
6
−V , DRAIN−TO−SOURCE VOLTAGE (V)
DS
−V , GATE−TO−SOURCE VOLTAGE (V)
GS
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.024
0.022
0.020
0.018
0.016
0.014
0.012
0.010
0.065
0.055
0.045
0.035
0.025
0.015
0.005
I
= −29 A
T = 25°C
D
J
T = 25°C
J
V
GS
= −4.5 V
V
= −10 V
GS
3
4
5
6
7
8
9
10
10 20 30 40 50 60 70 80 90 100 110 120
−V , GATE−TO−SOURCE VOLTAGE (V)
GS
−I , DRAIN CURRENT (A)
D
Figure 3. On−Resistance vs. Gate−to−Source
Figure 4. On−Resistance vs. Drain Current and
Voltage
Gate Voltage
2.00
1.80
1.60
1.40
1.20
1.00
0.80
0.60
100000
10000
1000
V
= 0 V
GS
V
I
= −10 V
= −29 A
GS
D
T = 150°C
J
T = 125°C
J
100
−50 −25
0
25
50
75
100 125 150 175
5
10 15 20 25 30 35 40 45 50 55 60
T , JUNCTION TEMPERATURE (°C)
J
−V , DRAIN−TO−SOURCE VOLTAGE (V)
DS
Figure 5. On−Resistance Variation with
Figure 6. Drain−to−Source Leakage Current
Temperature
vs. Voltage
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3
NVD5117PL
TYPICAL CHARACTERISTICS
6000
5500
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
10
Q
V
= 0 V
T
GS
T = 25°C
J
8
6
4
2
0
C
iss
Q
Q
gd
gs
V
I
= −48 V
= −29 A
DS
C
D
oss
T = 25°C
C
J
rss
0
0
10
20
30
40
50
60
0
10
20
30
40
50
60
70
80
90
−V , DRAIN−TO−SOURCE VOLTAGE (V)
DS
Q , TOTAL GATE CHARGE (nC)
g
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source vs. Total Charge
1000.0
100.0
10.0
120
100
80
60
40
20
0
V
= 0 V
GS
T = 25°C
J
t
d(off)
t
r
t
f
t
d(on)
V
= −48 V
= −29 A
= −10 V
DD
I
D
V
GS
1.0
1
10
R , GATE RESISTANCE (W)
100
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
−V , SOURCE−TO−DRAIN VOLTAGE (V)
G
SD
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
Figure 10. Diode Forward Voltage vs. Current
1000
100
10
250
200
150
100
50
10 ms
I
D
= −40 A
V
= −10 V
GS
100 ms
1 ms
10 ms
Single Pulse
= 25°C
T
C
dc
1
R
Limit
DS(on)
Thermal Limit
Package Limit
0.1
0
0.1
1
10
100
25
50
75
100
125
150
175
−V , DRAIN−TO−SOURCE VOLTAGE (V)
DS
T , STARTING JUNCTION TEMPERATURE (°C)
J
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
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4
NVD5117PL
TYPICAL CHARACTERISTICS
10
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.01
0.05
0.02
0.01
Single Pulse
0.00001
0.000001
0.0001
PULSE TIME (sec)
0.001
0.01
0.1
Figure 13. Thermal Response
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5
NVD5117PL
PACKAGE DIMENSIONS
DPAK (SINGLE GAUGE)
CASE 369C−01
ISSUE D
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
MENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLD
FLASH, PROTRUSIONS, OR GATE BURRS SHALL
NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE
OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM
PLANE H.
C
A
D
A
E
c2
b3
B
4
2
L3
L4
Z
H
DETAIL A
1
3
INCHES
DIM MIN MAX
0.086 0.094
A1 0.000 0.005
0.025 0.035
MILLIMETERS
MIN
2.18
0.00
0.63
0.76
4.57
0.46
0.46
5.97
6.35
MAX
2.38
0.13
0.89
1.14
5.46
0.61
0.61
6.22
6.73
A
b2
c
b
b
b2 0.030 0.045
b3 0.180 0.215
M
0.005 (0.13)
C
H
e
c
0.018 0.024
c2 0.018 0.024
GAUGE
SEATING
PLANE
L2
PLANE
C
D
E
e
0.235 0.245
0.250 0.265
0.090 BSC
2.29 BSC
9.40 10.41
1.40 1.78
2.74 REF
0.51 BSC
0.89 1.27
H
L
L1
0.370 0.410
0.055 0.070
0.108 REF
L
A1
L1
L2
0.020 BSC
DETAIL A
L3 0.035 0.050
ROTATED 905 CW
L4
Z
−−− 0.040
0.155 −−−
−−−
3.93
1.01
−−−
SOLDERING FOOTPRINT*
6.20
3.00
0.244
0.118
2.58
0.102
5.80
1.60
0.063
6.17
0.228
0.243
mm
inches
ǒ
Ǔ
SCALE 3:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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NVD5117PL/D
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