PI6C49003AE [PERICOM]
Networking Clock Generator;
| 型号： | PI6C49003AE |
| 厂家： | 
PERICOM SEMICONDUCTOR CORPORATION |
| 描述： | Networking Clock Generator |
| 文件： | 总12页 (文件大小：289K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI6C49003
Networking Clock Generator
Description
Features
The PI6C49003 is a clock generator device intended for PCIe®/
networking applications. The device includes five 100MHz
differential Host Clock Signal Level (HCSL) outputs for PCIe,
two single-ended 50 MHz outputs, one single-ended 32.256MHz
output, and one selectable single-ended 33/66/133 MHz output.
• 3.3V +/-10% Supply Voltage
• Uses 25MHz xtal such as Saronix-eCera™ SRX7278
• Five PCIe® 100MHz outputs with optional -0.5% spread
spectrum support
• Two LVCMOS 50MHz outputs that support +/- 10%
frequency margining
Using a serially programmable SMBUS interface, the PI6C49003
incorporates spread spectrum modulation on the five 100 MHz
HCSL PCIe outputs, and independent frequency margining on the
50MHz output, 33.3333MHz and 66.6666MHz clock outputs.
• One frequency selectable 33/66/133MHz LVCMOS output
• One 32.256MHz LVCMOS output
• Industrial temperature -40°C to 85°C
• Package: 48-pin TSSOP package
Pin Configuration
48
47
46
45
44
43
42
41
1
2
3
4
5
6
7
8
VDD
IREF
GND
VDD
NC
NC
100M_Q0-
100M_Q0+
100M_Q1+
100M_Q1-
VDD
VDD
VDD
GND
GND
GND
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
9
VDD
GND
VDD
Block Diagram
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
100M_Q2+
100M_Q2-
100M_Q3+
100M_Q3-
VDD
VDD
VDD
14
SCLK
SDATA
GND
25 MHz
Clock Buffer/
crystal or
Crystal
Oscillator
5
clock input
100M_OUT(0-4)
50M_Out1
50M_Out2
VDD
GND
VDD
50M_OUT(1-2)
100M_Q4+
100M_Q4-
33/66/133M_Out1
VDD
PLL, Dividers,
Buffers, and
Logic
GND
33/66/133M_OUT1
VDD
32.256M_Out1
GND
SCLK
32.256M_OUT1
SDATA
GND
PD_RESET
NC
VDD
NC
X2
PD_RESET
X1
10
ISET
475 Ohms
1%
GND
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PI6C49003
Networking Clock Generator
Pin Description
Pin # Pin Name
Pin Type
Power
Pin Description
1
V
3.3V Supply Pin
DD
2
IREF
NC
Output
Connect to 475-Ohm resistor to set HCSL output drive current
3
No connect. Leave open
4
NC
No connect. Leave open
5
V
V
Power
Power
Power
Power
Power
Power
Power
Input
3.3V Supply Pin
DD
DD
6
3.3V Supply Pin
7
GND
GND
Ground
8
Ground
9
V
DD
3.3V Supply Pin
10
11
12
13
14
GND
Ground
V
3.3V Supply Pin
DD
SCLK
SDATA
GND
SMBus compatible input clock. Supports fast mode 400kHz input clock.
I/O
SMBus compatible data line
Ground
Power
50MHz LVCMOS output. When disabled, output is trisated and has a nominal 110k-
Ohm pull-down.
15
16
50M_Out1
50M_Out2
Output
Output
50MHz LVCMOS output. When disabled, output is trisated and has a nominal 110k-
Ohm pull-down.
17
18
19
V
Power
Power
Power
3.3V Supply Pin
Ground
DD
GND
V
DD
3.3V Supply Pin
32.256MHz LVCMOS output. When disabled, output is trisated and has a nominal
110k-Ohm pull-down.
20
32.256M_Out1
Output
Power
21
22
23
GND
NC
Ground
NC
Power down reset - when low all PLL's are powered down and outputs tristated.
SMBus registers are reset to default values.
24
25
26
PD_RESET
Input
X1
X2
Input
Crystal input. Integrated 6pF capacitance
Output
Crystal output. Integrated 6pF capacitance
27
28
29
V
Power
Power
Power
3.3V Supply Pin
Ground
DD
GND
V
3.3V Supply Pin
DD
33/66/133MHz selectable LVCMOS output. When disabled, output is trisated and has
a nominal 110k-Ohm pull-down.
30
33/66/133M_Out1 Output
31
32
33
34
35
100M_Q4-
100M_Q4+
Output
Output
Power
Power
Power
100MHz HCSL output
100MHz HCSL output
3.3V Supply Pin
Ground
V
DD
GND
V
DD
3.3V Supply Pin
(Continued)
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PI6C49003
Networking Clock Generator
Pin # Pin Name
Pin Type
Output
Output
Output
Output
Power
Power
Power
Output
Output
Output
Output
Power
Power
Pin Description
36
37
38
39
40
41
42
43
44
45
46
47
48
100M_Q3-
100M_Q3+
100M_Q2-
100M_Q2+
100MHz HCSL output
100MHz HCSL output
100MHz HCSL output
100MHz HCSL output
3.3V Supply Pin
V
DD
GND
Ground
V
DD
3.3V Supply Pin
100M_Q1-
100M_Q1+
100M_Q0+
100M_Q0-
100MHz HCSL output
100MHz HCSL output
100MHz HCSL output
100MHz HCSL output
3.3V Supply Pin
V
DD
GND
Ground
50MHz Frequency Margining Table
33/66/100MHz Frequency Margining Table
FS6
0
FS5
0
FS4
0
33M/66M/133M_OUT1
33.3333 MHz
FS3 FS2
FS1
FS0 50M_OUT1, 50M_OUT2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
nominal
0
0
1
66.6666MHz +2%
66.6666MHz +1%
66.6666MHz +0%
66.6666MHz -2%
66.6666MHz -4%
66.6666MHz -6%
133.3333 MHz
0
nominal + 1%
nominal + 2%
nominal + 3%
nominal + 4%
nominal + 5%
nominal + 6%
nominal + 8%
0
1
0
1
0
1
1
1
1
0
0
0
1
0
1
0
1
1
0
1
1
1
1
1
0
nominal + 10%
nominal - 1%
nominal - 2%
nominal - 3%
nominal - 4%
nominal - 6%
nominal - 8%
nominal - 10%
0
1
1
0
0
1
1
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PI6C49003
Networking Clock Generator
Serial Data Interface (SMBus)
PI6C49003 is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit ad-
dress and read/write bit as shown below.
Address Assignment
A6
1
A5
1
A4
0
A3
1
A2
0
A1
0
A0
1
R/W
0/1
How to Write
1 bit
8 bits
1
8 bits
1
8 bits
1
8 bits
1
8 bits
1
1 bit
Start
bit
Register
offset
Byte
Count = N
Data Byte
0
Data Byte
N - 1
d2H
Ack
Ack
Ack
Ack
…
Ack Stop bit
Note:
1.
Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0.
How to Read (M: abbreviation for Master or Controller; S: abbreviation for slave/clock)
8
bits
8
bits
8
bits
8
bits
8
bits
8
bits
1 bit
1 bit
1 bit 1 bit
1 bit
1 bit
1 bit
…
1 bit
1 bit
S:
sends
# of
data
bytes
that
will
be
M:
send
start-
ing
data-
byte
loca-
tion:
N
S:
sends
start-
ing
data
byte
N
S:
sends M: Not
M:
Start
bit
M:
Send
"D2h"
S:
sends
Ack
S:
sends
Ack
M:
Start
bit
M:
Send
"D3h"
S:
sends
Ack
M:
sends
Ack
M:
sends
Ack
M:
Stop
bit
data
byte
N+X-
1
Ac-
knowl-
edge
…
sent:
X
Byte 0: Spread Spectrum Control Register
Power Up
Condition
Output(s)
Affected
Bit
Description
Type
Notes
0=spread off
1 = -0.5% down
spread
Spread Spectrum Selection for 100 MHz HCSL
PCI-Express clocks
All 100MHz HCSL
PCI Express outputs
7
RW
RW
RW
0
0
1
Enables hardware or software control of OE bits
(see Byte 0–Bit 6 and Bit 5 Functionality table)
PD_RESET pin,
bit 5
0 = hardware cntl
1 = software ctrl
6
Software PD_RESET bit. Enables or disables all
outputs
(see Byte 0–Bit 6 and Bit 5 Functionality table)
0 = disabled
1 = enabled
5
All outputs
4
3
2
Frequency margining select bit FS3
Frequency margining select bit FS2
Frequency margining select bit FS1
RW
RW
RW
1
0
1
See 50MHz Fre-
quency Select Table
on Page 3
50M_Out1 and
50M_Out2
1
Frequency margining select bit FS0
RW
0
Single-ended
50MHz output
50M_Out2
0 = disabled
1 = enabled
0
OE for single-ended 50 MHz output 50M_Out2
RW
1
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PI6C49003
Networking Clock Generator
Byte 0 - Bit 6 and Bit 5 Functionality
Bit 6
Bit 5
Description
0
1
1
X
0
PD_RESET HW pin/signal = enabled
Disables all outputs and tri-states the outputs, PD_RESET HW pin/signal = DO NOT CARE
Enable all outputs, PD_RESET HW pin/signal = DON'T CARE
1
Byte 1: Control Register
Power Up Condi-
tion
Bit
Description
Type
Output(s) Affected
Notes
0 = disabled
1 = enabled
7
6
5
OE for 32.256M_Out1
OE for 50M_Out1
RW
RW
RW
1
1
1
32.256M_Out1
50M_Out1
0 = disabled
1 = enabled
0 = disabled
1 = enabled
OE for 33/66/133M_Out1
33/66/133M_Out1
4
Reserved
Reserved
RW
RW
1
0
Not Applicable
Not Applicable
3 to 0
Byte 2: Control Register
Power Up Condi-
tion
Bit
Description
Type
Output(s) Affected
Notes
7
Frequency margining select bit FS6 RW
Frequency margining select bit FS5 RW
Frequency margining select bit FS4 RW
1
See 33/66/100MHz
Frequency Select
Table on Page 3
6
0
33/66/133M_Out1
Not Applicable
5
0
4 to 0
Reserved
R
Undefined
Byte 3: Control Register
Power Up Con-
dition
Bit
Description
Type
Output(s) Affected
Notes
0 = disabled
1 = enabled
7
5
4
2
1
OE for 100M_Q4 HCSL Output
OE for 100M_Q3 HCSL Output
OE for 100M_Q2 HCSL Output
OE for 100M_Q1 HCSL Output
OE for 100M_Q0 HCSL Output
RW
RW
RW
RW
RW
0
0
0
1
1
100M_Q4
100M_Q3
100M_Q2
100M_Q1
100M_Q0
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
0 = disabled
1 = enabled
3, 6
0
Reserved
Reserved
RW
R
0
Not Applicable
Not Applicable
Undefined
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PI6C49003
Networking Clock Generator
Byte 4: Control Register
Power Up Condi-
tion
Bit
Description
Type
Output(s) Affected
Notes
7 to 0
Reserved
R
Undefined
Not Applicable
Byte 5: Control Register
Power Up Condi-
tion
Bit
Description
Type
Output(s) Affected
Notes
7
6
5
4
3
2
1
0
Revivsion ID bit 3
Revivsion ID bit 2
Revivsion ID bit 1
Revivsion ID bit 0
Vendor ID bit 3
Vendor ID bit 2
Vendor ID bit 1
Vendor ID bit 0
R
R
R
R
R
R
R
R
0
0
0
0
0
0
1
1
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Not Applicable
Byte 6: Control Register
Power Up Condi-
tion
Bit
Description
Type
Output(s) Affected
Notes
7 to 0
Reserved
R
Undefined
Not Applicable
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PI6C49003
Networking Clock Generator
Absolute Maximum Ratings1 (Over operating free-air temperature range)
Symbol
Parameters
Min.
Max.
4.6
Units
V
DD
V
IH
V
IL
3.3V I/O Supply Voltage
Input High Voltage
Input Low Voltage
Storage Temperature
ESD Protection
-0.5
4.6
V
-0.5
-65
Ts
150
°C
V
V
ESD
2000
Note:
1. Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.)
Note:
Maximum Supply Voltage, V ............................................................ 7V
DD
Stresses greater than those listed under MAXIMUM RAT-
INGS may cause permanent damage to the device. This is
a stress rating only and functional operation of the device
at these or any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for ex-
tended periods may affect reliability.
All Inputs and Outputs ...............................................–0.5V to V +0.5V
DD
Ambient Operating Temperature....................................... –40°C to +85°C
Storage Temperature........................................................ –65°C to +150°C
Junction Temperature ........................................................................125°C
Peak Soldering Temperature..............................................................260°C
DC Electrical Characteristics
Unless otherwise specified, V =3.3V±10%, Ambient Temperature –40°C to +85°C
DD
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Operating Supply Volt-
age
V
DD
3.0
3.6
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
V
IH
V
IL
V
IH
V
IL
2
V
DD
V
–0.3
0.7V
0.8
SDATA, SCLK
SDATA, SCLK
V
DD
DD
0.3V
DD
Operating Supply Cur-
rent
I
150
5
DD
mA
IDD at Output Disable
Condition
PD_RESET = 0
PD_RESET
240
Internal Pull-Up/Pull-
Down Resistor
R
C
/R
k–Ohm
pF
PU PD
All single-ended outputs
All input pins
110
6
Input Capacitance
IN
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PI6C49003
Networking Clock Generator
Electrical Characteristics - Single-Ended
Unless otherwise specified, V =3.3V±10%, Ambient Temperature –40°C to +85°C
DD
Parameter
Symbol
Conditions
Min
Typ
25
Max
Units
MHz
kHz
Input Clock Frequency
SCLK Frequency
F
IN
100
400
Min. pulse width of
PD_RESET Input
100
ns
Output Frequency
Error
FS0, FS6 = 0
32.256MHz
0
ppm
Output Frequency
Error
7
Output Rise/Fall Time t t
V
=3.3V, 0.8V to 2.4V
DD
0.5
50
1
ns
%
r, f
Output Clock Duty
Cycle
Measured at V /2
45
55
DD
High-Level Output
Voltage
V
OH
V
OH
V
OL
I
OH
I
OH
I
OL
= -4mA
= -8mA
= 8mA
VDD-0.4
2.4
High-Level Output
Voltage
V
Low-Level Output
Voltage
0.4
140
200
50 MHz clock output
Peak-to-Peak Jitter
33/66/133MHz clock output
32.256 MHz clock output
125
115
120
120
175
150
175
160
ps
50 MHz clock output
Cycle-to-Cycle Jitter
33/66/133 MHz clock output
Clock Stabilization
Time from Power Up
3
10
ms
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PI6C49003
Networking Clock Generator
Electrical Characteristics - 100MHz Differential HCSL Outputs
Unless otherwise specified, V =3.3V±10%, Ambient Temperature –40°C to +85°C
DD
Symbol
Parameter
Conditions
Min
Typ
Max
100
150
Units
Output Frequency
Cycle-to-Cycle Jitter
MHz
T
CC/Jitter
ps
Using PCIe jitter measure-
ment method
Peak-to-Peak Phase Jitter
86
0
Spread Modulation Percentage
-0.5
32
%
Spread Modulation Frequency
kHz
Duty Cycle
T
45
50
55
%
DC
Rising Edge Rate
Falling Edge Rate
Note 3, 4
Note 3, 4
0.6
0.6
4.0
4.0
V/ns
V = 50%(measurement
threshold)
T
Output Skew
T
Z
200
ps
OSKEW
Clock Source DC Impedance,
single ended
50
Ohm
C-DC
Note 2, (R =33-Ohm,
R =50-Ohm)
T
S
High-Level Output Voltage
Low-Level Output Voltage
V
0.65
0.71
0.85
0.05
OH
OL
V
V
–0.20
0
I
@ 6*I
I
OH
–13
–14.2
–17
mA
V
OH
REF
Absolute Crossing Point Voltage
V
CROSS
Note 2, 5, 6
Note 2, 5, 8
Note 3, 9, 10
Note 3, 7
0.25
0.55
Variation of VCROSS over all ris-
ing clock edges
V
140
mV
CROSS Delta
PERIOD AVG
PERIOD ABS
Average Clock Period Accuracy
T
T
–300
2800
10.203
ppm
Absolute Period (including jitter
and spread spectrum)
9.847
ns
(Continued)
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PI6C49003
Networking Clock Generator
Notes:
1. Measured at the end of an 8-inch trace with a 5pF load.
2. Measurement taken from a single-ended waveform.
3. Measurement taken from a differential waveform.
4. Measured from -150 mV to +150 mV on the differential waveform. The signal is monotonic through the
measurement region for rise and fall time. The 300 mV measurement window is centered on the differen-
tial zero crossing.
5. Measured at crossing point where the instantaneous voltage value of the rising edge of 100M+ equals the
falling edge 100M–.
6. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is cross-
ing. Refers to all crossing points for this measurement.
7. Defines as the absolute minimum or maximum instantaneous period. This includes cycle-to-cycle jitter,
relative PPM tolerance, and spread spectrum modulation.
8. Defined as the total variation of all crossing voltages of rising 100M+ and falling 100M–.
9. Refer to section 4.3.2.1 of the PCI Express Base Specification, Revision 1.1 for information regarding
PPM considerations.
10. PPM refers to parts per million and is a DC absolute period accuracy specification. 1 PPM is 1/1,000,000th
of 100 MHz exactly or 100 Hz. For 300 PPM there is an error budget of 100Hz/PPM * 300 PPM = 30 kHz.
The period is measured with a frequency counter with measurement window set at 100 ms or greater. With
spread spectrum turned off the error is less than ±300 ppm. With spread spectrum turned on there is an ad-
ditional +2500 PPM nominal shift in maximum period resulting from the -0.5% down spread.
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PI6C49003
Networking Clock Generator
Configuration test load board termination for HCSL Outputs
Rs
337
5%
Clock
TLA
PI6C49003
Rs
337
5%
Clock#
TLB
2pF
5%
2pF
5%
Rp
49.97
1%
Rp
49.97
4757
1%
1%
Figure 4. Configuration Test Load Board Termination
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PI6C49003
Networking Clock Generator
DOCUMENT CONTROL NO.
PD - 1501
48
REVISION: G
DATE: 03/09/05
.236
.244
6.0
6.2
See Note 4
1
.488 12.4
.496 12.6
See Note 3
.047
1.20 Max
SEATING PLANE
0.09
0.20
.004
.008
0.45 .018
0.75 .030
.002
.007
.010
.0197
BSC
.006
0.05
0.15
.319
BSC
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
0.50
0.17
0.27
8.1
Note:
1. Controlling dimensions in millimeters.
2. Ref: JEDEC MO-153F/ED
3. Dimension does not include mold flash, protrusions or gate burrs. Mold flash, protru-
sions and gate burrs shall not exceed 0.15mm per side.
Pericom Semiconductor Corporation
3545 N. 1st Street, San Jose, CA 95134
1-800-435-2335 • www.pericom.com
4. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion
shall not exceed 0.25mm per side.
DESCRIPTION: 48-Pin 240-Mil Wide TSSOP
PACKAGE CODE: A
Note:
For latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php
•
(1-3)
Ordering Information
Ordering Code
Package Code
Package Description
48-pin, Pb-free & Green, TSSOP, (A48)
PI6C49003AE
A
Notes:
1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
2. E = Pb-free and Green
3. Adding an X suffix = Tape/Reel
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
PS9023A
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