TZA3004HL-T [NXP]
IC CLOCK RECOVERY CIRCUIT, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-313-2, LQFP-48, ATM/SONET/SDH IC;
| 型号： | TZA3004HL-T |
| 厂家： | 
NXP |
| 描述： | IC CLOCK RECOVERY CIRCUIT, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-313-2, LQFP-48, ATM/SONET/SDH IC ATM 异步传输模式 电信 电信集成电路 |
| 文件： | 总32页 (文件大小：180K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TZA3004HL
SDH/SONET data and clock
recovery unit STM1/4 OC3/12
Product specification
2000 Nov 28
Supersedes data of 1998 Feb 09
File under Integrated Circuits, IC19
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4 OC3/12
TZA3004HL
FEATURES
APPLICATIONS
• Data and clock recovery up to 622 Mbits/s
• Multi-rate configurable (155 and 622 Mbits/s)
• Data and clock recovery in STM1/OC3 and STM4/OC12
transmission systems.
• Differential data input with 2.5 mV (p-p) typical
DESCRIPTION
sensitivity
• Differential Current-Mode Logic (CML) data and clock
outputs with 50 Ω driving capability
The TZA3004HL is a data and clock recovery IC intended
for use in Synchronous Digital Hierarchy (SDH) and
Synchronous Optical Network (SONET) systems. The
circuit recovers data and extracts the clock signal from an
incoming bitstream up to 622 Mbits/s. It can be configured
for use in STM1/OC3 and STM4/OC12 systems.
• Adjustable CML output level
• Loop mode for system testing
• Bit error rate related loss of signal detection
• Few external components needed
• Single supply voltage
• Power dissipation 370 mW (typical value)
• LQFP48 plastic package.
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
TZA3004HL
LQFP48
plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm
SOT313-2
2000 Nov 28
2
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4 OC3/12
TZA3004HL
BLOCK DIAGRAM
LOS
39
SEL155
30
AREF ENL
h
48
1
FREQUENCY
DIVIDER 1
4/16
42
DOUT
43
45
46
6
DOUTQ
COUT
DATA
AND
CLOCK
OUTPUT
33
34
COUTQ
DLOOP
DLOOPQ
CLOOP
CLOOPQ
DIN
ALEXANDER
PHASE
DETECTOR
7
DINQ
3
TZA3004HL
4
enable
21
22
CREF
proportional
FREQUENCY
WINDOW
DETECTOR
(1000 ppm)
path
CREFQ
VCRO
+
integrating
path
∫
dt
130 pF
130 pF
37
POWER
PC
CONTROL
FREQUENCY
DIVIDER 2
64/128
4
17
2, 5, 8, 10, 11, 14, 17,
20, 23, 26, 29, 32, 35,
38, 41, 44, 47
12
9
24
16
15
25
27
28
31
MGU255
V
V
EE3
LOCK DREF19 DREF39 CAPDOQ
CAPUPQ
GND
EE1
V
V
EE4
EE2
Fig.1 Block diagram.
3
2000 Nov 28
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4 OC3/12
TZA3004HL
PINNING
SYMBOL
ENL
PIN
DESCRIPTION
1
loop mode enable input (active LOW)
ground; note 1
GND
2
CLOOP
CLOOPQ
GND
3
clock output in loop mode (differential)
4
inverted clock output in loop mode (differential)
ground; note 1
5
DLOOP
DLOOPQ
GND
6
data output in loop mode (differential)
inverted data output in loop mode (differential)
ground; note 1
7
8
DREF19
GND
9
reference frequency select input 1 (see Table 3)
ground; note 1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
GND
ground; note 1
LOCK
i.c.
phase lock detection output
internally connected; note 2
ground; note 1
GND
CAPUPQ
CAPDOQ
GND
external loop filter capacitor connection
external loop filter capacitor return connection
ground; note 1
i.c.
internally connected; note 2
internally connected; note 2
ground; note 1
i.c.
GND
CREF
CREFQ
GND
reference clock input (differential)
inverting reference clock input (differential)
ground; note 1
DREF39
VEE1
reference frequency select input 2 (see Table 3)
negative supply voltage (−3.3 V); note 3
ground; note 1
GND
VEE2
negative supply voltage (−3.3 V); note 3
negative supply voltage (−3.3 V); note 3
ground; note 1
VEE3
GND
SEL155
VEE4
STM mode select input 3 (see Table 2)
negative supply voltage (−3.3 V); note 3
ground; note 1
GND
DIN
data input (differential)
DINQ
GND
inverting data input (differential)
ground; note 1
i.c.
internally connected; note 2
control output for negative power supply
ground; note 1
PC
GND
LOS
loss of signal detection output
internally connected; note 2
i.c.
2000 Nov 28
4
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4 OC3/12
TZA3004HL
SYMBOL
GND
PIN
DESCRIPTION
41
42
43
44
45
46
47
48
ground; note 1
DOUT
DOUTQ
GND
data output in normal mode (differential)
inverted data output in normal mode (differential)
ground; note 1
COUT
COUTQ
GND
clock output in normal mode (differential)
inverted clock output in normal mode (differential)
ground; note 1
AREF
reference voltage input for controlling voltage swing on data and clock outputs
Notes
1. ALL GND pins must be connected; do not leave one single GND pin unconnected.
2. ALL pins denoted ‘i.c.’ have internal connections; external connections to these pins should not be made.
3. ALL VEE pins must be connected; do not leave one single VEE pin unconnected.
1
2
36 i.c.
35
ENL
GND
GND
34 DINQ
33
CLOOP
CLOOPQ
GND
3
4
DIN
32 GND
5
V
31
6
DLOOP
DLOOPQ
GND
EE4
TZA3004HL
7
30 SEL155
29 GND
8
V
V
DREF19
GND
9
28
27
26
25
EE3
EE2
10
11
12
GND
GND
LOCK
V
EE1
MGU254
Fig.2 Pin configuration.
2000 Nov 28
5
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4 OC3/12
TZA3004HL
FUNCTIONAL DESCRIPTION
If the levels at B and T are the same but are different from
the level at A, the clock was too late and needs to be
speeded up for synchronization. The phase detector
generates an up pulse forcing the VCRO to run at a slightly
higher frequency (+0.25%) for one bit period. The phase of
the clock signal is shifted with respect to the data signal (as
above, but in the opposite direction). While making these
phase adjustments, only the proportional path is active.
This type of loop is known as a Bang/Bang Phase-Locked
Loop (PLL) as the instantaneous frequency of the VCRO
changes in one of two discrete steps (±0.25%).
The TZA3004HL recovers data and clock signals from an
incoming high speed bitstream. The input signal on
pins DIN and DINQ is buffered and amplified by the input
circuitry (see Fig.1). The signal is then fed into the
Alexander phase detector where the phase of the
incoming data signal is compared with that of the internal
clock. If the signals are out of phase, the phase detector
generates correction pulses (up or down) that shift the
phase of the Voltage Controlled Ring Oscillator (VCRO)
output in discrete amounts (∆ϕ) until the clock and data
signals are in phase. The technique used is based on
principles first proposed by J. D. H. Alexander, hence the
name of the phase detector.
If the phase and the frequency of the VCRO are incorrect,
a long train of up or down pulses is generated. This train of
pulses is integrated to generate a control voltage that is
used to shift the centre frequency of the VCRO. Once the
correct frequency has been established, only the phase
will need to be adjusted for synchronization. The
Data sampling
As shown in Fig.3, the eye pattern of the incoming data is
sampled at three instants A, T and B. When clock and
data signals are synchronized (locked):
proportional path adjusts the phase of the clock signal,
whereas the integrating path adjusts the centre frequency.
• A is the centre of the data bit
Frequency window detector
• T is in the vicinity of the next transition
• B is in the centre of the bit following the transition.
The frequency window detector checks the VCRO
frequency which has to be within a 1000 ppm (parts per
million) window around the required frequency.
If the same level is recorded at both A and B, a transition
has not occurred and no action is taken. However, if the
levels at A and B are different, a transition has occurred
and the phase detector uses the level at T to determine
whether the clock was too early or too late with respect to
the data transition.
It compares the output of frequency divider 2 with the
reference frequency on pins CREF and CREFQ
(19.44 or 38.88 MHz; see Table 3). If the VCRO frequency
is found to be outside this window, the frequency window
detector disables the Alexander phase detector and forces
the VCRO output to a frequency within the window. The
phase detector then starts acquiring lock again. Due to the
loose coupling of 1000 ppm, the reference frequency does
not need to be highly accurate or stable. Any crystal based
oscillator that generates a reasonably accurate frequency
(e.g. 100 ppm) can be used.
If the levels at A and T are the same but are different from
the level at B, the clock was too early and needs to be
slowed down a little. The Alexander phase detector then
generates a down pulse which stretches a single output
pulse from the ring oscillator by approximately 0.25%
which is 4 ps of the 1.6 ns bit period in the STM4/OC12
mode. This forces the VCRO to run at a slightly lower
frequency for one bit period. The phase of the clock signal
is thus shifted fractionally with respect to the data signal.
Since sampling point A is always in the centre of the eye
pattern when the data and clock signals are in phase
(locked), the values recorded at this point are taken as the
retrieved data. The data and clock signals are available at
the CML output buffers, that are capable of driving a 50 Ω
load.
handbook, halfpage
DATA
RF data and clock input circuit
The schematic of the input circuit is shown in Fig.4.
A
T
B
RF data and clock output circuit
CLOCK
The schematic of the output circuit is shown in Fig.5.
MGK143
Fig.3 Data sampling.
2000 Nov 28
6
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4 OC3/12
TZA3004HL
handbook, halfpage
100 Ω
100 Ω
DOUTQ, COUTQ
DOUT, COUT
50 Ω
50 Ω
DIN,
CREF
DINQ,
CREFQ
V
AREF
MGL669
V
EE
MGL670
V
EE
Fig.4 RF data and clock input circuit.
Fig.5 RF data and clock output circuit.
Power supply and power control loop
Output amplitude reference
The TZA3004HL contains an on-board voltage regulator.
An external power transistor is needed to deliver the
supply to this circuit. The external circuit requirement is
straightforward and needs few components. A suitable
circuit with a power supply of −4.5 V is illustrated in Fig.6.
The inductor shown is an RF choke with an impedance
greater than 50 Ω at frequencies higher than 2 MHz. Any
transistor with a β of approximately 100 and enough
current sink capability can be used.
The voltage swing at the CML-compatible output stages
(pins DOUT, DOUTQ, COUT, COUTQ, DLOOP,
DLOOPQ, CLOOP and CLOOPQ) can be controlled by
adjusting the voltage on pin AREF (see Fig.7). An internal
voltage divider of 500 Ω and 16 kΩ connected between
ground and VEE initially fixes this level.
In most applications the outputs will be DC-coupled to
a load of 50 Ω. The output level regulation circuit will
maintain a 200 mV (p-p) single-ended swing across this
load. The voltage on pin AREF is half the single-ended
peak-to-peak value of the output signal (−100 mV).
No adjustments are necessary with DC-coupling.
The TZA3004HL can also be used with a power supply of
−5.0 or −5.2 V. The only adaptation to be made to the
power control circuit is to change the emitter resistor R1
(see Fig.6 and Table 1).
When the outputs are AC-coupled, the voltage on
As long as the power supply rejection ratio is greater than
60 dB for all frequencies, a different power supply
configuration could be used.
pin AREF is half the single-ended peak-to-peak value of
RL + Ro
the output signal multiplied by a factor
-------------------
RL
Table 1 Value of resistor R1.
where RL is the external load and Ro is the output
impedance of the TZA3004HL (100 Ω).
POWER SUPPLY
RESISTOR R1
−4.5 V
−5.0 V
−5.2 V
2.0 Ω
6.8 Ω
8.2 Ω
2000 Nov 28
7
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4 OC3/12
TZA3004HL
BAND GAP
REFERENCE
on chip
off chip
GND
V
PC
EE
100 nF
2 Ω
β ≈ 100
3.3
nF
1
kΩ
R1
2 Ω
1 µF
1 kΩ
(1)
L1
−4.5 V
MGU253
(1) L1 = RF choke type Murata BLM21, 1 µH.
Fig.6 Schematic diagram of TZA3004HL power control loop.
If the outputs are AC-coupled, the formulae for calculating
the required voltage on pin AREF and the value of the
resistor connected between pins AREF and VEE are:
RL + R
VAREF = –
o × 0.5V
(1)
-------------------
swing
RL
and:
handbook, halfpage
VEE
GND
R1 ×
– 1
----------------
VAREF
500 Ω
16 kΩ
on chip
RAREF =
-------------------------------------------------------------
(2)
V EE
R1
-------
R2
AREF
V
1 –
×
– 1
----------------
VAREF
AREF
R
where R1 = 500 Ω, R2 = 16 kΩ and VEE = −3.3 V.
AREF
To maintain a single-ended swing of 200 mV (p-p) across
a 50 Ω AC-coupled load, the voltage on pin AREF must be
V
EE
off chip
(50 + 100)Ω
–100 mV ×
= –300 mV.
--------------------------------
MGL667
50 Ω
This can be achieved by connecting a 7.3 kΩ resistor
between pins AREF and VEE
.
Fig.7 Functionality of pin AREF.
2000 Nov 28
8
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4 OC3/12
TZA3004HL
External capacitor for loop filter
Lock detection
The loop filter is an integrator with a built-in capacitance of
2 × 130 pF. To ensure loop stability while the frequency
window detector is active, an external capacitance of
200 nF should be connected between pins CAPUPQ
and CAPDOQ.
The LOCK output can be interpreted as an indication that
the reference clock is present on pin CREF and that the
acquisition aid (frequency window detector) is functioning
properly.
LOCK is an open-collector TTL output to be connected via
a 10 kΩ pull-up resistor to a positive supply voltage. If the
VCO frequency is within a 1000 ppm window around the
desired frequency, pin LOCK will stay at HIGH-level. If no
reference clock is present, or the VCO is outside the
1000 ppm window, pin LOCK will be at a LOW-level. The
logic level on pin LOCK does not indicate locking of the
PLL to the incoming data; this is done by the signal on
pin LOS.
Loop mode enable
The loop mode is provided for system testing (see Fig.8).
Loop mode is enabled by applying a voltage lower than
0.8 V (TTL LOW-level) to pin ENL. In loop mode, the
outputs on pins DLOOP, DLOOPQ, CLOOP and
CLOOPQ are switched on.
A voltage higher than 2.0 V (TTL HIGH-level) applied to
pin ENL switches on pins DOUT, DOUTQ, COUT
and COUTQ while pins DLOOP, DLOOPQ, CLOOP
and CLOOPQ are disabled to minimize power
consumption.
Loss of signal detection
The Loss Of Signal (LOS) function is closely related to the
functionality of the Alexander phase detector (see Fig.3 for
the meaning of A, B and T in this section).
Connecting pin ENL to VEE (−3.3 V) enables all outputs.
The phase detector takes no action if there has been no
transition and the values at sample points A and B are the
same. However, if levels A and B are equal but level at T
is different, even with no transition, the incorrect level at T
could lead to a bit error. This incorrect level could be due
to noise or from poor signal integrity. The cumulative affect
of bit errors could cause the PLL to lose lock and the LOS
alarm to be asserted. The LOS alarm assert level is
approximately Bit Error Rate (BER) = 5 × 10−2 and the
de-assert level is approximately BER = 1 × 10−3.
handbook, halfpage
off chip
on chip
ENL
36 kΩ
LOS detection functions correctly if the input signal is
larger than the input offset of the TZA3004HL. If the input
signal is smaller, it is masked by the input offset and
interpreted as consecutive bits of the same sign, thus
obstructing LOS detection. In practice, an optical front-end
device with a noise level larger than the specified offset of
the TZA3004HL will ensure proper LOS indication.
GND
DECODER
LOGIC
The LOS detection is BER related, but not dependent on
the data stream content or protocol. Therefore, an
SDH/SONET data stream is no prerequisite for a proper
LOS function. Since the LOS function of the TZA3004HL
is derived from digital signals, it is a good supplement to an
analog, amplitude based, LOS indication.
V
EE
MGL668
Pin LOS is an open-collector TTL compatible output. that
needs a pull-up resistor connected to a positive supply
voltage to function.
Fig.8 Input circuit of pin ENL.
The LOS pin will be at a (TTL) HIGH-level if the data signal
is absent on pins DIN and DINQ or if BER > 5 × 10−2;
otherwise pin LOS will be at LOW-level if BER < 1 × 10−3.
2000 Nov 28
9
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4 OC3/12
TZA3004HL
STM mode selection
Reference frequency select
The VCRO has a very wide tuning range. However, the
performance of the TZA3004HL is optimized for
SDH/SONET bit rates.
A reference clock signal of 19.44 or 38.88 MHz must be
connected to pins CREF and CREFQ. Pins DREF19
and DREF39 are used to select the appropriate output
frequency at frequency divider 2 (see Table 3).
Due to the nature of the PLL, the very wide tuning range is
a necessity for proper lock behaviour over the guaranteed
temperature range, aging and batch-to-batch spread.
To minimize the adverse influence of reference clock
crosstalk, a differential signal with an amplitude from
75 to 150 mV (p-p) is advised.
Though it may seem that the TZA3004HL is capable of
recovering bit rates other than SDH/SONET (STM1/OC3
and STM4/OC12), lock behaviour cannot be guaranteed.
Since the reference clock is only used as an acquisition aid
for the PLL of the frequency window detector, the quality
of the reference clock (i.e. phase noise) is not important.
There is no phase noise specification imposed on the
reference clock generator and even frequency stability
may be in the order of 100 ppm. In general, most
inexpensive crystal-based oscillators are suitable.
The required SDH/SONET bit rate is selected by
connecting pin SEL155 to the ground plane or to the
supply voltage VEE (see Table 2):
• For STM4/OC12 (622.08 Mbits/s) operation, pin
SEL155 is to be connected to ground (pin GND)
There are two application possibilities for the TZA3004HL
reference clock:
• For STM1/OC3 (155,52 Mbits/s) operation, pin SEL155
is to be connected to VEE
.
• A fixed reference clock frequency, here it is best to
connect pins DREF19 and DREF39 using a short track
or a via to the ground plane or the supply voltage VEE
The connection to VEE or ground carries a current of a few
milliamperes and should have low resistance and
inductance; short printed-circuit board tracks are
recommended. In some cases it may be necessary to add
a decoupling capacitor near the selection pin to provide
a clean return path for RF signals.
• A selectable reference clock frequency in which the pins
can be controlled through low-ohmic switching FETs,
e.g. BSH103 or equivalent (low RDSon).
When the TZA3004HL is used in an application with a fixed
data rate it is best to connect pin SEL155 by a short copper
Table 3 Reference frequency selection
LEVEL ON PIN
FREQUENCY DIVISION
trace or a via to the ground plane or supply voltage VEE
.
(MHz)
FACTOR
If a selectable reference clock frequency is required in the
application, the pin can be controlled through a low-ohmic
switching FET, e.g. BSH103 or equivalent (low RDSon).
DREF19
DREF39
38.88
19.44
64
ground
VEE
VEE
VEE
128
Table 2 STM mode select
BIT RATE
(Mbits/s)
DIVISION
FACTOR
LEVEL ON
PIN SEL155
MODE
STM1/OC3
155.52
622.08
16
4
VEE
STM4/OC12
ground
2000 Nov 28
10
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4 OC3/12
TZA3004HL
Application with positive supply voltage
LOSS OF SIGNAL AND LOCK DETECTION
The versatile design of the TZA3004HL allows the device
to operate in a positive supply voltage application,
although some pins then have a different operating mode.
This section deals with these differences and supports the
user with achieving a successful application of the
TZA3004HL in a +5 V environment.
In the negative supply application, pins LOS and LOCK
are open-collector outputs that require pull-up resistors to
a positive supply voltage.
In the positive supply application, the pull-up voltage would
need to be higher than the positive supply voltage. The
signals on pins LOS and LOCK would no longer be TTL
compatible. However, the internal circuit on pins LOS and
LOCK can be used in a current mirror configuration (see
Fig.9). This requires only an external PNP transistor (e.g.
BC857 or equivalent) to mirror the current. A 10 kΩ
pull-down resistor from the collector of the external
transistor to ground yields a TTL compatible signal again
but it is inverted. The meaning of the LOS and LOCK flag
when used in the positive supply application is shown in
Table 5.
APPLICATION DIAGRAM
A sample application diagram is shown in Fig.22. It should
be noted that all GND pins are now connected to VCC and
all VEE pins are still connected to the regulated voltage
from the power controller.
OUTPUT SELECTION
In a positive supply voltage application, the loop mode is
the default RF output. Due to the decoding logic on
pin ENL, it is only possible to select the loop mode outputs
or enable all the outputs.
handbook, halfpage
on chip
off chip
GND
If pin ENL is connected to VCC (+5 V), only the loop mode
outputs are active (see Table 4). When pin ENL is
connected to VEE (the voltage is approximately 3.3 V
below VCC), all outputs become active. In the positive
supply voltage application, the normal mode outputs
cannot be selected, unless the voltage on pin ENL is 2 V
above the positive supply voltage (VCC).
+5 V
BC857
signal out
10 kΩ
LOS,
LOCK
MGL671
CAUTION
Fig.9 Signal output for LOS and LOCK indication in
a positive supply voltage application.
Do not to connect pin ENL to ground, because this will
destroy the IC.
Table 4 Output selection in a positive supply voltage application
OUTPUT
MODE
LEVEL ON PIN ENL
DLOOP, DLOOPQ,
DOUT, DOUTQ,
CLOOP AND CLOOPQ
COUT AND COUTQ
Loop
V
CC (+5 V)
VEE (VCC − 3.3 V)
CC + 2 V
active
active
−
−
Loop and normal
Normal
active
active
V
Table 5 LOS and LOCK indication in a positive supply voltage application
SIGNAL
DESCRIPTION
loss of signal: BER > 5 × 10−2
no loss of signal: BER < 1 × 10−3
LEVEL
TTL
LOS active
0 V (ground)
LOW
HIGH
LOW
HIGH
LOS inactive
LOCK active
LOCK inactive
+5 V (VCC
0 V (ground)
+5 V (VCC
)
reference clock present and VCRO inside 1000 ppm window
no reference clock present or VCRO outside 1000 ppm window
)
2000 Nov 28
11
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4 OC3/12
TZA3004HL
DIVIDER SETTINGS
While laying out the application, the return path is the most
important issue to be considered. Always examine
carefully the current-carrying loops in the design. Care
should be taken that low-ohmic and low-inductance return
paths are available for all frequencies (both of interest and
not of interest). These return paths should preferably have
an enclosed area as small as possible, both horizontally
and vertically (by means of through-holes or vias). The
position of a decoupling capacitor is very important.
A decoupling capacitor in an unfavourable position could
do more damage than would completely omitting the
capacitor. In the correct location it could be the difference
between mediocre results and the ultimate achievement.
The reference frequency dividers and the STM mode
selectors operate in a similar manner in a positive supply
voltage application. The only difference is that pins
formerly connected to ground should now be connected to
VCC (+5 V). Pins connected to VEE should continue to be
connected to VEE, as connecting these pins to ground
(0 V) will damage the IC.
RF INPUT AND OUTPUTS
All RF inputs, outputs and internal signals of the
TZA3004HL are referenced to pins GND. In the positive
supply voltage application, this means that all RF signals
are referenced to VCC. Therefore a clean VCC rail is of
ultimate importance for proper RF performance. The best
performance is obtained when the transmission line
reference plane is also decoupled to VCC. Careful design
of VCC and good decoupling schemes should be taken into
account. While designing the printed-circuit board, keep in
mind that the VCC has become what was formerly ground.
2000 Nov 28
12
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4 OC3/12
TZA3004HL
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
MIN.
−6
MAX.
+0.5
UNIT
VEE
Vn
negative supply voltage
DC voltage on pins
V
V
CLOOP, CLOOPQ, DLOOP, DLOOPQ, CREF, CREFQ, DIN, DINQ, −1
+0.5
DOUT, DOUTQ, COUT and COUTQ
ENL, LOCK and LOS,
DREF19, DREF39, SEL155, PC and AREF
CAPUPQ and CAPDOQ
input current on pins
VEE − 0.5 +5.5
VEE − 0.5 +0.5
VEE + 0.5 −0.5
V
V
V
In
ENL
−
1
mA
mA
mW
°C
CREF, CREFQ, DIN and DINQ
total power dissipation
ambient temperature
−20
−
+10
Ptot
Tamb
Tj
700
−40
−
+85
junction temperature
+110
+150
°C
Tstg
storage temperature
−65
°C
HANDLING INSTRUCTIONS
Precautions should be taken to avoid damage through electrostatic discharge.
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
VALUE
46
UNIT
K/W
K/W
Rth(j-s)
Rth(j-a)
thermal resistance from junction to solder point
thermal resistance from junction to ambient
in free air; note 1
67
Note
1. Thermal resistance from junction to ambient is determined with the IC soldered on a standard single sided
57 × 57 × 1.6 mm FR4 epoxy PCB with 35 µm thick copper traces. The measurements are performed in still air.
2000 Nov 28
13
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4 OC3/12
TZA3004HL
CHARACTERISTICS
VEE = −3.3 V; Tamb = −40 to +85 °C; typical values measured at Tamb = 25 °C; all voltages are measured with respect
to GND; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VEE
negative supply voltage
negative supply current
total power dissipation
see Fig.12; note 1
open outputs; see Fig.13
−3.50
−3.30
112
−3.10
155
V
IEE
−
−
mA
Ptot
370
550
mW
Data and clock inputs: pins DIN, DINQ, CREF and CREFQ
Vi(p-p)
input voltage
(peak-to-peak value)
50 Ω measurement system;
see Fig.10; notes 2 and 3
7
200
2.5
450
7
mV
mV
Vi(sens)(p-p) input sensitivity
(peak-to-peak value)
50 Ω measurement system;
notes 2 and 4
−
VIO
VI
DC input offset voltage
input voltage
50 Ω measurement system
50 Ω measurement system
single-ended; see Fig.4; note 5
−3
0
+3
mV
mV
Ω
−600
−
−200
50
+250
−
Zi
input impedance
Data and clock outputs: pins DOUT, DOUTQ, DLOOP, DLOOPQ, COUT, COUTQ, CLOOP and CLOOPQ
Vo(p-p)
output voltage swing
(peak-to-peak value)
50 Ω measurement system;
single-ended; see Fig.10
default adjustment; note 6
special adjustment; note 7
170
50
−600
−
200
−
210
400
0
mV
mV
mV
Ω
VO
output voltage
−
Zo
output impedance
clock output rise time
clock output fall time
data output rise time
data output fall time
data-to-clock delay
single-ended
100
90
−
tr(C)
tf(C)
tr(D)
tf(D)
td(D-C)
differential; 20% to 80%
differential; 20% to 80%
differential; 20% to 80%
differential; 20% to 80%
see Fig.11; note 8
−
−
ps
−
90
−
ps
−
200
200
280
−
ps
−
−
ps
250
310
ps
Output amplitude adjustment: pin AREF
VAREF
output amplitude reference
voltage
floating pin
−110
−100
−90
mV
Power control output: pin PC
gm
IO
transconductance
output current
−84
−60
−42
mA/V
mA
1
−
3.5
Loop mode enable input: pin ENL
VIL
VIH
LOW-level input voltage
HIGH-level input voltage
−
−
−
0.8
V
V
2.0
−
Phase lock indicator: pin LOCK
VOL
VOH
LOW-level output voltage
HIGH-level output voltage
note 9
note 9
−0.6
−
−
−
V
V
−
3.3
2000 Nov 28
14
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4 OC3/12
TZA3004HL
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Loss of signal indicator: pin LOS
VOL
LOW-level output voltage
HIGH-level output voltage
assert time
note 9
−0.6
−
−
−
V
VOH
note 9
−
−
−
−
−
3.3
−
V
tas
note 10
note 10
note 10
note 10
0.1
µs
tdas
de-assert time
10
−
µs
BERas
BERdas
assert bit error rate
de-assert bit error rate
5 × 10−2
1 × 10−3
−
BER
BER
−
PLL characteristics
tacq
acquisition time
CREF = 19.44 MHz
CREF = 38.88 MHz
STM1/OC3 mode; note 11
f = 6.5 kHz
−
−
100
50
200
200
µs
µs
Jtol(p-p)
jitter tolerance
(peak-to-peak value)
1.5
>10
1.3
0.8
−
−
−
UI
UI
UI
f = 65 kHz
0.15
0.15
f = 1 MHz
STM4/OC12 mode; note 11
f = 25 kHz
1.5
>10
1.3
−
−
−
UI
UI
UI
f = 250 kHz
0.15
0.15
f = 5 MHz
0.35
Jgen(p-p)
jitter generation
(peak-to-peak value)
STM1/OC3 mode; note 12
f = 500 Hz to 1.3 MHz
f = 12 kHz to 1.3 MHz
f = 65 kHz to 1.3 MHz
STM4/OC12 mode; note 12
f = 1 kHz to 5 MHz
f = 12 kHz to 5 MHz
f = 250 kHz to 5 MHz
STM1/OC3 mode; note 12
f = 500 Hz to 1.3 MHz
f = 12 kHz to 1.3 MHz
f = 65 kHz to 1.3 MHz
STM4/OC12 mode; note 12
f = 1 kHz to 5 MHz
f = 12 kHz to 5 MHz
f = 250 kHz to 5 MHz
note 13
−
−
−
0.039
0.032
0.032
0.50
0.10
0.10
UI
UI
UI
−
−
−
0.050
0.040
0.052
0.50
0.10
0.10
UI
UI
UI
Jgen(rms)
jitter generation (RMS value)
−
−
−
0.0060
0.0046
0.0041
−
−
−
UI
UI
UI
−
−
−
−
0.0093
0.0079
0.0081
2000
−
−
−
−
UI
UI
UI
TDR
transitionless data run
bits
2000 Nov 28
15
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4 OC3/12
TZA3004HL
Notes to the characteristics
1. Typical power supply voltage for the voltage regulator is −4.5 V (see Fig.6).
2. It is assumed that both CML inputs carry a complementary signal with the specified peak-to-peak value (true
differential excitation).
3. The specified input voltage range is the guaranteed and tested range for proper operation; BER < 1 × 10−10
.
4. An input sensitivity of 7 mV (p-p) for BER < 1 10−10 is guaranteed. The typical input sensitivity for BER < 1 × 10−10
is 2.5 mV (p-p).
5. CML inputs are terminated internally using on-chip resistors of 50 Ω connected to ground.
6. Output voltage range with default reference voltage on pin AREF (floating).
7. Output voltage range with adjustment of voltage on pin AREF (see Section “Output amplitude reference”).
8. Measured with 1010 data pattern, single-ended output signals and rising edges of the signals on
pins COUT to DOUT or pins CLOOP to DLOOP. It should be noted that small deviations of the specified value are
possible if measured differentially.
9. External pull-up resistor of 10 kΩ connected to supply voltage of +3.3 V.
10. LOS assert or de-assert timing and BER level are for indication only. The values are neither production tested nor
guaranteed.
11. Measured in accordance with ITU specification G.958. Measured on demoboard OM5802 for STM1/OC3 and
STM4/OC12. For more information, see “Application note AN97065”.
12. Measured in accordance with ITU specification G.813 and 1 dB above the system input sensitivity power level.
Measured on demoboard OM5802 for STM1/OC3 and STM4/OC12.
13. TDR is bit rate independent.
2000 Nov 28
16
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4 OC3/12
TZA3004HL
CML INPUT
CML OUTPUT
V
I(max)
GND
GND
V
O(max)
V
V
IQH
OQH
V
V
OH
IH
V
V
i(p-p)
o(p-p)
V
V
V
IQL
V
OQL
OO
IO
V
V
OL
IL
V
V
O(min)
I(min)
MGK144
Fig.10 Logic level symbol definitions for CML.
GND
COUT or
CLOOP
−200 mV
t
d(D-C)
GND
DOUT or
DLOOP
−200 mV
MGL672
Fig.11 Data-to-clock delay for CML outputs: COUT to DOUT or CLOOP to DLOOP.
17
2000 Nov 28
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4 OC3/12
TZA3004HL
TYPICAL PERFORMANCE CHARACTERISTICS
MGL650
MGU252
−3.30
160
handbook, halfpage
handbook, halfpage
I
EE
V
EE
(mA)
(V)
120
−3.35
80
40
−3.40
−3.45
−40
0
−40
0
40
80
120
0
40
80
120
T (°C)
T (°C)
It should be noted that the voltage on pins VEE is regulated by the
power controller.
Fig.12 Supply voltage as a function of the
temperature.
Fig.13 Supply current as a function of the
temperature.
2000 Nov 28
18
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4 OC3/12
TZA3004HL
MGL657
MGL658
1
1
handbook, halfpage
handbook, halfpage
BER
BER
−1
−1
10
10
−2
−2
10
10
−3
−3
10
10
−4
−4
10
10
−5
−5
10
10
−6
−6
10
10
−7
−7
10
10
−8
−8
10
10
−9
−9
10
10
−10
−10
10
10
−11
−11
10
10
0
0.5
1
1.5
0
0.5
1
1.5
V
(mV)
V
(mV)
i(p-p)
i(p-p)
A complementary input signal of the indicated
value is applied to pins DIN and DINQ.
A complementary input signal of the indicated
value is applied to pins DIN and DINQ.
Fig.14 Bit error rate as a function of the input signal
in STM1/OC3 mode (155.52 Mbits/s).
Fig.15 Bit error rate as a function of the input signal
in STM4/OC12 mode (622.08 Mbits/s).
2000 Nov 28
19
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4 OC3/12
TZA3004HL
MGL659
3
10
J
tol(p-p)
(UI)
2
10
10
(1)
1
(2)
−1
10
2
3
4
1
10
10
10
10
f (kHz)
(1) Device performance measured on OM5802 demoboard.
(2) ITU specification template.
Fig.16 Jitter tolerance as a function of the jitter frequency in the STM1/OC3 mode (155.52 Mbits/s).
MGL660
3
10
J
tol(p-p)
(UI)
2
10
(1)
(2)
10
1
−1
10
2
3
4
1
10
10
10
10
f (kHz)
(1) Device performance measured on OM5802 demoboard.
(2) ITU specification template.
Fig.17 Jitter tolerance as a function of the jitter frequency in the STM4/OC12 mode (622.08 Mbits/s).
2000 Nov 28
20
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4 OC3/12
TZA3004HL
MGS228
200 mV/div
Measured single-ended.
Fig.18 Data and clock output waveforms in the STM4/OC12 mode (622.08 Mbits/s).
MGT219
Measured differentially.
Fig.19 Clock output waveform in the STM4/OC12 mode (622.08 Mbits/s).
21
2000 Nov 28
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4 OC3/12
TZA3004HL
MGT220
Measured differentially.; PRBS 223 − 1 pattern.
Fig.20 Data output waveform in the STM4/OC12 mode (622.08 Mbits/s).
2000 Nov 28
22
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4 OC3/12
TZA3004HL
APPLICATION INFORMATION
+3.3 V
10 kΩ
CAPUPQ
15
LOS
39
12
+3.3 V
10 kΩ
100 nF
100 nF
16
CAPDOQ
LOCK
DIN
DOUT
42
43
45
46
33
34
PRE-
DINQ
DOUTQ
COUT
AMP
normal
output
TZA3004HL
COUTQ
DLOOP
6
7
3
4
DLOOPQ
CLOOP
loop
output
CREF
21
22
38.88/19.44 MHz
system clock
CREFQ
CLOOPQ
ENL
output
select
1
48
30
DREF19
DREF39
AREF
9
SEL155
V
EE
24
37
PC
25
27
28
31
(1)
V
V
V
EE3 EE4
V
GND
EE1
EE2
17
100
nF
β ≈ 100
2 Ω
1
kΩ
1
kΩ
3.3
nF
1 µF
2 Ω
1 µH
−4.5 V
MGU257
(1) All pins GND must be connected directly to the PCB ground plane (pins 2, 5, 8, 10, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44 and 47).
(2) L1 = RF choke type Murata BLM21.
Fig.21 Application diagram showing the TZA3004HL configured for the STM4/OC12 mode (622.08 Mbits/s).
2000 Nov 28
23
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4 OC3/12
TZA3004HL
V
CC
LOS
CAPUPQ
15
39
12
LOS
100 nF
100 nF
16
10 kΩ
V
CC
CAPDOQ
LOCK
LOCK
10 kΩ
DIN
33
34
DOUT
PRE-
AMP
DINQ
42
43
45
46
DOUTQ
COUT
normal
output
unused
output
=
=
TZA3004HL
COUTQ
DLOOP
6
7
3
4
CREF
DLOOPQ
CLOOP
21
22
39 MHz
system clock
loop
output
main
CREFQ
(3)
output
CLOOPQ
ENL
output
select
DREF19
DREF39
1
V
9
CC
AREF
48
24
5
13, 18, 19,
36, 40
i.c.
SEL155
30
V
CC
25
27
28
31
37
PC
(1)
V
V
V
EE3 EE4
V
GND
EE1
EE2
17
100
nF
β ≈100
V
CC
2 Ω
1
kΩ
1
kΩ
3.3
nF
1 µF
2 Ω
(2)
L1
V
V
CC
CC
MGU256
(1) (1) All pins GND must be connected directly to VCC on the PCB plane of +5 V (pins 2, 5, 8, 10, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44 and 47).
(2) L1 = RF choke type Murata BLM201, 1 µH.
(3) The loop mode outputs are used as main outputs:
pin ENL = HIGH-level selects loop mode outputs
pin ENL = LOW-level selects loop mode and normal mode outputs simultaneously.
Fig.22 Application diagram showing the TZA3004HL configured for the STM4/OC12 mode (622.08 Mbits/s) with
a positive supply voltage application.
2000 Nov 28
24
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4 OC3/12
TZA3004HL
PACKAGE OUTLINE
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
c
y
X
36
25
A
E
37
24
Z
E
e
H
E
A
2
A
(A )
3
A
1
w M
p
θ
pin 1 index
b
L
p
L
13
48
detail X
1
12
Z
v M
D
A
e
w M
b
p
D
B
H
v
M
B
D
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.20 1.45
0.05 1.35
0.27 0.18 7.1
0.17 0.12 6.9
7.1
6.9
9.15 9.15
8.85 8.85
0.75
0.45
0.95 0.95
0.55 0.55
1.60
mm
0.25
0.5
1.0
0.2 0.12 0.1
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
99-12-27
00-01-19
SOT313-2
136E05
MS-026
2000 Nov 28
25
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4 OC3/12
TZA3004HL
SOLDERING
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Manual soldering
Wave soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
2000 Nov 28
26
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4 OC3/12
TZA3004HL
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
BGA, LFBGA, SQFP, TFBGA
WAVE
not suitable
REFLOW(1)
suitable
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS
not suitable(2)
suitable
PLCC(3), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
suitable
not recommended(3)(4) suitable
not recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2000 Nov 28
27
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4 OC3/12
TZA3004HL
DATA SHEET STATUS
PRODUCT
DATA SHEET STATUS
STATUS
DEFINITIONS (1)
Objective specification
Development This data sheet contains the design target or goal specifications for
product development. Specification may change in any manner without
notice.
Preliminary specification Qualification
This data sheet contains preliminary data, and supplementary data will be
published at a later date. Philips Semiconductors reserves the right to
make changes at any time without notice in order to improve design and
supply the best possible product.
Product specification
Production
This data sheet contains final specifications. Philips Semiconductors
reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Note
1. Please consult the most recently issued data sheet before initiating or completing a design.
DEFINITIONS
DISCLAIMERS
Short-form specification
The data in a short-form
Life support applications
These products are not
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes
Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
the use of any of these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.
Application information
Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2000 Nov 28
28
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4 OC3/12
TZA3004HL
NOTES
2000 Nov 28
29
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4 OC3/12
TZA3004HL
NOTES
2000 Nov 28
30
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4 OC3/12
TZA3004HL
NOTES
2000 Nov 28
31
Philips Semiconductors – a worldwide company
Argentina: see South America
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,
Tel. +61 2 9704 8141, Fax. +61 2 9704 8139
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210
Norway: Box 1, Manglerud 0612, OSLO,
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Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773
Pakistan: see Singapore
Belgium: see The Netherlands
Brazil: see South America
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
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Tel. +48 22 5710 000, Fax. +48 22 5710 001
Portugal: see Spain
Romania: see Italy
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
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Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Colombia: see South America
Czech Republic: see Austria
Tel. +65 350 2538, Fax. +65 251 6500
Slovakia: see Austria
Slovenia: see Italy
Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,
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South America: Al. Vicente Pinzon, 173, 6th floor,
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Tel. +55 11 821 2333, Fax. +55 11 821 2382
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Tel. +49 40 2353 60, Fax. +49 40 2353 6300
Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 93 301 6312, Fax. +34 93 301 4107
Hungary: see Austria
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745
India: Philips INDIA Ltd, Band Box Building, 2nd floor,
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Tel. +91 22 493 8541, Fax. +91 22 493 0966
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263
Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080
Taiwan: Philips Semiconductors, 5F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2451, Fax. +886 2 2134 2874
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
60/14 MOO 11, Bangna Trad Road KM. 3, Bagna, BANGKOK 10260,
Tel. +66 2 361 7910, Fax. +66 2 398 3447
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813
Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),
Tel. +39 039 203 6838, Fax +39 039 203 6800
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Uruguay: see South America
Vietnam: see Singapore
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Middle East: see Italy
Tel. +381 11 3341 299, Fax.+381 11 3342 553
For all other countries apply to: Philips Semiconductors,
Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN,
The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
70
SCA
© Philips Electronics N.V. 2000
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
403510/50/02/pp32
Date of release: 2000 Nov 28
Document order number: 9397 750 07684
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