TZA3005 [NXP]
SDH/SONET STM1/OC3 and STM4/OC12 transceiver; SDH / SONET STM1 / OC3和STM4 / OC12收发器
| 型号： | TZA3005 |
| 厂家： | 
NXP |
| 描述： | SDH/SONET STM1/OC3 and STM4/OC12 transceiver |
| 文件： | 总24页 (文件大小：529K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
TZA3005
SDH/SONET STM1/OC3 and
STM4/OC12 transceiver
1997 Aug 05
Objective specification
File under Integrated Circuits, IC19
Philips Semiconductors
Objective specification
SDH/SONET STM1/OC3 and
STM4/OC12 transceiver
TZA3005
• Section repeaters
FEATURES
• Fiber optic test equipment.
• Fiber optic terminators
• Supports STM1/OC3 (155.52 Mbits/s) and STM4/OC12
(622.08 Mbits/s)
• Supports 19.44, 38.88, 51.84 and 77.76 MHz reference
clock frequencies
GENERAL DESCRIPTION
• Meets Bellcore, ANSI and ITU-T specifications
• Integral high-frequency PLL for clock generation
• Interface to TTL logic
The TZA3005 SDH/SONET transceiver chip is a fully
integrated serialization/deserialization
SDH/SONET STM4/OC12 (622.08 Mbits/s) and
STM1/OC3 (155.52 Mbits/s) interface device. It performs
all necessary serial-to-parallel and parallel-to-serial
functions in accordance with SDH/SONET transmission
standards. It is suitable for SONET-based applications and
can be used in conjunction with the TZA3004 clock
recovery device, the TZA3000 optical receiver and the
TZA3001 laser driver. Figure 13 shows a typical network
application.
• Low jitter PECL (Positive Emitter Coupled Logic)
interface.
• 4- or 8-bit STM1/OC3 TTL/CMOS data path
• 4- or 8-bit STM4/OC12 TTL/CMOS data path
• No external filter components required
• QFP64 package
• Diagnostic and line loopback modes
• Lock detect
A high-frequency phase-locked loop is used for on-chip
clock synthesis, which means a slower external transmit
reference clock can be used. A 19.44, 38.88,
• LOS (Loss of Signal) input
51.84 or 77.76 MHz reference clock can be used, in
support of existing system clocking schemes. The
TZA3005 performs SDH/SONET frame detection.
• Low power (900 mW typically)
APPLICATIONS
The low jitter PECL interface ensures that Bellcore, ANSI,
and ITU-T bit-error rate requirements are satisfied. The
TZA3005 comes in a compact QFP64 package.
• SDH/SONET modules
• SDH/SONET-based transmission systems
• SDH/SONET test equipment
• ATM over SDH/SONET
• Add drop multiplexers
• Broadband cross-connects
ORDERING INFORMATION
TYPE
PACKAGE
NUMBER
NAME
DESCRIPTION
VERSION
TZA3005H
QFP64
plastic quad flat package; 64 leads (lead length 1.6 mm); body
SOT393-1
14 × 14 × 2.7 mm
1997 Aug 05
2
Philips Semiconductors
Objective specification
SDH/SONET STM1/OC3 and
STM4/OC12 transceiver
TZA3005
BLOCK DIAGRAM
TRANSMITTER
31
LLEN
(1)
61
TXPD0 to
TXPD7
8
8 : 1 PARALLEL-
TO-SERIAL
2
2
17, 18
21, 20
TXSD and
TXSDQ
D
MUX
MUX
2
TXPCLK
TIMING
GENERATOR
TXSCLK and
TXSCLKQ
62
63
SYNCLKDIV
LOCKDET
13
48
STOPTX
MRST
CLOCK
SYNTHESIZER
50
30
64
STOPRX
BUSWIDTH
19MHzO
on-chip capacitor
REFSEL0 and
REFSEL1
2
2
3, 4
49
MODE
REFCLK and
REFCLKQ
15, 14
RECEIVER
22
23
SDTTL
(2)
SDPECL
8
1 : 8 SERIAL-
TO-PARALLEL
RXPD0 to
RXPD7
33
47
35
TIMING
GENERATOR
RXPCLK
FP
OOF
FRAME
BYTE
DETECT
32
DLEN
24, 25
2
2
2
RXSD and
RXSDQ
D
MUX
2
27, 28
RXSCLK and
RXSCLKQ
52
51
TZA3005
V
CC(RXD)
MUX
GND
RXD
38,
46
34,
42
1
2
5
8
6
7
9
12
16
19
TXOUT
26
29
V
V
V
GND
GND
GND
RXOUT
CC(TXCORE)
GND
CCD(SYN)
V
SUB
V
CCA(SYN)
GND
TXCORE
DGND
CC(TXOUT)
CC(RXOUT)
MGK484
GND
SYN
AGND
SYNO
RXCORE
V
CC(RXCORE)
SYN
(1) Pins 53 to 60.
(2) Pins 36, 37, 39, 40, 41, 43, 44 and 45.
Fig.1 Block diagram.
3
1997 Aug 05
Philips Semiconductors
Objective specification
SDH/SONET STM1/OC3 and
STM4/OC12 transceiver
TZA3005
PINNING
SYMBOL
PIN
TYPE(1)
DESCRIPTION
supply voltage (transmitter core)
VCC(TXCORE)
GNDTXCORE
REFSEL0
REFSEL1
DGNDSYN
VCCD(SYN)
VCCA(SYN)
AGNDSYN
GNDSYNO
STOPSYN
RSTRX
1
S
S
I
2
ground (transmitter core)
reference clock select input 0
reference clock select input 1
digital ground (synthesizer)
digital supply voltage (synthesizer)
analog supply voltage (synthesizer)
analog ground (synthesizer)
ground (synthesizer output)
test input : synthesizer section shut down
test input : reset receive logic
ground (substrate)
3
4
I
5
S
S
S
S
S
I
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
I
GNDSUB
STOPTX
REFCLKQ
REFCLK
VCC(TXOUT)
TXSD
S
I
test input : transmit section shut down
inverted reference clock input
reference clock input
I
I
S
O
O
S
O
O
I
supply voltage (transmitter output)
serial data output
TXSDQ
inverted serial data output
ground (transmitter output)
inverted serial clock output
serial clock output
GNDTXOUT
TXSCLKQ
TXSCLK
SDTTL
TTL signal detect input
SDPECL
RXSD
I
PECL signal detect input
serial data input
I
RXSDQ
I
inverted serial data input
supply voltage (receiver core)
serial clock input
VCC(RXCORE)
RXSCLK
RXSCLKQ
GNDRXCORE
BUSWIDTH
LLEN
S
I
I
inverted serial clock input
ground (receiver core)
S
I
4/8 bus width select input
line loopback enable input (active LOW)
diagnostic loopback enable input (active LOW)
out of frame enable input
ground (parallel output)
I
DLEN
I
OOF
I
GNDRXOUT
FP
S
O
O
O
S
O
O
frame pulse output
RXPD0
parallel data output 0
RXPD1
parallel data output 1
VCC(RXOUT)
RXPD2
supply voltage (parallel output)
parallel data output 2
RXPD3
parallel data output 3
1997 Aug 05
4
Philips Semiconductors
Objective specification
SDH/SONET STM1/OC3 and
STM4/OC12 transceiver
TZA3005
SYMBOL
RXPD4
PIN
TYPE(1)
DESCRIPTION
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
O
S
O
O
O
S
O
I
parallel data output 4
GNDRXOUT
RXPD5
ground (receiver output)
parallel data output 5
RXPD6
parallel data output 6
RXPD7
parallel data output 7
VCC(RXOUT)
RXPCLK
MRST
supply voltage (receiver output)
receive parallel clock output
master reset (active LOW)
MODE
I
serial data rate select STM1/STM4
receiver section shut down
ground (receiver digital section)
supply voltage (receiver digital section)
parallel data input 0
STOPRX
GNDRXD
VCC(RXD)
TXPD0
I
S
S
I
TXPD1
I
parallel data input 1
TXPD2
I
parallel data input 2
TXPD3
I
parallel data input 3
TXPD4
I
parallel data input 4
TXPD5
I
parallel data input 5
TXPD6
I
parallel data input 6
TXPD7
I
parallel data input 7
TXPCLK
SYNCLKDIV
LOCKDET
19MHzO
I
transmit parallel clock input
transmit byte/nibble clock output (synchronous)
lock detect
O
O
O
19 MHz output reference clock
Note
1. Pin type abbreviations: O = Output, I = Input, S = power Supply.
1997 Aug 05
5
Philips Semiconductors
Objective specification
SDH/SONET STM1/OC3 and
STM4/OC12 transceiver
TZA3005
V
1
2
48 MRST
CC(TXCORE)
GND
RXPCLK
47
46
TXCORE
V
REFSEL0
REFSEL1
3
CC(RXOUT)
4
45 RXPD7
RXPD6
DGND
SYN
5
44
43 RXPD5
V
6
CCD(SYN)
V
GND
7
42
41
CCA(SYN)
RXOUT
AGND
SYN
RXPD4
8
TZA3005H
GND
9
40 RXPD3
SYNO
STOPSYN
RSTRX
10
11
12
13
14
15
16
39 RXPD2
V
38
CC(RXOUT)
GND
SUB
37 RXPD1
36 RXPD0
STOPTX
REFCLKQ
REFCLK
FP
35
34
GND
RXOUT
V
33 OOF
CC(TXOUT)
MGK483
Fig.2 Pin configuration.
6
1997 Aug 05
Philips Semiconductors
Objective specification
SDH/SONET STM1/OC3 and
STM4/OC12 transceiver
TZA3005
FUNCTIONAL DESCRIPTION
Introduction
Transmitter operation
The TZA3005 transceiver chip performs the serializing
stage in the processing of a transmit STM1/OC3 or
STM4/OC12 serial bitstream. It converts the byte
serial 19.44, 38.88 or 77.76 Mbytes/s data stream to bit
serial format at 155.52 or 622.08 Mbits/s. Diagnostic
loopback is provided (transmitter to receiver). Line
loopback is also provided (receiver to transmitter).
The TZA3005 transceiver implements SDH/SONET
serialization/deserialization, transmission and frame
detection/recovery functions. The block diagram in Fig.1
illustrates the basic operation of the chip. The TZA3005
can be used to implement the front-end of SONET
equipment, which consists primarily of the serial transmit
and receive interfaces. The chip handles all the functions
of these two elements, including parallel-to-serial and
serial-to-parallel conversion, clock generation, and system
timing. The system timing circuitry handles data stream
management, framing, and clock distribution throughout
the front-end.
An integral frequency synthesizer, consisting of a
phase-locked loop with a divider in the loop, can be used
to generate a high-frequency bit clock from a 19.44, 38.88,
51.84 or 77.76 MHz reference frequency.
CLOCK SYNTHESIZER
The TZA3005 is divided into a transmitter section and a
receiver section. The sequence of operations is as follows:
The serial output clock is generated by the clock
synthesizer (see Fig.1). This signal is phase synchronized
with the input reference clock (REFCLK). Two output clock
frequencies are available, synthesized from any of four
SDH/SONET reference frequencies.
• Transmitter operations:
– 4- or 8-bit parallel input
– Parallel-to-serial conversion
– Serial output
The MODE input is used to select the serial output clock
frequency: 622.08 MHz for STM4/OC12 or 155.52 MHz
for STM1/OC3 (see Table 1).
• Receiver operations:
– Serial input
Table 1 Clock frequency options
– Frame detection
OUTPUT CLOCK
FREQUENCY
– Serial-to-parallel conversion
– 4- or 8-bit parallel output.
MODE
OPERATING MODE
1
0
622.08 MHz
155.52 MHz
STM4/OC12
STM1/OC3
Internal clocking and control functions are transparent to
the user. Details of data timing can be found in Figs 3 to 9.
Table 2 Suggested interface devices
DATA RATE
(Mbits/s)
MANUFACTURER
Philips
TYPE
FUNCTION
TZA3004
TZA3000
TZA3001
SA5225
SA5223
PM5312
PM5355
622 or 155
622
clock recovery
optical receiver
laser driver
622
155
limiting amplifier
155
transimpedance amplifier
PMC-Sierra
155 or 622
622
transport terminal transceiver
Saturn user network interface
1997 Aug 05
7
Philips Semiconductors
Objective specification
SDH/SONET STM1/OC3 and
STM4/OC12 transceiver
TZA3005
The REFSEL0 and REFSEL1 inputs, in combination with
the MODE input, select the ratio between the output clock
frequency and the reference input frequency (see
Table 3). This ratio is adjusted for each of the four options
so that the reference frequency selected by REFSEL0 and
REFSEL1 is the same for all operating modes.
The SYNCLKDIV output is a byte rate version of TXSCLK.
For STM4/OC12, the SYNCLKDIV frequency is
77.76 or 155.52 MHz and for STM1/OC3, it is 19.44 or
38.88 MHz. SYNCLKDIV is intended for use as a byte
speed clock for upstream multiplexing and overhead
processing circuits. Using SYNCLKDIV for upstream
circuits will ensure a stable frequency and phase
relationship is maintained between the data entering and
leaving the TZA3005.
To ensure the TXSCLK frequency is accurate enough to
operate in a SONET system, the REFCLK input must be
generated from a differential PECL crystal oscillator with a
frequency accuracy better than 4.6 ppm for compliance
with “ITU G.813 (option 1)”, or 20 ppm for “ITU G.813
(option 2)”.
For parallel-to-serial conversion, the parallel input data is
transferred from the TXPCLK byte clock timing domain to
the internally generated byte clock timing domain, which is
phase aligned to TXPCLK.
The maximum value specified for reference clock jitter
must be guaranteed over the a 12 kHz to 1 MHz
bandwidth in order to comply with SONET jitter
requirements (see Table 4).
The timing generator also produces a feedback reference
clock for the clock synthesizer. A counter divides the
synthesized clock down to the same frequency as the
reference clock REFCLK. The PLL in the clock synthesizer
maintains the stability of the synthesized clock by
comparing the phase of the feedback reference clock with
that of the reference clock (REFCLK). The modulus of the
counter is a function of the reference clock frequency and
the operating frequency.
The on-chip PLL contains a phase detector, a loop filter
and a VCO. The phase detector compares the phases of
the output and REFCLK input signals. The loop filter
converts the phase detector output into a smooth DC
voltage that is used to vary the VCO frequency.
The VCO control voltage generated by the loop filter is
referenced to the average DC level in the output pulse train
generated by the phase discriminator. The corner
frequency is optimized to minimize output phase jitter.
PARALLEL-TO-SERIAL CONVERTER
The parallel-to-serial converter shown in Fig.1 contains
two byte-wide registers. The first register latches the data
from the parallel bus (TXPD0 to TXPD7) on the rising
edge of TXPCLK. The second register is a parallel loading
shift register which takes its input from the first register.
Table 3 Reference frequency options
INPUT CLOCK
REFSEL0 REFSEL1
FREQUENCY
The parallel data transfer is controlled by an internally
generated byte clock, which is phase aligned with the
transmit serial clock (see Section “Timing generator”). The
TXSCLK signal is used to shift the serial data out of the
second register.
0
0
1
1
0
1
0
1
19.44 MHz
38.88 MHz
51.84 MHz
77.76 MHz
Receiver operation
Table 4 Reference jitter limits
The TZA3005 transceiver chip performs the first stage in
the digital processing of a STM1/OC3 or STM4/OC12
serial bitstream. It converts the 155.52 or 622.08 Mbits/s
data stream into a 19.44 or 77.76 Mbytes/s serial format.
In nibble mode, a parallel data stream of
38.88 or 155.52 MHz is generated. Diagnostic (transmitter
to receiver) and line (receiver to transmitter) loopback
modes are provided.
MAXIMUM REFERENCE
CLOCK JITTER IN
12 kHz TO 1 MHz BAND
OPERATING MODE
84 ps (p-p)
STM4/OC12
STM1/OC3
336 ps (p-p)
TIMING GENERATOR
FRAME AND BYTE BOUNDARY DETECTION
The timing generator performs two functions. It provides a
byte rate version of the TXSCLK along with a mechanism
for phase aligning the incoming byte clock and the clock
that loads the parallel-to-serial shift register.
The frame and byte boundary detection circuitry searches
the incoming data for three consecutive A1 bytes followed
immediately by three consecutive A2 bytes. Framing
1997 Aug 05
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Philips Semiconductors
Objective specification
SDH/SONET STM1/OC3 and
STM4/OC12 transceiver
TZA3005
pattern detection is enabled and disabled by the
TXPD7 is the most significant bit and TXPD4 is the least
significant bit.
Out-Of-Frame (OOF) input. Detection is enabled by a
rising edge on OOF, and remains enabled while OOF is
HIGH. It is disabled when a framing pattern is detected and
OOF is no longer HIGH. When framing pattern detection is
enabled, the framing pattern is used to locate byte and
frame boundaries in the incoming data stream (Receive
Serial Data (RXSD) or looped transmitter data). The timing
generator block uses the located byte boundary to divide
the incoming data stream into bytes for output on the
parallel output data bus (RXPD0 to RXPD7). When a
48-bit pattern matching the framing pattern is detected, the
frame boundary is signalled on the Frame Pulse (FP)
output. When framing pattern detection is disabled, the
byte boundary is frozen. Only framing patterns aligned to
the fixed byte boundary are signalled on the FP output.
Parallel clock input (TXPCLK)
This is a 19.44, 38.88, 77.76 or 155.52 MHz nominally
50% duty factor TTL level input clock, to which
TXPD0 to TXPD7 are aligned. TXPCLK is used to transfer
the data on the inputs to a holding register in the
parallel-to-serial converter.
The rising edge of TXPCLK samples TXPD0 to TXPD7.
After a master reset, one rising edge of TXPCLK is
required to fully initialize the internal data path.
RECEIVER INPUT SIGNALS
Receive Serial Data (RXSD and RXSDQ)
It is extremely unlikely that random data in an STM1/OC3
or STM4/OC12 data stream will replicate the 48-bit
framing pattern. Therefore, the time taken to detect the
beginning of the frame should be less than 250 µs (as
specified in “ITU G.783”), even for extremely high bit error
rates.
These differential PECL serial data input signals are
normally connected to an optical receiver module or to the
TZA3004 data and clock recovery unit, and are clocked by
the RXSCLK and RXSCLKQ inputs.
Receive serial clock (RXSCLK and RXSCLKQ)
Once down-stream overhead circuitry has verified that
frame and byte synchronization are correct, the OOF input
can be set LOW to prevent the frame search process trying
to synchronize to a mimic frame pattern.
This differential PECL recovered clock signal is
synchronized to the RXSD inputs. It is used by the receive
section as the master clock for framing and deserialization
functions.
SERIAL-TO-PARALLEL CONVERTER
Out-Of-Frame (OOF)
A delay of between 1.5 and 2.5 byte periods (or 12 to 20
serial bit periods measured from the first bit of an incoming
byte to the beginning of the parallel output of that byte)
occurs in the serial-to-parallel converter. The variation in
the delay depends on the alignment of the internal parallel
load timing, which is synchronized to the data byte
boundaries, with respect to the falling edge of RXPCLK,
which is independent of the byte boundaries. RXPCLK is
neither truncated nor extended during reframe sequences.
This TTL level indicator is used to enable framing pattern
detection logic in the TZA3005. The framing pattern
detection logic is enabled by a rising edge on OOF, and
remains enabled until a frame boundary is detected or
OOF goes LOW. OOF is an asynchronous signal with a
minimum pulse width of one RXPCLK period
(see Figs 3 and 9).
Signal Detect PECL (SDPECL)
This is a PECL signal with an internal pull-down resistor.
It is active HIGH when SDTTL is at logic 0 and active LOW
when SDTTL is at logic 1. This single-ended 10K PECL
input is driven by the external optical receiver module to
indicate a loss of received optical power (Loss of Signal).
When SDPECL is inactive, the data on the serial data input
pins (RXSD and RXSDQ) will be internally forced to a
constant zero. When SDPECL is active, data on the RXSD
and RXSDQ pins will be processed normally.
Transceiver pin descriptions
TRANSMITTER INPUT SIGNALS
Parallel data inputs (TXPD0 to TXPD7)
This is a 19.44, 38.88, 77.76 or 155.52 Mbytes/s TTL level
word, aligned to the TXPCLK parallel input clock. TXPD7
is the most significant bit (corresponding to bit 1 of each
PCM word, the first bit transmitted). TXPD0 is the least
significant bit (corresponding to bit 8 of each PCM word,
the last bit transmitted). TXPD0 to TXPD7 are sampled on
the rising edge of TXPCLK. If a 4-bit bus width is selected,
When SDTTL is to be connected to the optical receiver
module instead of SDPECL, SDPECL should be tied HIGH
to implement an active LOW signal detect, or left
unconnected to implement an active HIGH signal detect.
1997 Aug 05
9
Philips Semiconductors
Objective specification
SDH/SONET STM1/OC3 and
STM4/OC12 transceiver
TZA3005
Signal Detect TTL (SDTTL)
Reference select (REFSEL0 and REFSEL1)
This is a TTL signal with an internal pull-up resistor. It is
active HIGH when SDPECL is unconnected (logic 0),
active LOW when SDPECL is at logic 1. This single-ended
TTL input is driven by the external optical receiver module
to indicate a loss of received optical power. When SDTTL
is inactive, the data on RXSD and RXSDQ will be internally
forced to a constant zero. When SDTTL is active, data on
the RXSD and RXSDQ pins will be processed normally.
This TTL signal is used to select the reference clock
frequency (see Table 3).
Mode select (MODE)
This TTL signal is used to select the serial bit rate.
LOW selects 155.52 Mbits/s. HIGH selects
622.08 Mbits/s.
Test inputs (STOPSYN, STOPTX, STOPRX and RSTRX)
Table 5 SDPECL/SDTTL truth table
These active HIGH TTL signals are used to test internal
circuitry during production testing. All must be LOW during
normal operation. Internal pull-down resistors will hold all
four test pins LOW if not connected.
SDPECL
SDTTL
RXPD OUTPUT DATA
0 or floating
0
0
0 or floating
1 or floating
0
RXSD input data
RXSD input data
0
1
1
TRANSMITTER OUTPUT SIGNALS
1 or floating
Transmit clock outputs (TXSCLK and TXSCLKQ)
COMMON INPUT SIGNALS
This differential PECL transmit serial clock output can be
used to retime the TXSD signal. The clock will be
622.08 MHz or 155.52 MHz depending on the operating
mode.
Bus width selection (BUSWIDTH)
This TTL signal is used to select 4-bit or 8-bit operation for
the transmit and receive parallel interfaces. LOW selects a
4-bit bus width. HIGH selects an 8-bit bus width.
Transmit Serial Data (TXSD and TXSDQ)
These differential PECL serial data stream signals are
normally connected to an optical transmitter module or to
the TZA3001 laser driver.
Reference clock (REFCLK and REFCLKQ)
These differential PECL inputs supply the reference clock
for the internal bit clock frequency synthesizer.
Parallel clock (SYNCLKDIV)
Diagnostic loopback enable (DLEN)
This CMOS reference clock is generated by dividing the
internal bit clock by eight (or by four when BUSWIDTH is
LOW). It is normally used to coordinate byte-wide transfers
between upstream logic and the TZA3005.
This active LOW TTL input selects diagnostic loopback.
When DLEN is HIGH, the TZA3005 uses the primary data
(RXSD) and clock (RXSCLK) inputs. When LOW, the
TZA3005 uses the diagnostic loopback clock and data
from the transmitter.
Lock detect (LOCKDET)
This is an active HIGH CMOS output. When active, it
indicates that the transmit PLL is locked to the reference
clock input.
Master reset (MRST)
This is an active LOW TTL level reset input. SYNCLKDIV
does not toggle during reset.
RECEIVER OUTPUT SIGNALS
Line loopback enable (LLEN)
Parallel outputs (RXPD0 to RXPD7)
This active LOW TTL input selects line loopback. When
LLEN is LOW, the TZA3005 will route the data from the
RXSD and RXSCLK inputs to the TXSD and TXSCLK
outputs.
This is a 19.44, 38.88, 77.76 or 155.52 Mbytes/s parallel
CMOS data bus aligned to the parallel output clock
(RXPCLK). RXPD7 is the most significant bit
(corresponding to bit 1 of each PCM word, the first bit
received). RXPD0 is the least significant bit
(corresponding to bit 8 of each PCM word, the last bit
received). RXPD0 to RXPD7 are updated on the falling
1997 Aug 05
10
Philips Semiconductors
Objective specification
SDH/SONET STM1/OC3 and
STM4/OC12 transceiver
TZA3005
edge of RXPCLK. When a 4-bit bus width is selected,
TXPD7 is the most significant bit and bit 4 is the least
significant bit.
inputs, and a receive-to-transmit loopback can be
established at the serial data rate. Diagnostic loopback
and line loopback can be active at the same time.
19 MHz clock output (19MHzO)
Receiver framing
This is a 19 MHz CMOS clock output from the clock
synthesizer. It should be connected to the reference clock
input of the external clock recovery function (such as the
TZA3004).
A typical reframe sequence involving byte realignment is
shown in Figure 3. Frame and byte boundary detection is
enabled on the rising edge on OOF and remains enabled
while OOF is HIGH. Boundaries are recognized on receipt
of the third A2 byte, the first data byte to be reported with
the correct byte alignment on the outgoing data bus
(RXPD0 to RXPD7). FP goes HIGH for one RXPCLK
cycle.
Frame Pulse (FP)
This CMOS output detects frame boundaries in the
incoming data stream (RXSD). When framing pattern
detection is enabled (see Section “Out-Of-Frame (OOF)”),
FP goes HIGH for one cycle of RXPCLK when a 48-bit
sequence matching the framing pattern is detected on the
RXSD inputs. When framing pattern detection is disabled,
FP goes HIGH when, after byte alignment, the incoming
data stream matches the framing pattern. FP is updated on
the falling edge of RXPCLK.
When interfacing with a section terminating device, OOF
must remain HIGH for a full frame after the initial frame
pulse. This is to allow the section terminating device to
verify internally that frame and byte alignment are correct
(see Fig.4). Since at least one framing pattern will have
been detected since the rising edge of OOF, boundary
detection will be disabled when OOF goes LOW.
The frame and byte boundary detection block is activated
by a rising edge on OOF, and remains active until an FP
pulse occurs AND OOF goes LOW (whichever occurs
last). Figure 4 shows a typical OOF timing pattern when
the TZA3005 is connected to a down stream section
terminating device. OOF remains HIGH for one full frame
after the first FP pulse. The frame and byte boundary
detection block is active until OOF goes LOW.
Parallel output clock (RXPCLK)
This 19.44, 38.88, 77.76 or 155.52 MHz nominally 50%
duty factor byte rate output clock (CMOS) is aligned to
RXPD0 to RXPD7 byte serial output data.
RXPD0 to RXPD7 and FP are updated on the falling edge
of RXPCLK.
Other operating modes
Figure 5 shows frame and byte boundary detection
activated on the rising edge of OOF, and deactivated by
the first FP pulse after OOF goes LOW.
DIAGNOSTIC LOOPBACK
A transmitter-to-receiver loopback mode is available for
diagnostic purposes. When DLEN is LOW, the differential
serial data output from the transmitter is routed to the
serial-to-parallel block in place of the normal data stream
(RXSD), at the serial data rate.
LINE LOOPBACK
The line loopback circuitry consists of alternate clock and
data output drivers. For the TZA3005, it selects the source
of the data and clock signals output on TXSD and
TXSCLK. When LLEN is HIGH, it selects data and clock
signals from the parallel-to-serial converter block. When
LLEN is LOW, it forces the output data multiplexer to select
data and clock signals from the RXSD and RXSCLK
1997 Aug 05
11
Philips Semiconductors
Objective specification
SDH/SONET STM1/OC3 and
STM4/OC12 transceiver
TZA3005
RXSCLK
OOF
RXSD
A1
A1
A1
A2
A2
A2
(1)
RXPD0 to
RXPD7
A2 (28H)
valid
data
invalid data
RXPCLK
FP
MGK485
(1) The input-to-output delay will be between 1.5 and 2.5 cycles of RXPCLK.
Fig.3 Frame and byte detection.
boundary detection enabled
boundary detection enabled
handbook, halfpage
OOF
handbook, halfpage
OOF
FP
FP
MGK486
MGK487
Fig.4 OOF operating time with PM5312 STTX or
PM5355 SUNI-622.
Fig.5 Alternate OOF timing.
1997 Aug 05
12
Philips Semiconductors
Objective specification
SDH/SONET STM1/OC3 and
STM4/OC12 transceiver
TZA3005
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
VCC
PARAMETER
MIN.
−0.5
MAX.
+6.5
UNIT
supply voltage
V
Vn
voltage on
any TTL input pin
any PECL input pin
CMOS output sink current
output source current
CMOS
−0.5
0
+5.5
VCC
8
V
V
Io(sink)
−
mA
Io(source)
−
8
mA
mA
W
high speed PECL
total power dissipation
−
50
Ptot
Tcase
Tj
−
1.3
case temperature under bias
junction temperature under bias
storage temperature
−55
−55
−65
+100
+125
+150
°C
°C
°C
Tstg
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
VALUE
55
UNIT
Rth(j-a)
thermal resistance from junction to ambient; note 1
K/W
Note
1. Measured using a standard test board. This value will vary (and could be as low as 33 K/W) depending on the number
of board layers, copper area, copper sheet thickness and the proximity of surrounding components.
1997 Aug 05
13
Philips Semiconductors
Objective specification
SDH/SONET STM1/OC3 and
STM4/OC12 transceiver
TZA3005
DC CHARACTERISTICS
SYMBOL
General
PARAMETER
CONDITION
MIN.
TYP.
MAX.
UNIT
VCC
Ptot
supply voltage
note 1
outputs open; VCC = 5 V
3.0
−
5.5
1.2
V
total power dissipation
−
0.9
W
TTL Inputs
VIH
VIL
IIH
HIGH-level input voltage
LOW-level input voltage
HIGH-level input current
I
IH ≤ 1 mA at VIH = 5.5 V
2.0
0
−
−
−
−
−
5.5
0.8
V
−
V
VI = 2.4 V
−10
−10
−10
+10
+10
+10
µA
µA
µA
VCC = 5.5 V; VI = 5.5 V
VI = 0.5 V
IIL
LOW-level input current
CMOS Outputs
VOH
VOL
HIGH-level output voltage
VCC = 3.0 V; IOH = −1 mA 2.7
3.0
−
V
LOW-level output voltage
output short-circuit current
VCC = 3.0 V; IOH = 4 mA
VCC = 5.5 V; VO = 0.5 V
−
−
0.1
+0.5
−200
V
IO(sc)
−500
mA
PECL I/O
VIH
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
note 2
note 2
V
V
V
CC − 1.17
CC − 1.81
CC − 1.1
−
−
V
CC − 0.88
CC − 1.48
V
V
V
VIL
V
VOH
terminated with
50 Ω to VCC − 2.0 V
V
V
−
CC − 1.0 VCC − 0.9
CC − 1.7 VCC − 1.6
1300
VOL
LOW-level output voltage
terminated with
50 Ω to VCC − 2.0 V
VCC − 1.8
V
∆Vi(dif)
differential input voltage
swing for differential PECL
inputs
note 2
100
600
mV
∆Vo
serial output voltage swing
terminated with
−
1600
mV
50 Ω to VCC − 2.0 V
Note
1. A single 5 V supply can be used for all VCC pins. Alternatively, a 3.3 V supply can be used for VCC(RXOUT) and 5 V
for the other supply pins. This reduces dissipation. Each supply line (VCC(TXCORE), VCCD(SYN), VCCA(SYN), VCC(TXOUT)
VCC(RXCORE), VCC(RXOUT) and VCC(RXD)) must be connected to VCC via an EMI line filter.
,
2. The PECL inputs are high impedance. The transmission lines should be terminated externally using an appropriate
termination.
1997 Aug 05
14
Philips Semiconductors
Objective specification
SDH/SONET STM1/OC3 and
STM4/OC12 transceiver
TZA3005
AC CHARACTERISTICS
SYMBOL
General
PARAMETER
CONDITION
MIN.
TYP.
MAX.
UNIT
fc(VCO)
Jo
nominal VCO centre frequency
data output jitter
−
−
622.08
−
MHz
peak-to-peak value, in lock;
note 1
−
0.06
UI
REFCLK(tol) reference clock frequency
tolerance
required to meet SONET
output frequency
specification; note 1
−20
−
−
+20
ppm
δ
reference clock input duty factor
rise/fall time
30
70
%UI
tr, tf
reference clock
10 to 90%
−
−
−
2.0
ns
ps
PECL output
20% to 80%; 50 Ω load to
220
450
VCC − 2.0 V; 5 pF capacitor
Receiver timing (see Figs. 6 and 7)
δ
RXPCLK duty factor
data output valid time; RXPCLK valid propagation delay at
40
50
60
%
tDOV
−23.7
−
+21.7
ns
LOW to RXPDn
STM1/OC3, 8-bit
valid propagation delay at
STM1/OC3, 4-bit
−10.9
−4.5
tbf
−
−
−
+8.9
+2.5
tbf
ns
ns
ns
valid propagation delay at
STM4/OC12, 8-bit
valid propagation delay at
STM4/OC12, 4-bit
tsu
set-up time
RXPDn, FP to RXPCLK
4
−
−
−
−
ns
ps
RXSD/RXSDQ to
400
RXSCLK/RXSCLKQ
th
hold time
RXPDn, FP to RXPCLK
2
−
−
−
−
ns
ps
RXSD/RXSDQ to
400
RXSCLK/RXSCLKQ
1997 Aug 05
15
Philips Semiconductors
Objective specification
SDH/SONET STM1/OC3 and
STM4/OC12 transceiver
TZA3005
SYMBOL
PARAMETER
CONDITION
MIN.
TYP.
MAX.
UNIT
Transmitter timing (see Figs. 8 and 9)
fclk
TXSCLK clock frequency
−
622.08 640
MHz
(nominal 155.52 or 622.08 MHz)
δ
duty factor
TXSCLK
40
33
50
50
60
67
%
%
TXPCLK
tsu
set-up time
TXPDn to TXPCLK
TXSD to TXSCLK
hold time
1.5
−
−
−
−
ns
ps
400
th
TXPDn to TXPCLK
TXSD to TXSCLK
data input valid time
1.0
400
−
−
−
−
−
ns
ps
ps
−
tDOV
valid propagation delay
TXSCLK LOW to TXSD
440
Note
1. Jitter on REFCLK and REFCLKQ should be less than 84 ps (peak-to-peak) for STM4/OC12 operation or 336 ps
(peak-to-peak) for STM1/OC3 operation, in a jitter frequency band from 12 kHz to 1 MHz.
1997 Aug 05
16
Philips Semiconductors
Objective specification
SDH/SONET STM1/OC3 and
STM4/OC12 transceiver
TZA3005
handbook, halfpage
RXPCLK
handbook, halfpage
RXPCLK
t
t
t
h
t
t
DOV
su
su
h
RXPD0 to
RXPD7, FP
RXSD/RXSDQ
MGK488
MGK489
Output propagation delay time of TTL outputs is the time in
nanoseconds from the 50% point of the reference signal to the
30% or 70% point of the output.
Maximum output propagation delays and duty cycles of TTL outputs
are measured with a 15 pF load.
Timing is measured from the cross-over point of the reference signal
to the cross-over point of the input.
Fig.6 Receiver output timing.
Fig.7 Receiver input timing.
handbook, halfpage
TXPCLK
handbook, halfpage
TXSCLK
t
t
h
t
t
su
t
su
DOV
h
TXPD0 to
TXPD7
TXSD
MGK490
MGK491
When a set-up time is specified on TTL signals between an input and
a clock, the set-up time in picoseconds from the 50% point of the
input to the 50% point of the clock.
When a hold time is specified on TTL signals between an input and
a clock, the hold time is the time in picoseconds from the 50% point
of the clock to the 50% point of the input.
Timing is measured from the cross-over point of the reference
signal to the cross-over point of the output.
Fig.8 Transmitter input timing.
Fig.9 Transmitter output timing.
1997 Aug 05
17
Philips Semiconductors
Objective specification
SDH/SONET STM1/OC3 and
STM4/OC12 transceiver
TZA3005
The connections required to implement the design are
shown in Fig.10, and the timing specifications are shown
in Fig.11. The specified set-up and hold times must be met
by the controller ASIC. It is recommended to latch the data
on the falling edge of the reference clock in order to satisfy
the appropriate specifications.
APPLICATION INFORMATION
It is sometimes necessary to ‘forward clock’ data in an
SDH/SONET system. When this is the case, the parallel
data clock and the reference clock from which the high
speed serial clock is synthesized will both originate from
the same (usually TTL/CMOS) clock source. The following
sections explain how to configure the TZA3005 to
operated in this mode.
PECL output termination
The PECL outputs have to be terminated with
50 Ω to VCC − 2.0V. If this voltage is not available, a
Thevenin termination can be used as shown in Fig.11.
Clock control logic description
The timing control logic in the TZA3005 automatically
generates an internal load signal with a fixed relationship
to the reference clock. The logic takes into account the
variation between the reference clock and the internal load
signal over temperature and voltage.
Reference clock
Reference clock jitter must be minimized to ensure
SONET jitter generation specifications are met. It may
prove difficult to meet these specifications if a TTL source
is used for the reference clock.
propagation delay <3.5 ns
handbook, halfpage
PECL
TTL/PECL
CONVERTER
2
REFCLK
TXPCLK
serial
data
ASIC
TZA3005
8
data
TXPD0 to TXPD7
MGK492
Fig.10 TZA3005 with data clocked by reference clock.
TXPCLK
TXPD0 to
TXPD7
MGK493
t
su
t
h
Fig.11 Data timing with respect to reference clock.
18
1997 Aug 05
Philips Semiconductors
Objective specification
SDH/SONET STM1/OC3 and
STM4/OC12 transceiver
TZA3005
VCC = 5.0 V
handbook, halfpage
R1
R2
83.3 Ω
83.3 Ω
IN
INQ
R3
125 Ω
R4
125 Ω
GND
MGK654
Fig.12 PECL output termination schemes.
1997 Aug 05
19
Philips Semiconductors
Objective specification
SDH/SONET STM1/OC3 and
STM4/OC12 transceiver
TZA3005
GM9K4
k
1997 Aug 05
20
Philips Semiconductors
Objective specification
SDH/SONET STM1/OC3 and
STM4/OC12 transceiver
TZA3005
PACKAGE OUTLINE
QFP64: plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 x 14 x 2.7 mm
SOT393-1
y
X
A
48
33
32
49
Z
E
e
A
2
H
A
E
(A )
3
E
A
1
θ
w M
p
L
p
b
pin 1 index
L
17
64
detail X
16
1
w M
b
p
v
M
A
Z
e
D
D
B
H
D
v
M
B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
D
H
L
L
v
w
y
Z
Z
E
θ
1
2
3
p
E
p
D
max.
7o
0o
0.25 2.75
0.10 2.55
0.45 0.23 14.1 14.1
0.30 0.13 13.9 13.9
17.45 17.45
16.95 16.95
1.03
0.73
1.2
0.8
1.2
0.8
mm
3.00
0.25
0.8
1.60
0.16 0.16 0.10
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
EIAJ
96-05-21
97-08-04
SOT393-1
MS-022
1997 Aug 05
21
Philips Semiconductors
Objective specification
SDH/SONET STM1/OC3 and
STM4/OC12 transceiver
TZA3005
SOLDERING
Introduction
Wave soldering
Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
If wave soldering cannot be avoided, the following
conditions must be observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
Reflow soldering
Even with these conditions, do not consider wave
soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
Reflow soldering techniques are suitable for all QFP
packages.
QFP100 (SOT382-1) or QFP160 (SOT322-1).
The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality
Reference Handbook” (order code 9397 750 00192).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Repairing soldered joints
Fix the component by first soldering two diagonally-
opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
1997 Aug 05
22
Philips Semiconductors
Objective specification
SDH/SONET STM1/OC3 and
STM4/OC12 transceiver
TZA3005
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1997 Aug 05
23
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Internet: http://www.semiconductors.philips.com
Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1997
SCA55
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427027/200/01/pp24
Date of release: 1997 Aug 05
Document order number: 9397 750 01745
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