IS9-2100AEH-Q [RENESAS]
HALF BRDG BASED MOSFET DRIVER;
| 型号： | IS9-2100AEH-Q |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | HALF BRDG BASED MOSFET DRIVER 驱动 接口集成电路 |
| 文件： | 总6页 (文件大小：188K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
Radiation Hardened High Frequency Half Bridge
Drivers
IS-2100ARH, IS-2100AEH
Features
The radiation hardened IS-2100ARH, IS-2100AEH are high
frequency, 130V half bridge N-Channel MOSFET driver ICs,
which are functionally similar to industry standard 2110 types.
The low-side and high-side gate drivers are independently
controlled. This gives the user maximum flexibility in dead
time selection and driver protocol.
• Electrically screened to DLA SMD # 5962-99536
• QML qualified per MIL-PRF-38535 requirements
• Radiation environment
- Maximum total dose . . . . . . . . . . . . . . . . . . . . . 300krad(Si)
- DI RSG process provides latch-up immunity
2
- SEU rating . . . . . . . . . . . . . . . . . . . . . . . . . . 82MeV/mg/cm
In addition, the devices have on-chip error detection and
correction circuitry, which monitors the state of the high-side
latch and compares it to the HIN signal. If they disagree, a set
or reset pulse is generated to correct the high-side latch. This
feature protects the high-side latch from single event upsets
(SEUs).
- Vertical device architecture reduces sensitivity to low dose
rates
• Bootstrap supply maximum voltage to 150V
• Drives 1000pF load at 1MHz with rise and fall times of 30ns
(typical)
Applications
• High frequency switch-mode power supplies
• Drivers for inductive loads
• DC motor drivers
• 1.5A (typical) peak output current
• Independent inputs for non-half bridge topologies
• Low DC power consumption . . . . . . . . . . . . . . 60mW (typical)
• Operates with V = V over 12V to 20V range
DD CC
• Low-side supply undervoltage protection
Pin Configuration
IS-2100ARH, IS-2100AEH
FLATPACK (CDFP4-F16)
TOP VIEW
LO
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
NC
COM
V
SS
V
LIN
SD
CC
NC
NC
VS
VB
HO
HIN
V
DD
NC
NC
May 10, 2016
FN9037.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2002, 2012, 2016. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
IS-2100ARH, IS-2100AEH
Ordering Information
ORDERING SMD NUMBER
PART NUMBER
(Note 1)
TEMP RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
(Note 2)
5962F9953602V9A
5962F9953602VXC
5962F9953602QXC
N/A
IS0-2100ARH-Q
IS9-2100ARH-Q
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
Die
16 Ld Flatpack
16 Ld Flatpack
16 Ld Flatpack
16 Ld Flatpack
Die
K16.A
K16.A
K16.A
K16.A
IS9-2100ARH-8
IS9-2100ARH/Proto
IS9-2100AEH-Q
IS0-2100AEH-Q
5962F9953603VXC
5962F9953603V9A
NOTES:
1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations.
2. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed in the
“Ordering Information” table must be used when ordering.
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IS-2100ARH, IS-2100AEH
Die Characteristics
Backside Finish:
DIE DIMENSIONS:
4820µm x 3300µm (190 mils x 130 mils)
Silicon
Thickness: 483µm 25.4µm (19 mils 1 mil)
ASSEMBLY RELATED INFORMATION:
INTERFACE MATERIALS:
Glassivation:
Substrate Potential:
Unbiased (DI)
Type: PSG (Phosphorous Silicon Glass)
Thickness: 8.0kÅ 1.0kÅ
ADDITIONAL INFORMATION:
Worst Case Current Density:
Top Metallization:
5
2
<2.0 x 10 A/cm
Type: ALSiCu
Thickness: 16.0kÅ 2kÅ
Transistor Count:
542
Substrate:
Radiation Hardened Silicon Gate,
Dielectric Isolation
Metallization Mask Layout
IS-2100ARH, IS-2100AEH
SD (13)
HIN (12)
LIN (14)
V
(15)
SS
V
(11)
DD
HO (8)
VB (7)
LO (1)
COM (2)
V
(3)
CC
VS (6)
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IS-2100ARH, IS-2100AEH
TABLE 1. IS-2100ARH, ISL-2100AEH DIE LAYOUT X-Y COORDINATES
PAD CENTER
PAD SIZE
X
Y
DX
DY
PAD NUMBER
PAD NAME
VCC
VS
(µm)
(µm)
(µm)
(µm)
3
6
296.5
4561
4561
4561
4645.5
4627.5
302
270
284.5
711
109
109
109
109
109
109
109
109
109
109
109
280
280
280
280
109
109
109
109
109
280
280
7
VB
8
HO
1079
1500
2817
3064.5
2040
1719
1095
697
11
12
13
14
15
1
VDD
HIN
SD
LIN
237.5
239
VSS
LO
296.5
296.5
2
COM
NOTE: Origin of coordinates is the lower left corner of the die.
3500
3000
2500
2000
1500
1000
500
0
0
1000
2000
3000
4000
5000
FIGURE 1. XY PAD CENTER
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IS-2100ARH, IS-2100AEH
Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please go to the web to make sure that you have the latest revision.
DATE
REVISION
FN9037.3
CHANGE
May 10, 2016
Updated Ordering information table by applying new standards and adding Notes 1 and 2.
Added Table 1 on page 4.
Added Package Outline Drawing K16.A.
About Intersil
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address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
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in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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IS-2100ARH, IS-2100AEH
Package Outline Drawing
K16.A
16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
Rev 2, 1/10
0.015 (0.38)
PIN NO. 1
1
2
0.008 (0.20) ID OPTIONAL
0.050 (1.27 BSC)
PIN NO. 1
ID AREA
0.440 (11.18)
MAX
0.005 (0.13)
MIN
4
0.022 (0.56)
0.015 (0.38)
TOP VIEW
0.115 (2.92)
0.009 (0.23)
0.004 (0.10)
0.045 (1.14)
0.026 (0.66)
0.045 (1.14)
6
0.285 (7.24)
0.245 (6.22)
-D-
-H-
-C-
0.370 (9.40)
0.250 (6.35)
0.13 (3.30)
MIN
0.03 (0.76) MIN
SEATING AND
BASE PLANE
LEAD FINISH
SIDE VIEW
NOTES:
Index area: A notch or a pin one identification mark shall be located
adjacent to pin one and shall be located within the shaded area shown.
The manufacturer’s identification shall not be used as a pin one
identification mark. Alternately, a tab may be used to identify pin one.
1.
0.006 (0.15)
0.004 (0.10)
LEAD FINISH
2. If a pin one identification mark is used in addition to a tab, the limits
of the tab dimension do not apply.
0.009 (0.23)
0.004 (0.10)
BASE
METAL
3. The maximum limits of lead dimensions (section A-A) shall be
measured at the centroid of the finished lead surfaces, when solder
dip or tin plate lead finish is applied.
0.019 (0.48)
0.015 (0.38)
4. Measure dimension at all four corners.
0.0015 (0.04)
MAX
5. For bottom-brazed lead packages, no organic or polymeric materials
shall be molded to the bottom of the package to cover the leads.
0.022 (0.56)
0.015 (0.38)
6. Dimension shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension minimum shall
be reduced by 0.0015 inch (0.038mm) maximum when solder dip
lead finish is applied.
3
SECTION A-A
7. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
8. Controlling dimension: INCH.
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