UPD98414F2-RN1 [RENESAS]
IC,ATM/SONET FRAMER,CMOS,BGA,352PIN,PLASTIC;
| 型号： | UPD98414F2-RN1 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | IC,ATM/SONET FRAMER,CMOS,BGA,352PIN,PLASTIC ATM 异步传输模式 |
| 文件： | 总46页 (文件大小：499K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD98414
2.4 Gbps ATM SONET FRAMER
The µPD98414 (NEASCOT-P70) is one of ATM LSIs and provides the functions of the TC sublayer of the
SONET/SDH-base physical layer of the ATM protocol specified by the ATM Forum.
Its main functions include a transmission function for mapping an ATM cell passed from a high-end ATM layer
device to the payload of a 2.4 Gbps SONET STS-48c/SDH STM-16c frame and transmitting the cell to a MUX device
in the circuit, and a reception function for separating the overhead and ATM cell from the data string received from a
DEMUX device and transmitting the ATM cell to the ATM layer device.
This LSI is ideal for systems that constitute the ATM network of a LAN or WAN, such as a transmission system,
ATM switch, and high-speed backbone switch.
Detailed descriptions of its functions, etc., are given in the following user's manual. Be sure to read it for
design purposes.
µPD98414 User's Manual: S14166E
FEATURES
• Supplies the functions of the TC (Transmission Convergence) sublayer recommended by the ATM Forum and
ITU-T.
• Supports the concatenation frame of 2.4 Gbps SONET STS-48c/SDH STM-16c.
• ATM layer interface
• 32-bit, 104-MHz LVTTL FIFO interface
• 15-cell transmit/receive FIFO
• Supports 52-byte/56-byte cell formats.
• Prefixes one-word TAG area to receive cell.
• Circuit side interface
• 16-bit PECL level I/O
• Either of two modes can be selected for CPU interface
• 16-bit data bus
• Intel-compatible mode [RD, WR, RDY-type]/Motorola-compatible mode [DS, R/W, ACK-type]
• Supports two types of overhead interfaces (that can access all overhead areas).
• Incorporates overhead byte insert/drop registers.
• Incorporates dedicated overhead byte insert/extract interfaces.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S14242EJ2V0DS00 (2nd edition)
Date Published July 2001 NS CP(K)
Printed in Japan
The mark shows major revised points.
©
1999, 2001
µPD98414
• Many OAM functions
• Fault: Detection of LOS, OOF, LOF, LOP, OCD, and LCD
• Alarm: Detection and transmission of APS, Line AIS, Line RDI, Path AIS, and Path RDI
• Receive APS signal and Signal Label (C2 byte) monitoring functions
• Bit error rate monitoring function
• Transmit/receive message buffer for J0/J1 trace messages (16 bytes or 64 bytes long)
• Supports loopback function.
Remote: Two modes (ATM layer loopback and circuit side loopback)
• Supports an error generation pseudo frame transmission function for testing.
• Three general-purpose input and five general-purpose output ports
• Supports JTAG boundary scan test (IEEE1149.1).
• 0.35-µm CMOS process
• +3.3 V single power source
ORDERING INFORMATION
Part Number
Package
µPD98414F2-RN1
352-pin plastic BGA (cavity down advanced type) (35 × 35)
Data Sheet S14242EJ2V0DS
2
Clock
generator
Clock
generator
16-bit
× 156M bps
MUX
(AMCC
S3043, etc.)
E/O
O/E
32
32
PD98414
NEASCOT-P70
µ
ATM cell
interface
Switch
DEMUX
(AMCC
S3044, etc.)
16-bit
× 156M bps
Microprocessor
interface
Overhead
interface
CPU
µ
µ
µPD98414
BLOCK DIAGRAM
ATM Layer Device
Rx ATM Layer Interface
Tx ATM Layer Interface
MADD[8]
MD[16]
BMODE
DS_B/RD_B
ACK2S_B/
RDY2S_B
ACK3S_B/
RDY3S_B
RW/WR_B
CS_B
POUT0
POUT1
POUT2
POUT3
POUT4
PIN0
PIN1
PIN2
PHINT_B
RESET_B
LOSS
OOFS
LOFS
LOPS
LCDS
LAISS
PAISS
LRDIS
PRDIS
B1ERS
B2ERS
TLAIS
TPAIS
TLRDI
TPRDI
RSOHCK (25M)
RSOHFP
TSOHCK (25M)
TSOHFP
TSOHD[4]
TSOHAV
RSOHD[4]
RSOHAV
RPOHCK (576K)
RPOHFP
TPOHCK (576K)
TPOHFP
TPOHD
RPOHD
RPOHAV
TPOHAV
32
32
TCS (77M)
RCS (19M)
JCK
JDI
JMS
JRST_B
JDO
Line Interface
MUX/DEMUX Chip
Data Sheet S14242EJ2V0DS
4
µPD98414
PIN CONFIGURATION
RXCLK
RCLK_N
RCLK_P
RXCLK_O
RXCLAV
TCLK_N
TCLK_P
RXSOC
RXPRTY
RXDATA[31:0]
RXENB_B
RXSEL_B
32
TPCLK_N
ATM Layer Interface
TPCLK_P
TXPLD[15:0]
RXPLD[15:0]
16
16
Line Interface
TXCLK
RCS
TCS
TXCLK_O
TXCLAV
32
CD
TXDATA[31:0]
TXENB_B
3
VREF[3:1]
TXSOC
TSOHCK
TSOHFP
TXPRTY
TXSEL_B
4
TSOHD[3:0]
TSOHAV
8
MADD[7:0]
MD[15:0]
CS_B
16
TPOHCK
TPOHFP
TPOHD
µPD98414
NEASCOT-P70
RW/WR_B
TPOHAV
Management Interface
DS_B/RD_B
Overhead Insert/
Extract Interface
ACK2S_B/RDY2S_B
ACK3S_B/RDY3S_B
RESET_B
RSOHCK
RSOHFP
4
RSOHD[3:0]
RSOHAV
PHINT_B
BMODE
RPOHCK
RPOHFP
LOSS
OOFS
LOFS
LOPS
LCDS
LAISS
PAISS
LRDIS
RPOHD
RPOHAV
5
POUT[4:0]
PIN[2:0]
3
General I/O Ports
JTAG Interface
Alarm Signals Pins
JCK
JMS
PRDIS
B1ERS
B2ERS
JDI
JRST_B
JDO
TLAIS
TPAIS
VDD
Power and Ground
GND
Alarm Instruction Pins
TLRDI
TPRDI
8
IC
Others (Leave open)
Data Sheet S14242EJ2V0DS
5
µPD98414
PIN CONFIGURATION (BOTTOM VIEW)
• 352-pin plastic BGA (cavity down advanced type) (35 × 35)
µPD98414F2-RN1
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
51
50
60
70
76
80
160
150
170
240
250
320
330
260
230
140
310
340
180
40
90
270
220
130
300
8
350
352
7
6
190
30
26
5
280
290
4
210
200
3
120
110
100
2
20
10
3
2
1
1
AF AE AD AC AB AA
Y W V U T R P N M L K J H G F E D C B A
Index mark
Data Sheet S14242EJ2V0DS
6
µPD98414
PIN ARRANGEMENT TABLE
(1/4)
Serial No. Address No.
Pin Name
Serial No. Address No.
Pin Name
RXDATA15
RXDATA17
GND
Serial No. Address No.
Pin Name
1
A01
B01
GND
TCS
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
AE26
AD26
AC26
AB26
AA26
Y26
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
F26
E26
D26
C26
B26
A26
A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A09
A08
A07
A06
A05
A04
A03
A02
B02
C02
D02
E02
F02
TXCLAV
GND
2
3
C01
IC
POUT0
PHINT_B
GND
4
D01
IC
RXDATA19
GND
5
E01
RXPLD15
RXPLD13
GND
6
F01
RXDATA24
GND
GND
7
G01
RW/WR_B
MADD6
MADD4
MADD1
MD13
MD10
MD7
8
H01
RXPLD10
RXPLD8
VDD
RXDATA28
RXDATA30
RXPRTY
RXCLAV
GND
9
J01
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
K01
L01
GND
M01
N01
RXPLD4
VDD
POUT1
PRDIS
P01
GND
MD3
R01
GND
VDD
MD0
T01
VDD
GND
GND
U01
RCLK_P
RPOHFP
RSOHD2
RSOHAV
TPOHAV
TSOHD2
TSOHD0
POUT4
GND
LAISS
TXPLD13
GND
V01
OOFS
W01
Y01
GND
GND
TXDATA1
VDD
VDD
AA01
AB01
AC01
AD01
AE01
AF01
AF02
AF03
AF04
AF05
AF06
AF07
AF08
AF09
AF10
VDD
GND
GND
W26
V26
VDD
VDD
TXDATA10
TXDATA12
TXDATA15
TXDATA17
GND
TXPLD3
VDD
U26
GND
T26
GND
PIN1
R26
TPCLK_P
IC
TLRDI
POUT2
RXDATA1
VDD
P26
N26
TXDATA19
GND
JDI
M26
VDD
L26
TXDATA24
GND
VDD
GND
K26
RCS
VDD
J26
TXDATA28
TXDATA30
TXPRTY
IC
RXDATA10
RXDATA12
H26
VDD
G26
GND
Data Sheet S14242EJ2V0DS
7
µPD98414
(2/4)
Serial No. Address No.
Pin Name
RXPLD12
RXPLD11
RXPLD9
VREF2
Serial No. Address No.
Pin Name
RXDATA31
RXENB_B
VDD
Serial No. Address No.
Pin Name
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
G02
H02
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AD25
AC25
AB25
AA25
Y25
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
B09
B08
B07
B06
B05
B04
B03
C03
D03
E03
F03
G03
H03
J03
MD9
MD5
J02
MD1
K02
RXCLK_O
B2ERS
GND
L02
GND
VDD
M02
VDD
PAISS
TXPLD12
TXPLD11
TXPLD9
TXPLD7
GND
N02
RXPLD3
RXPLD2
RXPLD0
RCLK_N
RPOHD
RSOHD3
RSOHD1
RSOHFP
TPOHFP
TSOHD1
TSOHFP
PIN2
VDD
P02
LOSS
R02
LCDS
T02
VDD
U02
TXDATA3
TXDATA5
TXDATA6
TXDATA9
VDD
VDD
V02
GND
W02
Y02
W25
V25
TXPLD1
TCLK_N
TPCLK_N
JCK
AA02
AB02
AC02
AD02
AE02
AE03
AE04
AE05
AE06
AE07
AE08
AE09
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
U25
T25
GND
R25
P25
TXDATA16
TXDATA18
VDD
JRST_B
VDD
VDD
N25
M25
L25
IC
PIN0
TXDATA22
TXDATA25
TXDATA27
GND
VREF3
GND
TPAIS
VDD
K25
VDD
RXDATA3
RXDATA5
RXDATA6
RXDATA9
VDD
J25
VDD
H25
G25
F25
TXDATA31
TXENB_B
VDD
VDD
K03
L03
M03
N03
P03
R03
T03
U03
V03
W03
Y03
GND
RXPLD7
RXPLD5
VDD
E25
TXCLK_O
RESET_B
DS_B/RD_B
VDD
GND
D25
C25
B25
RXDATA16
RXDATA18
VDD
RXPLD1
GND
B24
ACK3S_B/RDY3S
_B
GND
RXDATA22
RXDATA25
RXDATA27
GND
B23
MADD5
MADD2
MD14
RPOHAV
VDD
B22
B21
RSOHD0
TPOHD
B20
MD11
Data Sheet S14242EJ2V0DS
8
µPD98414
(3/4)
Serial No. Address No.
Pin Name
TSOHD3
TSOHAV
POUT3
VDD
Serial No. Address No.
Pin Name
TXDATA21
TXDATA23
TXDATA26
VDD
Serial No. Address No.
Pin Name
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
AA03
AB03
AC03
AD03
AD04
AD05
AD06
AD07
AD08
AD09
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AC24
AB24
AA24
Y24
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
N24
M24
L24
K24
J24
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
H04
J04
GND
GND
K04
VDD
L04
GND
CD
VDD
M04
RXPLD6
GND
RXDATA0
GND
H24
G24
F24
E24
D24
C24
C23
C22
C21
C20
C19
C18
C17
C16
C15
C14
C13
C12
C11
C10
C09
C08
C07
C06
C05
C04
D04
E04
F04
G04
VDD
N04
TXSEL_B
TXCLK
IC
P04
VDD
RXDATA4
VDD
R04
VREF1
VDD
T04
RXDATA8
RXDATA11
RXDATA13
VDD
CS_B
U04
RPOHCK
GND
VDD
V04
ACK2S_B/RDY2S
_B
W04
Y04
RSOHCK
TPOHCK
GND
MADD3
MADD0
MD12
VDD
VDD
AA04
AB04
AC04
AC05
AC06
AC07
AC08
AC09
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
RXDATA21
RXDATA23
RXDATA26
VDD
TSOHCK
GND
MD6
TPRDI
VDD
MD2
VDD
VDD
RXDATA2
GND
VDD
TXPLD14
VDD
RXSEL_B
RXCLK
TLAIS
RXDATA7
GND
TXPLD10
GND
GND
LRDIS
TXPLD6
TXPLD5
VDD
RXDATA14
GND
VDD
LOPS
RXDATA20
VDD
TXDATA0
GND
TXPLD2
TXPLD0
VDD
VDD
TXDATA4
VDD
RXDATA29
GND
W24
IC
V24
TXDATA8
TXDATA11
TXDATA13
VDD
JMS
GND
U24
GND
RXSOC
GND
T24
IC
R24
VDD
B1ERS
GND
P24
VDD
RXPLD14
Data Sheet S14242EJ2V0DS
9
µPD98414
(4/4)
Serial No. Address No.
Pin Name
LOFS
Serial No. Address No.
Pin Name
TXSOC
GND
Serial No. Address No.
Pin Name
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
AB23
AA23
Y23
W23
V23
U23
T23
R23
P23
N23
M23
L23
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
G23
F23
E23
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
346
347
348
349
350
351
352
D11
D10
D09
D08
D07
D06
D05
VDD
TXPLD4
GND
VDD
TXDATA2
GND
BMODE
GND
GND
TXDATA7
GND
MADD7
VDD
TCLK_P
GND
GND
MD15
GND
JDO
TXDATA14
GND
MD8
TXDATA20
VDD
MD4
GND
VDD
TXPLD15
GND
K23
J23
TXDATA29
GND
VDD
H23
GND
TXPLD8
Data Sheet S14242EJ2V0DS
10
µPD98414
PIN NAME
ACK2S_B
ACK3S_B
B1ERS
B2ERS
BMODE
CD
Acknowledge 2 State
Acknowledge 3 State
B1 Error Rate Degrade
B2 Error Rate Degrade
Bus Mode
RSOHFP
RW
Rx SOH Insert Frame Pulse
Management Data Read/Write
Rx Cell Available
RXCLAV
RXCLK
UTOPIA Rx Clock In
UTOPIA Rx Clock Out
UTOPIA Rx Data
RXCLK_O
RXDATA0-
RXDATA31
RXENB_B
Carrier Detect
CS_B
Chip Select
DS_B
Data Strobe
Rx Cell Enable
GND
Ground
RXPLD0-RXPLD15 Rx Line Data
IC
Internal Circuits Connection
JTAG Test Clock
JTAG Test Data In
JTAG Test Data Out
JTAG Test Mode Select
JTAG Test Reset
Line AIS State
RXPRTY
RXSEL_B
RXSOC
TCLK_N
TCLK_P
TCS
Rx Parity
JCK
Rx Cell Select
JDI
Rx Start Of Cell
Tx Clock In − (155 MHz)
Tx Clock In + (155 MHz)
Tx Line Clock Signal Out (77 MHz)
Tx Line AIS Frame Send
Tx Line RDI Frame Send
Tx Path AIS Frame Send
Tx Clock Out − (155 MHz)
Tx Clock Out + (155 MHz)
Tx POH Insert Available
Tx POH Insert Clock
Tx POH Insert Data
JDO
JMS
JRST_B
LAISS
TLAIS
LCDS
LCD State
TLRDI
LOFS
LOF State
TPAIS
LOPS
LOP State
TPCLK_N
TPCLK_P
TPOHAV
TPOHCK
TPOHD
LOSS
LOS State
LRDIS
Line RDI State
MADD0-MADD7
MD0-MD15
OOFS
Management Address
Management Data
OOF State
TPOHFP
TPRDI
Tx POH Insert Frame Pulse
Tx Path RDI Frame Send
Tx TOH Insert Available
Tx TOH Insert Clock
Tx TOH Insert Data
PAISS
Path AIS State
PHINT_B
PIN0-PIN2
POUT0-POUT4
PRDIS
Interrupt
TSOHAV
TSOHCK
TSOHD0-TSOHD3
TSOHFP
TXCLAV
TXCLK
General In
General Out
Path RDI State
Rx Line Clock − (155 MHz)
Rx Line Clock + (155 MHz)
Tx TOH Insert Frame Pulse
Tx Cell Available
RCLK_N
RCLK_P
RCS
UTOPIA Tx Clock In
UTOPIA Tx Clock Out
UTOPIA Tx Data
Rx Line Clock Signal Out (19 MHz) TXCLK_O
RD_B
Read
TXDATA0-
TXDATA31
TXENB_B
TXPLD0-TXPLD15
TXPRTY
RDY2S_B
RDY3S_B
RESET_B
RPOHAV
RPOHCK
RPOHD
RPOHFP
RSOHAV
RSOHCK
Ready 2-State
Ready 3-State
Tx Cell Enable
Tx Line Data
Tx Parity
Reset
Rx POH Insert Available
Rx POH Insert Clock
Rx POH Insert Data
Rx POH Insert Frame Pulse
Rx SOH Insert Available
Rx SOH Insert Clock
TXSEL_B
TXSOC
Tx Cell Select
Tx Start Of Cell
VDD
VDD
VREF1-VREF3
WR_B
Voltage Reference For PECL In
Write
RSOHD0-RSOHD3 Rx SOH Insert Data
Data Sheet S14242EJ2V0DS
11
µPD98414
CONTENTS
1. PIN FUNCTION..........................................................................................................................................13
1.1 Line Interface..................................................................................................................................13
1.2 ATM Layer Interface.......................................................................................................................14
1.3 Management Interface ...................................................................................................................17
1.4 Overhead Interface.........................................................................................................................18
1.5 General-Purpose I/O Port ..............................................................................................................20
1.6 Alarm Signal Input/Output.............................................................................................................20
1.7 JTAG Boundary Scan ....................................................................................................................21
1.8 Power and Grounding Pins...........................................................................................................22
1.9 Others..............................................................................................................................................22
1.10 Handling Unused Pins...................................................................................................................23
1.11 Initial States of Each Pin ...............................................................................................................24
2. CONNECTION EXAMPLE OF MUX/DEMUX DEVICE..............................................................................25
3. ELECTRIC CHARACTERISTICS ..............................................................................................................27
4. PACKAGE DRAWING...............................................................................................................................41
5. RECOMMENDED SOLDERING CONDITIONS ........................................................................................42
Data Sheet S14242EJ2V0DS
12
µPD98414
1. PIN FUNCTION
1.1 Line Interface
The line interface connects MUX and DEMUX devices in the circuit.
Pin Name
RCLK_N
Serial No.
115
Address No.
T02
I/O, Level
Function
I
Receive clock input (155.52 MHz).
PECL
These pins input a 155.52-MHz clock, synchronized with the
receive data.
RCLK_P
TCLK_N
17
U01
B06
189
I
Transmit clock input (155.52 MHz).
These pins input a transmit clock. The µPD98411 updates
transmit data TXPLD15 through TXPLD0 at the rising edge
of this clock.
PECL
TCLK_P
350
D07
TPCLK_N
TPCLK_P
190
97
B05
A05
O
Transmit clock output (155.52 MHz).
PECL
The clocks input to TCLK_N and TCLK_P are internally
inverted and output from these pins.
RXPLD15-
RXPLD0
5, 280, 6,
E01, G04, F01,
G02, H02, H01,
J02, J01, L03,
M04, M03, M01,
N02, P02, P03,
R02
I
Receive 16-bit parallel data input.
106, 107, 8,
108, 9, 201,
285, 202, 12,
112, 113, 204,
114
PECL
TXPLD15-
TXPLD0
342, 265, 87,
181, 182, 267,
183, 345, 184,
269, 270, 347,
94, 272, 188,
273
D15, C15, A15,
B14, B13, C13,
B12, D12, B11,
C11, C10, D10,
A08, C08, B07,
C07
O
Transmit 16-bit parallel data output.
PECL
TCS
RCS
CD
2
B01
O
Transmit system clock output (77.76 MHz).
LVTTL
The transmit clocks input to TCLK_N and TCLK_P are
divided by two in the µPD98414 and output from this pin.
102
215
C02
O
Receive system clock output (19.44 MHz).
LVTTL
The receive clocks input to RCLK_N and RCLK_P are
divided by eight in the µPD98414 and output from this pin.
AD04
I
Receive framer function reset.
LVTTL
While the input level of this pin is low, the receive framer
(5V tolerant) block (from the circuit up to the receive FIFO) is reset. The
transition of this signal from high to low can be used as a
condition for LOS detection. The optical input failure alarm
signal output by a receive optical link module can be input to
this pin.
VREF3-
VREF1
195, 109, 288
E03, K02, R04
I
These pins input reference potentials (intermediate
VREF
potentials) for single-end PECL input signals (RXPLD[15:0]).
Data Sheet S14242EJ2V0DS
13
µPD98414
1.2 ATM Layer Interface
The ATM layer interface transfers cells to and from a high-end ATM layer device.
(1/3)
Pin Name
RXCLK
Serial No.
232
Address No.
AD21
I/O, Level
Function
I
Receive FIFO clock input.
LVTTL
This pin inputs the clock, from 8 to 104 MHz, used to
transfer receive data.
RXCLK_O
RXSOC
144
312
AE22
AC20
O
Receive FIFO clock return output.
LVTTL
This pin returns and outputs the clock input to RXCLK.
O
Receive cell start position signal output.
LVTTL
This pin goes high during the clock cycle in which the first
byte of the receive cell is output to RXDATA, to post
notification to the ATM layer device.
RXCLAV
46
AF21
O
Receive FIFO cell data transfer enable signal output.
The µPD98414 drives RXCLAV high if one or more cells of
receive data to be transferred exists in the receive FIFO, to
post notification to the ATM layer device. RXCLAV is held
high if one or more cells of valid data exists in the receive
FIFO at the seventh clock cycle or later after the start of
output of the cell; otherwise, RXCLAV goes low.
LVTTL
RXENB_B
142
AE20
I
Receive enable signal input (byte unit control).
LVTTL
The ATM layer device enables or disables the receive cell
data output by the µPD98414 in byte units. The µPD98414
samples RXENB_B at the rising edge of RXCLK. When it
detects the low level of RXENB_B, it updates the output of
RSOC and RXDATA starting from the next clock cycle, and
then transfers the receive cell data. If RXENB_B is high, the
µPD98414 stops the output of RSOC and RXDATA, starting
from the next clock cycle.
Caution This signal cannot be used with RXSEL_B at
the same time. Fix this signal to the low level
when it is not used.
RXSEL_B
231
AD20
I
Receive enable signal input (cell unit control).
The ATM layer device enables the µPD98414 to output
receive cell data in cell units. The µPD98414 samples
RXSEL_B at the rising edge, one clock cycle before RXSOC
goes high, and starts outputting receive cell data from the
next clock cycle if RXSEL_B is low. Once the µPD98414
has detected that RXSEL_B has gone low, it does not
sample RXSEL_B until the next sampling timing (one clock
before RXSOC goes high). When the µPD98414 detects
that RXSEL_B has gone high at the sampling timing, it
continues sampling RXSEL_B at every clock, and starts
outputting cells from the clock cycle next to that in which the
low level of RXSEL_B was detected.
LVTTL
Caution This signal cannot be used with RXENB_B at
the same time. Fix this signal to the low level
when it is not used.
Data Sheet S14242EJ2V0DS
14
µPD98414
(2/3)
Pin Name
RXPRTY
Serial No.
Address No.
AF20
I/O, Level
Function
45
O
Parity bit output.
LVTTL
This pin generates an odd parity bit for the output data on
RXDATA and outputs it from RXPRTY. The parity bit is
always output.
The parity bit to be generated can be changed to even parity
depending on the setting of the RRPM bit of the MDR5
register.
RXDATA31- 141, 44, 309,
AE19, AF19, AC17,
AF18, AE17, AD16,
AE16, AF16, AD15,
AE15, AD14, AC14,
AF14, AE13, AF12,
AE12, AF11, AC12,
AD11, AF10, AD10,
AF09, AE09, AD09,
AC09, AE08, AE07,
AD07, AE06, AC07,
AF05, AD05
O
Receive cell data output bus.
RXDATA0
43, 139, 227,
138, 41, 226,
137, 225, 306,
39, 135, 37,
134, 36, 304,
222, 35, 221,
34, 131, 220,
301, 130, 129,
218, 128, 299,
30, 216
LVTTL
These pins form a 32-bit data bus through which receive cell
data is output to the ATM layer device. The data on this bus
is updated at the rising edge of RXCLK.
TXCLK
253
F24
I
Transmit FIFO clock input.
LVTTL
This pin inputs the clock, from 8 to 104 MHz, used to
transfer transmit data.
TXCLK_O
TXSOC
167
331
E25
G23
O
Transmit FIFO clock return output.
LVTTL
This pin returns and outputs the clock input to TXCLK.
I
Transmit cell start position signal input.
LVTTL
This pin inputs a signal that indicates the start position of a
transmit cell. The µPD98414 recognizes the clock cycle in
which TXSOC is high as the first word of a cell.
TXCLAV
71
F26
O
Transmit FIFO cell data reception enable signal output.
This signal posts notification of the vacancy of the transmit
FIFO to the ATM layer device. If the number of cells stored
in the transmit FIFO has reached the threshold value set by
the TCAV[1:0] bits of the MDR5 register, the µPD98414
drives TXCLAV low. The threshold value can be selected
from 9, 11, 13, or 15 cells. The default value is 15 cells, at
which point the transmit FIFO is full. The µPD98414 keeps
receiving cells, even if TXCLAV is driven low, until the
transmit FIFO is full (i.e., 15 cells). The 16th and
LVTTL
subsequent cells are dropped and the µPD98414 reports an
overflow of the transmit FIFO.
Data Sheet S14242EJ2V0DS
15
µPD98414
(3/3)
Pin Name
TXENB_B
Serial No.
165
Address No.
G25
I/O, Level
Function
I
Transmit enable signal input (byte unit control).
LVTTL
This signal indicates, in byte units, that the ATM layer
device has output valid transmit cell data to TXDATA. The
µPD98414 samples TXENB_B at the rising edge of TXCLK.
If TXENB_B is low, it loads the data on TXSOC and
TXDATA to the transmit FIFO at the edge of TXCLK. If
TXENB_B is high, the data on TXSOC and TXDATA is not
loaded to the transmit FIFO.
Caution This signal cannot be used with RXSEL_B at
the same time. Fix this signal to the low level
when it is not used.
TXSEL_B
252
G24
I
Transmit enable signal input (cell unit control).
This signal informs the µPD98414, in cell units, that the
ATM layer device is outputting valid transmit cell data to
TXDATA.
LVTTL
The µPD98414 samples TXSEL_B at the rising edge of the
TXCLK clock immediately before a high level is input to
TXSOC when it receives a transmit cell from the ATM layer
device. If TXSEL_B is low, the µPD98414 loads the cell
input in the next clock cycle to the transmit FIFO. Once the
µPD98414 has detected the low level of TXSEL_B and
started loading the cell, it does not sample TXSEL_B until
the next sampling timing (i.e., the clock immediately before
the next TXSOC input). If TXSEL_B is high at the clock
immediately before the high level is input to TXSOC, the
µPD98414 loads the next cell to the transmit FIFO.
Caution This signal cannot be used with RXSEL_B at
the same time. Fix this signal to the low level
when it is not used.
TXPRTY
70
G26
I
Parity bit input.
LVTTL
(Internal
pull-up)
This pin inputs the odd parity bit of the data input to
TXDATA. The µPD98414 calculates a parity based on the
input data and parity bit. If it detects an error, it sets the
UPED bit of the UEDR register to report the error. The
µPD98414 calculates a parity only within the range of 53
bytes of the a transmit cell (H1 to P48). An even parity can
be also used depending on the setting of the TRPM bit of
the MDR5 register.
TXDATA31- 164, 69, 328,
H25, H26, K23,
J26, K25, L24,
L25, L26, M24,
M25, N24, N23,
N26, P25, R26,
R25, T26, R23,
T24, U26, U24,
V26, V25, V24,
V23, W25, Y25,
Y24, AA25, Y23,
AB26, AB24
I
Transmit cell data input bus.
TXDATA0
68, 162, 248,
161, 66, 247,
160, 246, 325,
64, 158, 62,
157, 61, 323,
243, 60, 242,
59, 154, 241,
320, 153, 152,
239, 151, 318,
55, 237
LVTTL
These pins form a 32-bit data bus through which transmit
cell data is input. The µPD98414 inputs the data on this bus
at the rising edge of TXCLK.
Data Sheet S14242EJ2V0DS
16
µPD98414
1.3 Management Interface
The management interface is used to access the registers of the µPD98414.
(1/2)
Pin Name
RESET_B
Serial No.
168
Address No.
D25
I/O, Level
Function
I
System reset input.
This signal initializes the µPD98414. Input a low-pulse
LVTTL
(5V tolerant) signal having a width of at least 100 ns.
PHINT_B
BMODE
74
C26
E23
O
Interrupt signal output.
LVTTL
This signal informs the host of occurrence of an interrupt
(5V tolerant) cause.
333
I
Bus mode select input.
The mode of the management interface is determined from
LVTTL
(5V tolerant) the input level of this signal after a reset.
BMODE =
Low: <DS, R/W, ACK> -type is selected.
High: <RD, WR, RDY> -type is selected.
MADD7-
MADD0
335, 78, 172,
79, 258, 173,
80, 259
D22, A24, B23,
A23, C22, B22,
A22, C21
I
Address input.
LVTTL
These pins form the 8-bit bus used to input the addresses of
(5V tolerant) the internal registers.
MD15-MD0
337, 174, 81,
260, 175, 82,
176, 339, 83,
262, 177, 340,
84, 263, 178,
85
D20, B21, A21,
C20, B20, A20,
B19, D18, A19,
C18, B18, D17,
A18, C17, B17,
A17
I/O
16-bit data bus.
LVTTL
This 16-bit data bus is used to exchange data with the
(5V tolerant) internal registers.
RW
77
A25
I
Read/write signal input or write signal input.
The function of this signal differs depending on the mode set
(WR_B)
LVTTL
(5V tolerant) by BMODE.
When BMODE = low, it functions as a read/write control
signal (RW).
RW =High: Ready cycle
Low: Write cycle
When BMODE = high, it functions as a write signal
(WR_B) that specifies a write access.
ACK2S_B
257
171
255
C23
B24
D24
O
Acknowledge signal output or ready signal two-state output.
This pin indicates that data is ready when it is accessed for
(RDY2S_B)
LVTTL
(5V tolerant) read. It outputs an acknowledge ready signal, which
indicates that data can be received, in two states during the
write cycle.
ACK3S_B
O
Acknowledge signal output or ready signal tristate output.
This pin indicates that data is ready when it is accessed for
read. It outputs an acknowledge ready signal, which
(RDY3S_B)
3-state
LVTTL
(5V tolerant) indicates that data can be received, in tristate during the
write cycle.
CS_B
I
Chip select signal input.
LVTTL
When this signal is low, access to the internal registers of
the µPD98414 is enabled.
(5V tolerant)
Data Sheet S14242EJ2V0DS
17
µPD98414
(2/2)
Pin Name
Serial No.
169
Address No.
C25
I/O, Level
Function
DS_B
(RD_B)
I
Data strobe signal input or read signal input.
The function of this pin differs depending on the
LVTTL
(5V tolerant) management interface mode selected by the input to the
BMODE pin.
BMODE = low: Functions as a data strobe signal
(DS_B) that indicates that data is output
to MD.
BMODE = high: Functions as a read signal (RD_B) that
specifies a read access.
1.4 Overhead Interface
The overhead interface is used to transfer the contents of the section overhead (SOH) and path overhead (POH)
that are exchanged between the peripheral device and µPD98414.
(1/2)
Pin Name
TSOHCK
Serial No.
295
Address No.
AB04
I/O, Level
Function
O
Transmit TOH interface clock output (25.92 MHz).
LVTTL
This pin outputs a 25.92-MHz clock obtained by internally
dividing transmit clock TCLK (155.52 MHz) by six. TSOHFP
and TSOHD are output in sync with this divided clock.
TSOHFP
122
AC02
O
Transmit TOH frame pulse output.
LVTTL
TSOHFP is driven high one clock cycle before the input of
transmit TOH data is started.
TSOHD3-
TSOHD0
211, 22, 121,
23
AA03, AB01, AB02,
AC01
I
Transmit TOH data input 4-bit bus.
LVTTL
This is a 4-bit data bus that inputs transmit TOH data. It
(5V tolerant/ inputs the TOH data on TSOHD as 1 byte in two clock
Internal
cycles, starting from the clock cycle next to that in which
TSOHFP is output.
pull-down)
TSOHAV
212
AB03
I
Transmit TOH data validity indication signal input.
This signal informs the µPD98414 that valid TOH data has
been output to TSOHD. The µPD98414 samples TSOHAV
at the rising edge of TSOHCK during the first of the two
clock cycles in which SOH data is input. If TSOHAV is high,
the µPD98414 inputs the data on TSOHD in that cycle and
the next; when TSOHAV is low, the µPD98414 does not
input the data.
LVTTL
(5V tolerant/
Internal
pull-down)
TPOHCK
293
Y04
O
Transmit POH interface clock output (576 kHz).
This pin outputs the 576-kHz clock resulting from internally
dividing transmit clock TCLK (155.52 MHz) by 270.
TPOHFP and TPOHD are output in sync with this divided
clock.
LVTTL
TPOHFP
TPOHD
120
210
AA02
Y03
O
Transmit POH frame pulse output.
LVTTL
This signal is driven high one cycle before the clock cycle in
which the input of the transmit POH data is started.
I
Transmit POH data input.
LVTTL
This pin inputs serial transmit POH data. It inputs the
(5V tolerant/ transmit POH data on TPOHD as one byte in eight clock
Internal
cycles, starting from the clock cycle next to that in which
TPOHFP is output.
pull-down)
Data Sheet S14242EJ2V0DS
18
µPD98414
(2/2)
Pin Name
TPOHAV
Serial No.
Address No.
AA01
I/O, Level
Function
21
I
Transmit POH data validity indication signal input.
This signal informs the µPD98414 that valid POH data has
been output to TPOHD. The µPD98414 samples TPOHAV
at the rising edge of TPOHCK in the first of the eight clock
cycles in which POH data is input. If TPOHAV is high, the
µPD98414 inputs the TPOHD data for a duration of eight
clock cycles, starting from the cycle in which TPOHAV goes
high; if TPOHAV is low, the µPD98414 does not input the
TPOHD data.
LVTTL
(5V tolerant/
Internal
pull-down)
RSOHCK
RSOHFP
292
119
W04
Y02
O
Receive TOH interface clock output (25.92 MHz)
LVTTL
This pin outputs the 25.92-MHz clock obtained by internally
dividing receive clock RCLK (155.52 MHz) by six. RSOHFP
and RSOHAV are output in sync with this divided clock.
O
Receive TOH frame pulse output.
LVTTL
This signal goes high one cycle before the clock cycle in
which output of the receive SOH data is started.
RSOHD3-
RSOHD0
117, 19, 118,
209
V02, W01, W02,
W03
O
Receive TOH data output 4-bit bus.
LVTTL
This 4-bit data bus outputs receive TOH data. It starts
output of the receive SOH data onto RSOHD starting from
the clock cycle next to that in which RSOHFP is output.
RSOHAV
RPOHCK
20
Y01
U04
O
Receive TOH data validity indication signal output.
This signal indicates that valid receive TOH data is output to
RSOHD. In the clock cycle in which valid data is output to
RSOHD, RSOHAV goes high. In the clock cycle in which
valid data is not output, RSOHAV goes low.
LVTTL
290
O
Receive POH interface clock output (576 kHz).
This pin outputs a 576-kHz clock obtained by internally
dividing receive clock RCLK (155.52 MHz) by 270.
RPOHFP and RPOHAV are output in sync with this divided
clock.
LVTTL
RPOHFP
RPOHD
18
V01
U02
O
Receive POH frame pulse output.
LVTTL
This signal goes high one cycle before the clock cycle in
which output of receive POH data is started.
116
O
Receive POH data output.
LVTTL
This pin outputs serial receive POH data. It outputs the
receive POH data to RPOHD as one byte in eight clock
cycles, starting from the clock cycle next to that in which
RPOHFP is output.
RPOHAV
207
U03
O
Receive POH data validity indication signal output.
This signal indicates that valid receive POH data has been
output to RPOHD. In a clock cycle in which valid data is
output to RPOHD, RPOHAV goes high; in a cycle in which
valid data is not output, it goes low.
LVTTL
Data Sheet S14242EJ2V0DS
19
µPD98414
1.5 General-Purpose I/O Port
Pin Name
PIN2
Serial No.
123
Address No.
AD02
I/O, Level
Function
I
General-purpose input port.
These are general-purpose input pins that input the state
LVTTL
(Internal pull- signals of external peripheral devices. The signal levels of
down)
these pins are reflected on the bits of the internal GPSR
register. Changes in the statuses of these bits can be used
as interrupt causes.
PIN1, PIN0
27, 125
AF02, AE03
I
LVTTL
Caution Of PIN2 to PIN0, only PIN2 is not a 5-V
tolerant pin.
(5V tolerant/
Internal
pull-down)
POUT4-
POUT0
24, 213, 29,
48, 73
AD01, AC03, AF04,
AF23, D26
O
General-purpose output port.
LVTTL
The setting of the bits of the internal POUTR register are
output to these pins as signal levels. These pins can be
used to control external peripheral devices.
1.6 Alarm Signal Input/Output
Pin Name
Serial No.
Address No.
AC22, AE23,
I/O, Level
Function
O
Alarm signal output.
B1ERS, B2ERS, 314, 145,
LAISS, LCDS, 52, 149,
LOFS, LOPS, 316, 236,
LOSS, LRDIS, 148, 234,
OOFS, PAISS, 53, 146,
If the µPD98414 detects an event such as a fault or alarm at
AE26, AC25,
AB23, AC24,
AD25, AD23,
AD26, AE24,
AF24
LVTTL
the reception side, it sets the corresponding bit of the
internal ESTR register. One of these alarm signals goes
high to post notification of the occurrence of the event to an
external device. If the event is cleared and the bit of the
ESTR register is reset, the signal goes low.
PRDIS
49
TLAIS,
TLRDI,
TPAIS,
TPRDI
233,
28,
AD22,
AF03,
AE04,
AC05
I
Alarm transmit command input.
LVTTL
While any of these signals goes high, the corresponding
126,
297
(5V tolerant/ alarm frame (Line AIS, Line RDI, Path AIS, or Path RDI) is
Internal
transmitted. The transmission of an alarm frame can also
be specified by setting the CMR1 register.
pull-down)
Data Sheet S14242EJ2V0DS
20
µPD98414
1.7 JTAG Boundary Scan
Pin Name
JCK
Serial No.
191
Address No.
B04
I/O, Level
Function
Boundary scan clock input.
I
LVTTL
Ground this pin when not used.
(5V tolerant)
JDI
99
A03
D05
I
Boundary scan data input.
LVTTL
Ground this pin when not used.
(5V tolerant)
JDO
352
O
Boundary scan data output.
Open this pin when not used.
LVTTL
3-state
(5V tolerant)
JMS
276
192
C04
B03
I
Boundary scan mode select signal input.
Ground this pin when not used.
LVTTL
(5V tolerant)
JRST_B
I
Boundary scan reset signal input.
Ground this pin when not used.
LVTTL
(5V tolerant)
Remark About the treatment of JTAG boundary scan pins for normal operation
A pulse input to the RESET_B pin does not reset the JTAG logic.
If the JTAG logic has not been reset, the µPD98414 may not operate normally. Either of the following two
methods can be used to reset the JTAG logic. If the JRST_B pin is not connected to a ground, be sure to
reset the JTAG logic, using either method, after the power is switched on.
• Resetting the JTAG logic without using the JRST_B pin
Use the JMS and JCK pins to reset the JTAG logic and keep it reset (with the JRST_B pin pulled up).
Fix the JMS pin at 1 (pulled up), and input five or more clock cycles to the JCK pin.
• Using the JRST_B pin to reset the JTAG logic
If a low pulse is input to the JRST_B pin, and the JMS and JRST_B pins are pulled up and kept at a high
level, the JTAG logic is kept reset, so it does not affect normal operations. As for the JDI and JCK pins,
keep the input level pulled down or up.
Data Sheet S14242EJ2V0DS
21
µPD98414
1.8 Power and Grounding Pins
Pin Name
VDD
Serial No.
Address No.
I/O
Function
−
Power supply pins (+3.3 5%)
10, 13, 16, 31, 33,
K01, N01, T01, AF06, AF08,
AF25, AA26, W26, A12, A11,
A09, A07, A02, B02, E02,
M02, AE02, AE05, AE10, AE14,
AE21, AE25, AB25, U25, N25,
F25, B25, B15, B09, C03,
G03, H03, J03, N03, V03,
AD03, AD08, AD12, AD13, AD17,
AD18, AD19, AD24, W24, R24,
P24, K24, J24, H24, C24,
C19, C16, C14, C09, C06,
F04, K04, P04, T04, AC06,
AC15, AC16, AA23, M23, L23,
D21, D13, D11
50, 56, 58, 90, 91,
93, 95, 100, 101, 104,
111, 124, 127, 132, 136,
143, 147, 150, 155, 159,
166, 170, 180, 186, 193,
197, 198, 199, 203, 208,
214, 219, 223, 224, 228,
229, 230, 235, 240, 244,
245, 249, 250, 251, 256,
261, 264, 266, 271, 274,
279, 283, 287, 289, 298,
307, 308, 317, 326, 327,
336, 344, 346
−
GND
1, 7, 11, 14, 15,
A01, G01, L01, P01, R01,
AE01, AF01, AF07, AF13, AF15,
AF17, AF22, AF26, AC26, Y26,
P26, M26, K26, E26, B26,
A26, A16, A14, A13, A10,
A06, F02, L02, AE11, AE18,
T25, J25, B16, B10, B08,
F03, K03, R03, T03, AD06,
AA24, C12, D04, H04, J04,
L04, N04, V04, AA04, AC04,
AC08, AC10, AC11, AC13, AC18,
AC19, AC21, AC23, W23, U23,
T23, P23, J23, H23, F23,
D23, D19, D16, D14, D09,
D08, D06
Ground pins
25, 26, 32, 38, 40,
42, 47, 51, 54, 57,
63, 65, 67, 72, 75,
76, 86, 88, 89, 92,
96, 105, 110, 133, 140,
156, 163, 179, 185, 187,
196, 200, 205, 206, 217,
238, 268, 277, 281, 282,
284, 286, 291, 294, 296,
300, 302, 303, 305, 310,
311, 313, 315, 319, 321,
322, 324, 329, 330, 332,
334, 338, 341, 343, 348,
349, 351
1.9 Others
Pin Name
IC
Serial No.
3, 4, 98,
Address No.
I/O, Level
Function
−
C01, D01, A04,
D02, D03, E24,
C05, E04
Internal circuit connection test pins.
These pins must be kept open.
103, 194, 254,
275, 278
Data Sheet S14242EJ2V0DS
22
µPD98414
1.10 Handling Unused Pins
Depending on the mode, some pins are not used. These pins must be handled as listed below.
Pin Name
Handling
IC
Leave open.
Ground.
RCLK_N, TCLK_N
RCLK_P, TCLK_P
RXPLD[15:0], TXPLD[15:0]
CD
Pulled up to 3.3 V.
Pulled up to 3.3 V.
Pulled up to 3.3 or 5 V.
Ground.
RXCLK, RXENB_B, RXSEL_B, TXCLK,
TXENB_B, TXSOC, TXSEL_B
TXPRTY
Leave open.
Pulled up to 3.3 or 5 V.
Ground.
CS_B
MADD[7:0] , DS_B, RW
TSOHD[3:0], TSOHAV,
TPOHD, TPOHAV,
Ground.
PIN[2:0]
Leave open.
Ground.
TLAIS, TPAIS, TLRDI, TPRDI
JCK, JMS, JDI, JRST_B
Output pins
Ground.
Leave open.
Data Sheet S14242EJ2V0DS
23
µPD98414
1.11 Initial States of Each Pin
Pin Name
During a Reset
Immediately After Reset
Receive framer function
reset by CD pin = L
TPCLK_N/TPCLK_P
TXPLD15-TXPLD0
TCS
Not reset. Depends on TCLK_N/P input.
L
L
Not reset. Depends on TCLK_N/P input.
RCS
L
L
RXCLK_O
Not reset. Depends on RXCLK input.
RXSOC
L
L
L
L
RXCLAV
RXPRTY
Outputs parity bit of RXDATA[31:0].
RXDATA31-RXDATA0
TXCLK_O
L
L
Not reset. Depends on TXCLK input.
TXCLAV
L
L
PHINT_B
H
H
MD15-MD0
ACK2S_B/RDY2S_B
ACK3S_B/RDY3S_B
TSOHCK
Input mode (undefined)
H
Hi-Z
L
H
Hi-Z
L
TSOHFP
L
L
TPOHCK
L
L
TPOHFP
L
L
RSOHCK
L
L
L
L
L
L
L
L
L
L
RSOHFP
L
L
RSOHD3-RSOHD0
RSOHAV
L
L
L
L
RPOHCK
L
L
RPOHFP
L
L
RPOHD
L
L
RPOHAV
L
L
POUT4-POUT0
L
L
B1ERS, B2ERS,
LAISS, LCDS,
LOFS, LOPS,
LOSS, LRDIS,
OOFS, PAISS,
PRDIS
L
Other than LOPS, OOFS : L LOSS, OOFS, LOFS: Note
LOPS, OOFS
: H LOPS, LCDS: H
B1ERS, B2ERS, LAISS,
LRDIS, PAISS, PRDIS: L
JDO
Undefined
Undefined
Note The detection circuits of LOS, OOF, and LOF are not reset when CD pin is set to L. The states of LOSS,
OOFS, and LOFS pins depend on the input states of the line.
Data Sheet S14242EJ2V0DS
24
µPD98414
2. CONNECTION EXAMPLE OF MUX/DEMUX DEVICE
• Recommended MUX/DEMUX device
Connecting the following MUX and DEMUX devices to the µPD98414 is recommended:
AMCC SONET/SDH OC-48 16:1 TRANSMITTER S3043
1:16 RECEIVER
Clock Recovery
S3044
S3040
S3040
clock
recovery
µPD98414
S3043
MUX
S3044
µPD98414
(RX)
EO
OE
(TX)
DEMUX
(The S3040 is unnecessary if the optical link module (OE) has a clock recovery function.)
• Circuit connection example
Examples of connecting AMCC's S3043 and S3044 are shown below.
Figure 2-1. Example of Connecting µPD98414 and S3043 (Transmission Circuit)
S3043
(AMCC)
µPD98414
(NEC)
VDD (3.3 V)
91 Ω
91 Ω
16
PIN[15:0]
TXPLD[15:0]
124 Ω
0.1 µF
TPCLK_P/N
TCLK_P/N
PCLK P/N
2
155 MHz
PICLKN P/N
150 Ω
50 Ω
0.1 µF
0.01 µF
Oscillator
REFCLK P
REFCLK N
300 Ω
155 MHz
0.01 µF
PULSE
READ
400 Ω
Data Sheet S14242EJ2V0DS
25
µPD98414
Figure 2-2. Example of Connecting µPD98414 and S3044 (Reception Circuit)
µPD98414
S3044
(NEC)
(AMCC)
OVREF
VREF1
0.1 µF
0.1 µF
VREF2
VREF3
0.1 µF
16
RXPLD[15:0]
RCLK_P/N
POUT[15:0]
POCLK P/N
150 Ω
150 Ω
50 Ω
0.1 µF
2
50 Ω
0.1 µF
Data Sheet S14242EJ2V0DS
26
µPD98414
3. ELECTRIC CHARACTERISTICS
When seeing "Absolute Maximum Ratings," "Recommended Operating Conditions," or "DC Characteristics," see
also "Pin Classifications" described below.
ABSOLUTE MAXIMUM RATINGS
Parameter
Power supply voltage
Input/output voltage
Symbol
VDD
Conditions
Rating
−0.5 to +4.6
−0.5 to +4.6
−0.5 to +6.6
−0.5 to +4.6
20
Unit
V
VI1/VO1
VI2/VO2
VI3/VO3
IO1
LVTTL level
V
LVTTL level, 5-V tolerant pin
PECL-level pin
IOL = 6 mA
V
V
Output current
mA
mA
mA
mA
°C
°C
IO2
IOL = 9 mA
30
IO3
IOL = 12 mA
40
IO4
IOL = 18 mA
60
Operating ambient temperature
Storage temperature
TA
−40 to +85
−65 to +150
Tstg
Caution Absolute maximum ratings are rated values beyond which physical damage will be caused to the
product; if the rated value of any of the parameters in the above table is exceeded, even
momentarily, the quality of the product may deteriorate. Always use the product within its rated
values.
RECOMMENDED OPERATING CONDITIONS
Parameter
Power supply voltage
Symbol
VDD
Conditions
MIN.
3.135
−40
TYP.
3.3
MAX.
3.465
+85
Unit
V
Operating ambient temperature
High-level input voltage
TA
°C
V
VIH1
VIH2
VIH3
VIH4
VIL1
LVTTL-level pin
2.4
VDD
LVTTL level, 5-V tolerant pin
PECL-level pin (single-ended)
PECL-level pin (differential)
LVTTL-level pin
2.0
5.0
V
VIREF + 0.15
VDD−1.2
0
VDD
V
VDD−0.55
0.8
V
Low-level input voltage
V
VIL2
LVTTL level, 5-V tolerant pin
PECL-level pin (single-ended)
PECL-level pin (differential)
0
0.8
V
VIL3
0
VIREF−0.15
VDD−1.4
VDD/2+0.5
V
VIL4
VDD−2.0
VDD/2−0.5
300
V
VREF1-VREF3 pin input voltage
PECL differential input voltage
VIREF
VIDFF
V
PECL-level pin (differential)
mV
Caution Make sure that the product is air-cooled at a velocity of at least 1 m/s during operation.
Data Sheet S14242EJ2V0DS
27
µPD98414
DC CHARACTERISTICS (TA = −40°C to +85°C, VDD = 3.3 5%)
Parameter
Off-state output current
Input leakage current
Low-level output current
Symbol
IOZ
Conditions
VO = VDD or GND
MIN.
TYP.
MAX.
10
Unit
µA
ILI
VI = VDD or GND
10
µA
IOL1
IOL2
IOL3
IOL4
IOL5
IOH1
IOH2
IOH3
IOH4
IOH5
VOL1
VOL2
LVTTL-level pin
VOL = 0.4 V
6
12
18
6
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
LVTTL level, 5-V tolerant pin
VOL = 0.4 V
9
High-level output current
LVTTL-level pin
VOH = 2.4 V
−6
−12
−18
−2
−2
LVTTL level, 5-V tolerant pin
VOH = 2.4 V
Low-level output voltage
High-level output voltage
LVTTL-level pin, IOL = 0 mA
0.1
0.1
LVTTL level, 5-V tolerant
pin, IOL = 0 mA
V
VOL3
PECL-level pin, IOL = 0 mA
When terminated as shown
in Figure 2-1.
0.37 × VDD
0.45 × VDD
V
VOH1
VOH2
LVTTL-level pin, IOH = 0 mA
VDD−0.1
VDD−0.2
V
V
LVTTL level, 5-V tolerant pin,
IOH = 0 mA
VOH3
PECL-level pin, IOH = 0 mA
When terminated as shown
in Figure 2-1.
0.66 × VDD
0.75 × VDD
V
A
Supply current
IDD
Normal operation
1.05
1.3
CAPACITANCE
Parameter
Output capacitance
Input capacitance
I/O capacitance
Symbol
CO
Conditions
Frequency = 1 MHz
Frequency = 1 MHz
Frequency = 1 MHz
MIN.
TYP.
MAX.
10
Unit
pF
7
7
7
CI
10
pF
CIO
10
pF
Data Sheet S14242EJ2V0DS
28
µPD98414
PIN CLASSIFICATIONS
• Input pins
Category
VI1
Applicable Pins
Number of Pins
LVTTL-level pin
With pull-up
With pull-down
−
TXPRTY
PIN2
1
1
VIH1
VIL1
RXCLK, RXENB_B, RXDEL_B, TXCLK, TXDATA[31:0],
TXENB_B, TXSEL_B, TXSOC
39
LVTTL level
VI2
With pull-down
PIN0, PIN1, TLAIS, TLRDI, TPAIS, TPOHAV, TPOHD,
TPRDI, TSOHAV, TSOHD[3:0]
13
5-V tolerant pin
VIH2
VIL2
3-state
MD15-MD0
16
18
−
BMODE, CD, CS_B, DS_B/RD_B, MADD[7:0], RESET_B,
RW/WR_B, JCK, JDI, JMS, JRST_B
−
PECL-level pin
(single-ended)
VI3
RXPLD[15:0]
16
VIH3
VIL3
VI3
−
PECL-level pin
(differential)
RCLK_P, RCLK_N, TCLK_P, TCLK_N
4
VIH4
VIL4
VIDFF
Caution Of general-purpose input pins PIN2 to PIN0, only pin PIN2 is not 5-V tolerant.
• Output pins
Category
VO1
Applicable Pins
Number of Pins
31
LVTTL-level pin
IOL1/IOH1
IO1
B1ERS, B2ERS, LAISS, LCDS, LOFS, LOPS,
LOSS, LRDIS, OOFS, PAISS, POUT[4:0], PRDIS,
RPOHAV, RPOHCK, RPOHD, RPOHFP, RSOHAV,
RSOHCK, RSOHD[3:0], RSOHFP, TPOHCK,
TPOHFP, TSOHCK, TSOHFP
VOL1/VOH1
IOL2/IOH2
IO3
RCS, RXCLAV, RXDATA[31:0], RXPRTY, RXSOC,
TCS, TXCLAV
38
IOL3/IOH3
IOL4/IOH4
IOL5/IOH5
IO4
IO1
IO2
RXCLK_O, TXCLK_O
JDO
2
1
LVTTL level
VO2
5-V tolerant pin
VOL2/VOH2
ACK3S_B/RDY3S_B, ACK2S_B/RDY3S_B,
PHINT_B, MD[15:0] (3-state)
19
−
−
PECL-level pin
(single-ended)
PECL-level pin
(differential)
VO3
IO2
TXPLD[15:0]
16
2
VOL3/VOH3
VO3
IO2
TPCLK_P, TPCLK_N
VOL3/VOH3
Data Sheet S14242EJ2V0DS
29
µPD98414
AC CHARACTERISTICS (TA = −40°C to +85°C, VDD = 3.3 5%)
AC Test Conditions
• Delay time definition
VDD
Input pin
0.5 × VDD
0 V
Output pin
0.5 × VDD
tPD
• Load definition
D.U.T
(Device under test)
CL = 15 pF
(1) RESET_B input
Parameter
RESET_B pulse width
Symbol
tWRST
Conditions
MIN.
100
TYP.
MAX.
Unit
ns
tWRST
RESET_B
Data Sheet S14242EJ2V0DS
30
µPD98414
(2) Management interface
(a) Write timing (BMODE = 0)
Parameter
Symbol
tSADDS
tSCSDS
tSRWDS
tSDADS
tHADDS
tHCSDS
tHRWDS
tHDADS
tVAK2W
tVAK3W
tIAK2W
Conditions
MIN.
10
5
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address setup time (referred to DS_B↓)
CS_B setup time (referred to DS_B↓)
RW setup time (referred to DS_B↓)
Data setup time (referred to DS_B↑)
Address hold time (referred to DS_B↑)
CS_B hold time (referred to DS_B↑)
RW hold time (referred to DS_B↑)
Data hold time (referred to DS_B↑)
Delay from DS_B↓ to ACK2S_B output
Delay from DS_B↓ to ACK3S_B output
Delay from DS_B↑ to ACK2S_B float
Delay from DS_B↑ to ACK3S_B float
DS_B pulse width
5
15
4
1
1
4
Load capacitance = 15 pF, Note
Load capacitance = 15 pF, Note
Note
0
10
10
10
10
0
0
tVAK3W
tWDS
0
50
40
Minimum interval (1) from DS_B↑ to
DS_B↓
tDSINT1
Minimum interval (2) from DS_B↑ to
DS_B↓
tDSINT2
150
ns
Note tDSINT2 is a minimum interval when the following registers are continuously accessed. A shorter interval for
continuous access will cause the ACK2S_B (ACK3S_B) output delay to exceed the maximum value of
tVAK2W (tVAK3W).
tDSINT1 is a value when a register other than the following registers is accessed, or when one of the
following registers is first accessed.
Registers: RJ0ARR, RJ0APR, RJ0BRR, RJ0BPR, RJ1ARR, RJ1APR, RJ1BRR, RJ1BPR,
TJ0ARR, TJ0APR, TJ0BRR, TJ0BPR, TJ1ARR, TJ1APR, TJ1BRR, TJ1BPR
MADD[7:0]
tSADDS
tSCSDS
tHADDS
CS_B
tHCSDS
Data
MD[15:0]
DS_B
tHDADS
tDSINT1, tDSINT2
tHRWDS
tSDADS
tWDS
tSRWDS
RW
ACK2S_B
tVAK2W
tIAK2W
ACK3S_B
tVAK3W
tIAK3W
Data Sheet S14242EJ2V0DS
31
µPD98414
(b) Write timing (BMODE = 1)
Parameter
Symbol
tSADWR
tSCSWR
tSRDWR
tSDAWR
tHADWR
tHCSWR
tHRDWR
tHDAWR
tVRY2W
tVRY3W
tIRY2W
Conditions
MIN.
10
5
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address setup time (referred to WR_B↓)
CS_B setup time (referred to WR_B↓)
RD_B setup time (referred to WR_B↓)
Data setup time (referred to WR_B↑)
Address hold time (referred to WR_B↑)
CS_B hold time (referred to WR_B↑)
RD_B hold time (referred to WR_B↑)
Data hold time (referred to WR_B↑)
Delay from WR_B↓ to RDY2S_B output
Delay from WR_B↓ to RDY3S_B output
Delay from WR_B↑ to RDY2S_B float
Delay from WR_B↑ to RDY3S_B float
WR_B pulse width
5
15
4
1
40
4
Load capacitance = 15 pF, Note
Load capacitance = 15 pF, Note
Note
0
10
10
10
10
0
0
tIRY3W
0
tWWR
50
40
Minimum interval (1) from WR_B↑ to
WR_B↓
tWRINT1
Minimum interval (2) from WR_B↑ to
WR_B↓
tWRINT2
150
ns
Note tWRINT2 is a minimum interval when the following registers are continuously accessed. A shorter interval for
continuous access will cause the RDY2S_B (RDY3S_B) output delay to exceed the maximum value of
tVRY2W (tVRY3W).
tWRINT1 is a value when a register other than the following registers is accessed, or when one of the
following registers is first accessed.
Registers: RJ0ARR, RJ0APR, RJ0BRR, RJ0BPR, RJ1ARR, RJ1APR, RJ1BRR, RJ1BPR,
TJ0ARR, TJ0APR, TJ0BRR, TJ0BPR, TJ1ARR, TJ1APR, TJ1BRR, TJ1BPR
MADD[7:0]
tHADWR
tSADWR
tSCSWR
tHCSWR
CS_B
Data
tHDAWR
MD[15:0]
WR_B
tSDAWR
tWWR
tWRINT1, tWRINT2
RD_B
RDY2S_B
RDY3S_B
tHRDWR
tSRDWR
tVRY2W
tIRY2W
tVRY3W
tIRY3W
Data Sheet S14242EJ2V0DS
32
µPD98414
(c) Read timing (BMODE = 0)
Parameter
Symbol
tSADDS
tSCSDS
tSRWDS
tHADDS
tHCSDS
tHRWDS
tVAK2R
tVAK3R
tVDADS
tIAK2R
Conditions
MIN.
10
5
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address setup time (referred to DS_B↓)
CS_B setup time (referred to DS_B↓)
RW setup time (referred to DS_B↓)
Address hold time (referred to DS_B↑)
CS_B hold time (referred to DS_B↑)
RW hold time (referred to DS_B↑)
Delay from DS_B↓ to ACK2S_B output
Delay from DS_B↓ to ACK3S_B output
Delay from DS_B↓ to data output
Delay from DS_B↑ to ACK2S_B float
Delay from DS_B↑ to ACK3S_B float
Delay from DS_B↑ to data float
5
4
1
1
Load capacitance = 15 pF, Note
Load capacitance = 15 pF, Note
Note
0
10
10
22
10
10
22
20
0
0
0
tIAK3R
0
tIDADS
3
Delay from ACK2S_B[ACK3S_B]↓ to
tDDAAK
data output
DS_B pulse width
tWDS
50
40
ns
ns
Minimum interval (1) from DS_B↑ to
DS_B ↓
tDSINT1
Minimum interval (2) from DS_B↑ to
DS_B ↓
tDSINT2
150
ns
Note tDSINT2 is a minimum interval when the following registers are continuously accessed. A shorter interval for
continuous access will cause the ACK2S_B (ACK3S_B) output delay to exceed the maximum value of
tVAK2R (tVAK3R).
tDSINT1 is a value when a register other than the following registers is accessed, or when one of the
following registers is first accessed.
Registers: RJ0ARR, RJ0APR, RJ0BRR, RJ0BPR, RJ1ARR, RJ1APR, RJ1BRR, RJ1BPR, TJ0ARR,
TJ0APR, TJ0BRR, TJ0BPR, TJ1ARR, TJ1APR, TJ1BRR, TJ1BPR
MADD[7:0]
tSADDS
tHADDS
CS_B
tHCSDS
tSCSDS
Valid data
Invalid data
tWDS
MD[15:0]
DS_B
tVDADS
tIDADS
tDDAAK
tDSINT1, tDSINT2
RW
tHRWDS
tSRWDS
ACK2S_B
tVAK2R
tIAK2R
ACK3S_B
tVAK3R
tIAK3R
Data Sheet S14242EJ2V0DS
33
µPD98414
(d) Read timing (BMODE = 1)
Parameter
Symbol
tSADRD
tSCSRD
tSWRRD
tHADRD
tHCSRD
tHWRRD
tVRY2R
tVRY3R
tVDARD
tIRY2R
Conditions
MIN.
10
5
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address setup time (referred to RD_B↓)
CS_B setup time (referred to RD_B↓)
WR_B setup time (referred to RD_B↓)
Address hold time (referred to RD_B↑)
CS_B hold time (referred to RD_B↑)
WR_B hold time (referred to RD_B↑)
Delay from RD_B↓ to RDY2S_B output
Delay from RD_B↓ to RDY3S_B output
Delay from RD_B↓ to data output
Delay from RD_B↑ to RDY2S_B float
Delay from RD_B↑ to RDY3S_B float
Delay from RD_B↑ to data float
5
4
1
40
0
Load capacitance = 15 pF, Note
Load capacitance = 15 pF, Note
Note
10
10
22
10
10
22
20
0
0
0
tIRY3R
0
tIDARD
3
Delay from RDY2S_B[RDY3S_B]↓ to
tDDARY
data output
RD_B pulse width
tWRD
50
40
ns
ns
Minimum interval (1) from RD_B↑ to
RD_B↓
tRDINT1
Minimum interval (2) from RD_B↑ to
RD_B↓
tRDINT2
150
ns
Note tRDINT2 is a minimum interval when the following registers are continuously accessed. A shorter interval for
continuous access will cause the RDY2S_B (RDY3S_B) output delay to exceed the maximum value of
tVRY2R (tVRY3R).
tRDINT1 is a value when a register other than the following registers is accessed, or when one of the
following registers is first accessed.
Registers: RJ0ARR, RJ0APR, RJ0BRR, RJ0BPR, RJ1ARR, RJ1APR, RJ1BRR, RJ1BPR, TJ0ARR,
TJ0APR, TJ0BRR, TJ0BPR, TJ1ARR, TJ1APR, TJ1BRR, TJ1BPR
MADD[7:0]
tSADRD
tHADRD
CS_B
tSCSRD
tHCSRD
Invalid data
tDDARY
Valid data
MD[15:0]
RD_B
tVDARD
tIDARD
tRDINT1, tRDINT2
tWRD
WR_B
tHWRRD
tSWRRD
RDY2S_B
tVRY2R
tIRY2R
RDY3S_B
tVRY3R
tIRY3R
Data Sheet S14242EJ2V0DS
34
µPD98414
(3) Overhead interface
(a) Insert
Parameter
Symbol
fWSCKT
tWSCKT
tDSHPT
tSSHDT
tHSHDT
tSSHAT
tHSHAT
fWPCKT
tWPCKT
tDPHPT
tSPHDT
tHPHDT
tSPHAT
tHPHAT
Conditions
MIN.
TYP.
25.92
38.6
MAX.
Unit
MHz
ns
TSOHCK frequency
Note
Note
TSOHCK cycle time
Delay from TSOHCK↑ to TSOHFP output
TSOHD setup time (referred to TSOHCK↑)
TSOHD hold time (referred to TSOHCK↑)
TSOHAV setup time (referred to TSOHCK↑)
TSOHAV hold time (referred to TSOHCK↑)
TPOHCK frequency
Load capacitance: 15 pF
−6
20
2
+6
ns
ns
ns
20
2
ns
ns
Note
576
kHz
µs
ns
TPOHCK cycle time
Note
1.74
Delay from TPOHCK↑ to TPOHFP output
TPOHD setup time (referred to TPOHCK↑)
TPOHD hold time (referred to TPOHCK↑)
TPOHAV setup time (referred to TPOHCK↑)
TPOHAV hold time (referred to TPOHCK↑)
Load capacitance: 15 pF
−6
10
5
+6
ns
ns
10
5
ns
ns
Note TSOHCK and TPOHCK are divided clocks of TCLK_P/N.
TOH insert
TSOHCK
tWSCKT
tDSHPT
tDSHPT
TSOHFP
tSSHDT
tHSHDT
TSOHD[3:0]
tSSHAT
tHSHAT
TSOHAV
POH insert
TPOHCK
tWPCKT
tDPHPT
tDPHPT
TPOHFP
tSPHDT
tHPHDT
TPOHD
tSPHAT
tHPHAT
TPOHAV
Data Sheet S14242EJ2V0DS
35
µPD98414
(b) Extract
Parameter
Symbol
fWSCKR
tWSCKR
tDSHPR
tDSHDR
tDSHAR
fWPCKR
tWPCKR
tDPHPR
tDPHDR
tDPHAR
Conditions
MIN.
TYP.
25.92
38.6
MAX.
Unit
MHz
ns
RSOHCK frequency
Note
Note
RSOHCK cycle time
Delay from RSOHCK↑ to RSOHFP output
Delay from RSOHCK↑ to RSOHDT output
Delay from RSOHCK↑ to RSOHAV output
RPOHCK frequency
Load capacitance: 15 pF
Load capacitance: 15 pF
Load capacitance: 15 pF
Note
−3
−3
−3
+3
+3
+3
ns
ns
ns
576
kHz
µs
ns
RPOHCK cycle time
Note
1.74
Delay from RPOHCK↑ to RPOHFP output
Delay from RPOHCK↑ to RPOHDT output
Delay from RPOHCK↑ to RPOHAV output
Load capacitance: 15 pF
Load capacitance: 15 pF
Load capacitance: 15 pF
−3
−3
−3
+3
+3
+3
ns
ns
Note RSOHCK and RPOHCK are divided clocks of RCLK_P/N.
TOH extract
RSOHCK
tWSCKR
tDSHPR
tDSHPR
RSOHFP
tDSHDR
tDSHDR
RSOHD
tDSHAR
tDSHAR
RSOHAV
POH extract
RPOHCK
tWPCKR
tDPHPR
tDPHPR
RPOHFP
tDPHDR
tDPHDR
RPOHD
tDPHAR
tDPHAR
RPOHAV
Data Sheet S14242EJ2V0DS
36
µPD98414
(4) ATM layer interface
(a) Transmit ATM layer interface
Parameter
TXCLK frequency
Symbol
fCYTK
Conditions
MIN.
8
TYP.
MAX.
104
Unit
MHz
ns
TXCLK cycle time
tCYTK
9.6
3.9
3.9
0.5
0.5
2.8
125
TXCLK high level width
tWTKH
tWTKL
ns
TXCLK low level width
ns
Delay from TXCLK↑ to TXCLK_O output
Delay from TXCLK↑ to TXCLAV output
tDTKO
Load capacitance: 15 pF,Note
6
6
ns
tDCATK
tSDITK
Load capacitance: 15 pF
ns
TXDATA[31:0] setup time (referred to
ns
TXCLK↑)
TXDATA[31:0] hold time (referred to
tHDITK
0.5
ns
TXCLK↑)
TXSOC setup time (referred to TXCLK↑)
TXSOC hold time (referred to TXCLK↑)
TXPRTY setup time (referred to TXCLK↑)
TXPRTY hold time (referred to TXCLK↑)
TXENB_B setup time (referred to TXCLK↑)
TXENB_B hold time (referred to TXCLK↑)
TXSEL_B setup time (referred to TXCLK↑)
TXSEL_B hold time (referred to TXCLK↑)
tSSOTK
tHSOTK
tSPRTK
tHPRTK
tSENTK
tHENTK
tSSLTK
tHSLTK
2.8
0.5
2.8
0.5
2.8
0.5
2.8
0.5
ns
ns
ns
ns
ns
ns
ns
ns
Note TXCLK_O is logic inversion output of TXCLK.
tCYTK
tWTKL
tWTKH
TXCLK
TXCLK_O
tDTKO
TXCLAV
tSENTK
tHENTK
tDCATK
tDCATK
TXENB_B
TXSEL_B
TXSOC_B
tSSOTK
tHSOTK
tHSLTK
tSSLTK
TXDATA[31:0]
TXPRTY
tHDITK
tSDITK
tSPRTK
tHPRTK
Data Sheet S14242EJ2V0DS
37
µPD98414
(b) Recieve ATM layer interface
Parameter
RXCLK frequency
Symbol
fCYRK
Conditions
MIN.
8
TYP.
MAX.
104
Unit
MHz
ns
RXCLK cycle time
tCYRK
9.6
3.9
3.9
0.5
0.5
0.5
125
RXCLK high level width
tWRKH
tWRKL
ns
RXCLK low level width
ns
Delay from RXCLK↑ toRXCLK_O output
Delay from RXCLK↑ to RXCLAV output
tDRKO
Load capacitance: 15 pF,Note
Load capacitance: 15 pF
Load capacitance: 15 pF
6
6
6
ns
tDCARK
tDDORK
ns
Delay from RXCLK↑ to RXDATA[31:0]
ns
output
Delay from RXCLK↑ to RXSOC output
Delay from RXCLK↑ to RXPRTY output
RXENB_B setup time (referred to RXCLK↑)
RXENB_B hold time (referred to RXCLK↑)
RXSEL_B setup time (referred to RXCLK↑)
RXSEL_B hold time (referred to TXCLK↑)
tDSORK
tDPRRK
tSENRK
tHENRK
tSSLRK
tHSLRK
Load capacitance: 15 pF
Load capacitance: 15 pF
0.5
0.5
2.8
0.5
2.8
0.5
6
6
ns
ns
ns
ns
ns
ns
Note RXCLK_O is logic inversion output of RXCLK.
tCYRK
tWRKH
tWRKL
RXCLK
RXCLK_O
RXCLAV
tDRKO
tDCARK
tDCARK
RXENB_B
tHENRK
tSENRK
RXSEL_B
RXSOC_B
tSSLRK
tHSLRK
tDSORK
tDSORK
tDDORK
tDPRRK
RXDATA[31:0]
RXPRTY
tDDORK
tDPRRK
Data Sheet S14242EJ2V0DS
38
µPD98414
(5) Line interface
Parameter
Symbol
fCYTC
Conditions
MIN.
TYP.
155.52
6.43
MAX.
Unit
MHz
ns
TCLK_P[TCLK_N] frequency
TCLK_P[TCLK_N] cycle time
tCYTC
TCLK_P[TCLK_N] high level width
TCLK_P[TCLK_N] low level width
RCLK_P[RCLK_N] frequency
tWTCH
tWTCL
fCYRC
tCYRC
tWRCH
tWRCL
tDTDO
tDTPCO
2.6
2.6
ns
ns
155.52
6.43
MHz
ns
RCLK_P[RCLK_N] cycle time
RCLK_P[RCLK_N] high level width
RCLK_P[RCLK_N] low level width
Delay from TCLK_P↑ to TXPLD[15:0]
2.6
2.6
0.5
0.5
ns
ns
4.0
4.5
ns
Delay from TCLK_P[TCLK_N]↑ to
TPCLK_P[TPCLK_N]↓
Note
ns
RXPLD[15:0] setup time (referred to
RXCLK↑)
tSRDI
tHRDI
1.8
0.5
ns
ns
RXPLD[15:0] hold time (referred to
RXCLK↑)
Note TPCLK_P, TPCLK_N are logic inversion outputs of TCLK_P, TCLK_N.
tCYTC
tWTCL
tWTCH
TCLK_P
TXPLD[15:0]
TPCLK_P
tDTDO
tDTPCO
TCLK_P (TCLK_N)
TPCLK_P (TPCLK_N)
tDTPCO
tCYRC
tWRCL
tWRCH
RCLK_P
RXPLD[15:0]
tSRDI
tHRDI
Data Sheet S14242EJ2V0DS
39
µPD98414
(6) JTAG boundary scan
Parameter
JCK cycle time
Symbol
tCYJCK
tJCKH
tJCKL
Conditions
MIN.
250
100
100
30
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
JCK high level width
JCK low level width
JMS setup time
tSJMS
tHJMS
tSJDI
JMS hold time
30
JDI setup time
30
JDI hold time
tHJDI
30
Capture_DR data input setup time
Capture_DR data input hold time
Delay from JCK↓ to Up Date_DR output
Delay from JCK↓ to JDO
JRST_B low level width
tSJIN
30
tHJIN
30
tDJOUT
tDJDO
tJRSTL
0
50
50
0
tCYJCK
tCYJCK
tJCKH
tJCKL
JCK
JRST_B
JMS
tJRSTL
tSJMS
tHJMS
tSJDI
tHJDI
JDI
tDJDO
JDO
tSJIN
tHJIN
All input
All output
tDJOUT
Data Sheet S14242EJ2V0DS
40
µPD98414
4. PACKAGE DRAWING
352-PIN PLASTIC BGA (CAVITY DOWN ADVANCED TYPE) (35x35)
B
D
ZE
ZD
A
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
E
8
7
6
5
4
3
2
1
AE AC AA W U
R
N
L
J G E C A
AF AD AB Y
V Y P M K H F D B
Index area
3-C0.5
A2
C1.25
A
S
e
y
S
A
A1
A4
M
M
φ
φ
x1
x2
S
S
A B
352- b
φ
detail of A part
ITEM MILLIMETERS
35.00 0.20
35.00 0.20
1.27
D
E
e
A
1.50 0.30
0.60 0.10
0.90
A1
A2
A4
b
0.25 MIN.
0.75 0.15
0.30
x1
x2
y
0.15
0.20
ZD
ZE
1.625
1.625
P352F2-127-RN1-1
Data Sheet S14242EJ2V0DS
41
µPD98414
5. RECOMMENDED SOLDERING CONDITIONS
The conditions listed below shall be met when soldering the µPD98414.
For details of the recommended soldering conditions, refer to our document Semiconductor Device Mounting
Technology Manual (C10535E).
Please consult with our sales offices in case any other soldering process is used, or in case soldering is done
under different conditions.
Surface-Mount Type
•
µPD98414F2-RN1: 352-pin plastic BGA (cavity down advanced type) (35 × 35)
Soldering Process
Infrared ray reflow
Soldering Conditions
Peak package's surface temperature: 220°C
Symbol
IR20-202-2
Reflow time: 30 seconds or less (210°C or more)
Maximum allowable number of reflow processes: 2
Exposure limit: 2 daysNote (20 hours of pre-baking is required at 125°C afterward)
<Caution>
Non-heat-resistant trays, such as magazine and taping trays, cannot be baked before
unpacking.
Note Maximum number of days during which the product can be stored at a temperature of 25°C and a relative
humidity of 65% or less after dry-pack package is opened.
Data Sheet S14242EJ2V0DS
42
µPD98414
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet S14242EJ2V0DS
43
µPD98414
NEASCOT-P70 is a trademark of NEC Corporation.
•
The information in this document is current as of July, 2001. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
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