UPD98421F1-GA1 [RENESAS]
Content Addressable SRAM, 8KX64, MOS, PBGA240, 16 X 16 MM, PLASTIC, FBGA-240;
| 型号： | UPD98421F1-GA1 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Content Addressable SRAM, 8KX64, MOS, PBGA240, 16 X 16 MM, PLASTIC, FBGA-240 静态存储器 |
| 文件： | 总44页 (文件大小：325K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD98421
HIGH-SPEED ADDRESS SEARCH ENGINE
DESCRIPTION
The µPD98421 is a CAM (Content Addressable Memory) with a capacity of 64 bits × 8192 entries. Equipped with
three types of search modes, this memory can search data at high speeds. One of these search modes, Longest
Prefix Match mode, can mask data in entry units and output the address with the longest match in the search data.
This function is effective for searching IP addresses of Layer 3.
FEATURES
• 64 bits × 8K entries
• High-speed synchronous operation. Maximum operating frequency: 33 MHz (normal mode)/50 MHz (FF mode)
• Mask register masking any bit of 64-bit search data
• Three search modes supported for high-speed searching.
•
•
•
Full Match mode:
30 ns (at 33 MHz)
Full Match with Mask mode: 30 ns
Longest Prefix Match mode: 60 ns
• Number of entries can be expanded by connecting multiple µPD98421s.
• Can read/write data by high-speed synchronous operation (memory operation).
• Supply voltage: 3.3 V 0.15 V
• 240-pin plastic FBGA
ORDERING INFORMATION
Part Number
Package
µPD98421F1-GA1
240-pin plastic FBGA (16 × 16)
Remark In this document, active-low pins are expressed as xxx_B (_B suffixed to a pin name).
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S13650EJ5V0DS00 (5th edition)
Date Published January 2002 NS CP (K)
Printed in Japan
The mark shows major revised points.
©
1998
µPD98421
BLOCK DIAGRAM
CLK
RESET_B
CE
V
GND
DD
Sequencer block
CE_B
WAIT_B
Bus I/F block
Search engine block
A12 to A0
DATA63 to DATA0
WE_B
FULL
FMSK
ENHIT_B
Search data register
OE_B
MEM
HAD0 to HAD12
HIT_B
ERR_B
Search mask data register
Mode register
SMD63 to SMD0
Memory block
Entry data memory
(64 bits 4096 words)
Mask data memory
(64 bits 4096 words)
×
×
2
Data Sheet S13650EJ5V0DS
µPD98421
SYSTEM CONFIGURATION EXAMPLE
Router LSI
Synchronous SRAM
CE_B, CE
A14 to A0
V
DD
SRAM_CE
DATA63 to DATA0
OE_B, WE_B
µ
PD98421 #0
ENHIT_B
ENHIT_B0
HIT_B0
CE_B, CE
µPD98421_CE0
HIT_B
HAD12 to HAD0
ERR_B
A12 to A0
DATA63 to DATA0
OE_B, WE_B
MEM, FULL, FMSK
SMD63 to SMD0
µ
PD98421 #1
ENHIT_B
ENHIT_B1
HIT_B1
µPD98421_CE1
CE_B, CE
HIT_B
HAD12 to HAD0
ERR_B
A12 to A0
DATA63 to DATA0
OE_B, WE_B
MEM, FULL, FMSK
SMD63 to SMD0
Glue
logic
A14 to A0
DATA63 to DATA0
OE_B, WE_B
MEM, FULL, FMSK
µ
PD98421 #n
ENHIT_Bn
HIT_Bn
ENHIT_B
µPD98421_CEn
CE_B, CE
HIT_B
HAD12 to HAD0
ERR_B
A12 to A0
DATA63 to DATA0
OE_B, WE_B
MEM, FULL, FMSK
SMD63 to SMD0
Hit address12 to 0
Hit address14, 13
HADOUT
ERR_B
HIT_B
ERROUT_B
HITOUT_B
3
Data Sheet S13650EJ5V0DS
µPD98421
PIN CONFIGURATION
• 240-pin plastic FBGA (16 × 16)
µ
PD98421F1-GA1
(Top view)
Index mark
43
44
45
108 109
164
18
17
16
15
14
13
12
11
10
9
47
48
49
50
51
52
53
35
36
38
39
40
41
42
46
37
105 106 107
161
102
110 111
114
115
34
33
99
98
100 101
103 104
112 113
168
156
155
160
162 163
157 158 159
165 166 167
54
55
208 209
211 212 213 214 169 116
32
97 154 203 204 205 206 207
210
233 234 235 236
215
31
30
96
95
94
153 202
152 201
170 117
56
216 171 118
217 172 119
57
58
29
151 200
28
27
93 150 199 232
92 149 198 231
237 218 173 120
59
60
61
µ
PD98421F1-GA1
(Bottom view)
238 219 174 121
239 220 175 122
240 221 176 123
222 177 124
26
25
91
90
148 197 230
8
147 196 229
146 195
62
63
7
89
24
23
88 145 194
6
223 178 125
64
65
66
22
21
20
87
86
85
144 193
143
228 227 226 225
126
5
224 179
192 191 190 189 188 187 186 185 184 183 182 181
127
4
180
142 141
140 139 138 137 136 135 134
133 132 131 130 129 128 67
3
19
18
84
17
83
16
82
15
81
14
79
12
2
80
13
78
11
77
10
76
9
75
8
74
7
73
6
72
5
71
4
70
3
69
2
68
1
1
Index mark
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
4
Data Sheet S13650EJ5V0DS
µPD98421
Pin No.
1 (A1)
Pin Name
Pin No.
49 (D18)
50 (C18)
51 (B18)
52 (A18)
53 (A17)
54 (A16)
55 (A15)
56 (A14)
57 (A13)
58 (A12)
59 (A11)
60 (A10)
61 (A9)
62 (A8)
63 (A7)
64 (A6)
65 (A5)
66 (A4)
67 (A3)
68 (A2)
69 (B2)
70 (C2)
71 (D2)
72 (E2)
73 (F2)
74 (G2)
75 (H2)
76 (J2)
Pin Name
DATA23
SMD22
DATA21
SMD20
VDD
Pin No.
Pin Name
Pin No.
145 (T6)
146 (T7)
147 (T8)
148 (T9)
Pin Name
GND
Pin No.
Pin Name
DATA38
DATA40
SMD38
DATA35
GND
L
97 (U15) GND
98 (U16) A3
193 (R5)
194 (R6)
195 (R7)
196 (R8)
197 (R9)
2 (B1)
L
GND
3 (C1)
I.C.
99 (U17)
VDD
SMD36
DATA34
4 (D1)
DATA63
GND
100 (T17) A1
5 (E1)
101 (R17) HAD12
102 (P17) GND
149 (T10) DATA32
150 (T11) WE_B
151 (T12) MEM
152 (T13) GND
153 (T14) A9
6 (F1)
DATA60
SMD59
DATA57
VDD
DATA18
DATA17
GND
198 (R10) SMD32
199 (R11) OE_B
200 (R12) CE_B
201 (R13) A12
202 (R14) A8
7 (G1)
103 (N17) HAD6
104 (M17) HAD3
105 (L17) GND
8 (H1)
9 (J1)
SMD15
SMD13
VDD
10 (K1)
11 (L1)
12 (M1)
13 (N1)
14 (P1)
15 (R1)
16 (T1)
17 (U1)
18 (V1)
19 (V2)
20 (V3)
21 (V4)
22 (V5)
23 (V6)
24 (V7)
25 (V8)
26 (V9)
27 (V10)
28 (V11)
29 (V12)
30 (V13)
31 (V14)
32 (V15)
33 (V16)
34 (V17)
35 (V18)
36 (U18)
37 (T18)
38 (R18)
39 (P18)
40 (N18)
SMD55
SMD53
GND
106 (K17) ENHIT_B
107 (J17) SMD30
108 (H17) DATA28
109 (G17) DATA26
110 (F17) DATA25
111 (E17) GND
154 (T15) A6
155 (T16) A4
203 (R15) A0
SMD10
SMD9
DATA7
GND
156 (R16) HAD11
157 (P16) HAD9
158 (N16) HAD7
159 (M16) HAD2
160 (L16) VDD
204 (P15) GND
205 (N15) VDD
206 (M15) HAD4
207 (L15) HIT_B
208 (K15) SMD31
SMD50
DATA48
GND
DATA46
DATA45
SMD44
GND
SMD4
SMD3
GND
112 (D17) GND
113 (C17) DATA20
114 (B17) GND
161 (K16) RESET_B
162 (J16) GND
163 (H16) SMD28
164 (G16) SMD26
165 (F16) SMD25
166 (E16) SMD23
167 (D16) VDD
209 (J15)
VDD
210 (H15) GND
DATA0
VDD
115 (B16) DATA19
116 (B15) SMD18
117 (B14) DATA16
118 (B13) DATA15
119 (B12) GND
211 (G15) VDD
DATA42
GND
212 (F15) SMD24
213 (E15) DATA22
214 (D15) SMD19
215 (D14) DATA14
216 (D13) SMD16
217 (D12) SMD14
218 (D11) DATA11
219 (D10) DATA9
GND
SMD40
SMD39
DATA37
GND
I.C.
VDD
DATA62
SMD61
GND
120 (B11) SMD12
121 (B10) SMD11
122 (B9) DATA8
123 (B8) SMD7
124 (B7) SMD5
168 (C16) SMD21
169 (C15) GND
170 (C14) SMD17
171 (C13) VDD
SMD34
DATA33
CLK
SMD58
DATA56
DATA54
DATA52
SMD51
DATA49
VDD
172 (C12) DATA13
173 (C11) GND
174 (C10) DATA10
220 (D9)
221 (D8)
222 (D7)
223 (D6)
224 (D5)
225 (H5)
226 (J5)
227 (K5)
228 (L5)
229 (P8)
230 (P9)
GND
WAIT_B
CE
77 (K2)
78 (L2)
125 (B6)
VDD
SMD6
GND
126 (B5) SMD2
127 (B4) SMD0
N.C.
79 (M2)
80 (N2)
81 (P2)
82 (R2)
83 (T2)
84 (U2)
85 (U3)
86 (U4)
87 (U5)
88 (U6)
89 (U7)
90 (U8)
91 (U9)
92 (U10)
93 (U11)
94 (U12)
95 (U13)
96 (U14)
175 (C9)
176 (C8)
177 (C7)
178 (C6)
179 (C5)
180 (C4)
181 (D4)
182 (E4)
183 (F4)
184 (G4)
185 (H4)
186 (J4)
187 (K4)
188 (L4)
SMD8
DATA6
DATA4
DATA3
DATA1
GND
DATA2
SMD1
DATA58
GND
A10
128 (B3)
129 (C3)
L
L
A7
A5
SMD46
DATA44
VDD
130 (D3) GND
A2
131 (E3) SMD63
132 (F3) DATA61
133 (G3) DATA59
134 (H3) GND
DATA53
DATA51
SMD37
VDD
GND
N.C.
DATA43
SMD42
SMD41
DATA39
VDD
L
HAD10
HAD8
HAD5
SMD60
SMD62
VDD
135 (J3) SMD56
136 (K3) SMD54
137 (L3) SMD52
138 (M3) DATA50
139 (N3) SMD49
140 (P3) DATA47
141 (R3) GND
231 (P10) GND
232 (P11) FULL
233 (L14) HAD0
234 (K14) DATA31
235 (J14) DATA29
236 (H14) SMD27
237 (E11) DATA12
238 (E10) GND
41 (M18) HAD1
SMD57
DATA55
GND
42 (L18)
43 (K18)
44 (J18)
45 (H18)
ERR_B
GND
DATA36
SMD35
SMD33
GND
DATA30
SMD29
VDD
189 (M4) GND
46 (G18) DATA27
FMSK
VDD
142 (T3) SMD45
190 (N4)
191 (P4)
192 (R4)
SMD48
47 (F18)
48 (E18)
GND
143 (T4)
VDD
SMD47
SMD43
239 (E9)
240 (E8)
VDD
DATA24
A11
144 (T5) DATA41
DATA5
Remarks 1. Figures in parentheses indicate the coordinates in the pin configuration.
2. I.C.: Internal Connection
L:
Fixed at low level
N.C.: No Connection
5
Data Sheet S13650EJ5V0DS
µPD98421
PIN NAMES
A12 to A0:
CE, CE_B:
CLK:
Address
Chip Select
Clock
DATA63 to DATA0: Data
ENHIT_B:
ERR_B:
FMSK:
Enable Hit
Error
Full Match Mask Mode
Full Match Mode
Ground
FULL:
GND:
HAD12 to HAD0:
HIT_B:
Hit Address
Hit
MEM:
Memory
OE_B:
Output Enable
Reset
RESET_B:
SMD63 to SMD0:
VDD:
Search Mask Data
Supply Voltage
Wait
WAIT_B:
WE_B:
Write Enable
6
Data Sheet S13650EJ5V0DS
µPD98421
CONTENTS
1. PIN FUNCTIONS...................................................................................................................................8
2. MEMORY/REGISTER CONFIGURATION..........................................................................................11
2.1 Memory Configuration...............................................................................................................11
2.1.1 Full Match mode...............................................................................................................................11
2.1.2 Full Match with Mask/Longest Prefix Match mode...........................................................................11
2.2 Register Configuration ..............................................................................................................12
2.2.1 Search data register.........................................................................................................................12
2.2.2 Mask data register............................................................................................................................12
2.2.3 Mode register ...................................................................................................................................13
2.2.4 NOP register.....................................................................................................................................13
3. FUNCTIONAL DESCRIPTION............................................................................................................14
3.1 Memory Operation .....................................................................................................................14
3.2 Search Operation .......................................................................................................................14
3.2.1 Full Match mode...............................................................................................................................14
3.2.2 Full Match with Mask mode..............................................................................................................15
3.2.3 Longest Prefix Match mode..............................................................................................................17
3.2.4 Other points to be noted...................................................................................................................19
4. ELECTRICAL SPECIFICATIONS.......................................................................................................21
5. RECOMMENDED SOLDERING CONDITIONS.................................................................................38
6. PACKAGE DRAWING ........................................................................................................................39
7
Data Sheet S13650EJ5V0DS
µPD98421
1. PIN FUNCTIONS
Pin Name
CLK
Pin No.
I/O
Description
28
29
Input
Clock.
System clock input pin. Inputs a clock of up to 33 MHz (normal mode)/50 MHz
(FF mode).
WAIT_B
Input
Wait.
Wait input pin. Asserted active at low level. If the WAIT_B signal is active at
the rising edge of CLK, the µPD98421 is placed in a wait status for the duration
of 1 CLK cycle from the next rising of CLK. In wait status, all the pins retain the
status immediately before the wait status was set. However, output control by
CE, CE_B, and ENHIT_B is valid.
CE_B
200
30
Input
Input
Chip select.
Asserted active at low level. When the CE signal and CE_B signal of a chip
are asserted active at the same time, the chip is selected.
DATA, HAD, ERR_B, and SMD of the unselected chip enter a high-impedance
state.
CE
Chip select.
Asserted active at low level. When the CE signal and CE_B signal of a chip
are asserted active at the same time, the chip is selected.
DATA, HAD, ERR_B, and SMD of the unselected chip enter a high-impedance
state.
A12 to A0
201, 96, 32, 153,
202, 33, 154, 34,
155, 98, 35, 100,
203
Input
I/O
Address.
A12 to A0 are 13-bit address signals.
Signals input to A12 through A8 are ignored in the I/O access mode.
DATA63 to
DATA0
4, 72, 132, 6, 133,
225, 8, 76, 186,
77, 227, 78, 228,
138, 80, 14, 140,
16, 17, 83, 85, 20,
144, 194, 88, 193,
24, 90, 196, 148,
27, 149, 234, 44,
235, 108, 46, 109,
110, 48, 49, 213,
51, 113, 115, 54,
55, 117, 118, 215,
172, 237, 218,
Data.
DATA63 to DATA0 are data bus signals that input/output 64-bit data to/from the
internal memory and registers.
174, 219, 122, 62,
176, 240, 177,
178, 223, 179, 67
WE_B
OE_B
150
Input
Input
Write enable.
Enables writing to DATA63 to DATA0. When the WE_B signal is active,
DATA63 to DATA0 enter a high-impedance state.
199
Output enable.
Enables output of data from DATA63 to DATA0.
8
Data Sheet S13650EJ5V0DS
µPD98421
Pin Name
MEM
Pin No.
I/O
Description
151
Input
Memory.
Specifies access right to memory/register.
When the MEM signal is high, the µPD98421 performs the same operations as
an SRAM (refer to 3. FUNCTIONAL DESCRIPTION). When this signal is low,
the internal registers can be accessed for input/output.
MEM
Access function
Memory access
I/O access
1
0
FULL
232
94
Input
Input
Full Match Mode.
Sets a search mode with the MEM and FMSK signals (refer to 3.
FUNCTIONAL DESCRIPTION).
FMSK
Full Match with Mask mode.
Sets a search mode with the MEM and FULL signals (refer to 3. FUNCTIONAL
DESCRIPTION).
HAD12 to
HAD0
101, 156, 38, 157, Output
39, 158, 103, 40, 3 state
Hit address.
HAD12 through HAD0 output a matched valid address if the HIT_B signal goes
206, 104, 159, 41, (Internal low and ERR_B goes high during a search operation. If ERR_B is asserted
233
pull-up) active (low level), HAD output is invalid. HAD12 is meaningless except in the
Full Match mode.
These pins are internally pulled up.
HIT_B
207
Output
Hit.
Data is searched after it is written to the search data register during a search
operation. HIT_B is a low-active signal that indicates that data matching the
search data has been found.
0: Match data found, 1: Match data not found
ERR_B
ENHIT_B
42
Output
(Open
drain)
Error.
This signal goes low if two or more sets of entry data having the same mask
data are found during a search operation.
Because this is an open-drain signal, pull it up.
This signal is inactive (high-impedance) during a memory operation.
106
Input
Enable hit.
This signal controls output of the HAD12 to HAD0 and ERR_B signals.
ENHIT_B HAD[12:0]
ERR_B
1
0
Hi-Z
Hi-Z
Output enabled
SMD63 to
SMD0
131, 183, 73, 182, 7, I/O
75, 185, 135, 10,
136, 11, 137, 79, 13, pull-up) in the Longest Prefix Match mode. Connect each of these pins to the
Search mask data.
(Internal The SMD63 to SMD0 signals are used for temporary I/O with other µPD98421s
139, 190, 191, 82,
142, 18, 192, 86, 87,
22, 23, 195, 229,
147, 91, 26, 92, 198,
208, 107, 45, 163,
236, 164, 165, 212,
166, 50, 168, 52,
214, 116, 170, 216,
57, 217, 58, 120,
121, 60, 61, 175,
123, 221, 124, 64,
65, 126, 224, 127
corresponding pin of the other µPD98421s.
9
Data Sheet S13650EJ5V0DS
µPD98421
Pin Name
RESET_B
Pin No.
I/O
Description
161
Input
Reset.
When this signal is set to low, the chip is initialized. Only the internal
sequencer and mode register are initialized; the memory area is not cleared.
Be sure to create an external circuit in which RESET_B becomes low level after
power application. In addition, input at least 2 CLK or more NOP commands
continuously after releasing reset.
VDD
GND
9, 53, 59, 68, 71, 81,
84, 89, 95, 99, 125,
143, 160, 167, 171,
184, 188, 205, 209,
211, 230, 239
–
–
3.3 V power supply
5, 12, 15, 19, 21, 25,
36, 43, 47, 56, 63,
66, 69, 74, 93, 97,
102, 105, 111, 112,
114, 119, 130, 134,
141, 145, 146, 152,
162, 169, 173, 180,
187, 189, 197, 204,
210, 220, 222, 226,
231, 238
Ground
N.C.
I.C.
L
31, 37
–
–
–
No connection.
Leave open.
3, 70
Internally connected.
Leave open.
1, 2, 128, 129, 181
Always fix these pins at low level.
10
Data Sheet S13650EJ5V0DS
µPD98421
2. MEMORY/REGISTER CONFIGURATION
2.1 Memory Configuration
The µPD98421 has a memory area of 64 bits × 8192 entries. Two types of memory configurations can be
selected in accordance with the search mode. For this selection, no special setting of the chip is necessary. The
µPD98421 can also be used as a synchronous SRAM.
2.1.1 Full Match mode
64 bits × 8192 entries: Entry data
In the Full Match mode, all the 8192 entries are used as a data area.
Table 2-1. Memory Mapping in Full Match Mode
Address
0000h
0001h
:
Contents
Entry data
Entry data
:
0FFFh
1000h
:
Entry data
Entry data
:
1FFEh
1FFFh
Entry data
Entry data
2.1.2 Full Match with Mask/Longest Prefix Match mode
64 bits × 4096 entries: Entry data
64 bits × 4096 entries: Entry mask data
In the Full Match with Mask and Longest Prefix Match modes, 4096 entries at addresses 0000h to 0FFFh are
used as a data area, and addresses 1000h to 1FFFh are used as a mask data area.
The mask data at 1000h to 1FFFh mask each of the corresponding entry data as shown in Table 2-2. If a bit of
the mask data is 0, the corresponding bit of the entry data is ignored during the search.
The mask data must be successively masked, starting from the LSB, in the Longest Prefix Match mode.
Example FFFF0000 → Correct, FF00F000 → Incorrect
11
Data Sheet S13650EJ5V0DS
µPD98421
Table 2-2. Memory Mapping in Full Match with Mask/Longest Prefix Match Modes
Address
0000h
0001h
:
Contents
Entry data
Entry data
:
0FFFh
1000h
:
Entry data
Mask data of 0000h
:
1FFEh
1FFFh
Mask data of 0FFEh
Mask data of 0FFFh
2.2 Register Configuration
The µPD98421 allocates the internal registers to 256 words of I/O addresses. Each register is 64 bits long.
Address signal lines A0 through A7 are used to specify an I/O address to access a register. A8 through A12 are not
used. When a register is accessed, the MEM signal line is made low. To write data to the register, the WE_B pin is
asserted active; to read data from the register, the OE_B pin is asserted active. Data can be written to a register in 1
clock cycle in both the normal and FF modes (except a search operation by writing data to the search data register).
When a register is read in the normal mode, the read data is output 1 clock cycle after the I/O address has been
input. In the FF mode, the read data is output 2 clock cycles after address input. For the details of the normal and
FF modes, refer to 2.2.3 Mode register.
Table 2-3. Internal Registers
I/O Address
00h
Register
Search data register
01h
Mask data register
02h
Mode register
03h
Reserved (do not access this register.)
NOP register
04h
05 to FFh
Reserved (do not access this register.)
2.2.1 Search data register
The search data is stored in this register. When 64-bit search data is written to the search data register, the
µPD98421 starts a search operation.
The search data register is not initialized even when the chip is reset.
2.2.2 Mask data register
The mask data register stores a value to mask the search data stored in the search data register. Store a valid
value in this register before a value is written to the search data register.
If a bit of the mask data register is 0, the corresponding bit of the search data register is masked and ignored. The
masking specified by this register is valid for all entries in all the search modes.
The mask data register is not initialized even when the chip is reset. When the bit width of all entries is less than
64 bits, it is recommended to mask unused bits using this function (to reduce the current consumption of the chip).
However, do not mask bit 63.
12
Data Sheet S13650EJ5V0DS
µPD98421
2.2.3 Mode register
The mode register selects the search timing mode (normal/FF mode) of the µPD98421 and controls the operations
of the µPD98421 without using the FULL, FMSK, and WAIT_B signal lines. This register is initialized to 0 after the
chip has been reset.
63
6
5
ff
4
3
2
1
0
reserved
full
fmsk
wait_b2
wait_b1
enbl
enbl
Validates or invalidates the full, fmsk, wait_b2, and wait_b1 bits of the mode register.
0: Invalidates full, fmsk, wait_b2, and wait_b1 bits, and validates the FULL, FMSK, and
WAIT_B signal lines.
1: Validates full, fmsk, wait_b2, and wait_b1 bits, and invalidates the FULL, FMSK, and
WAIT_B signal lines.
wait_b1
Specifies whether a wait cycle is inserted after the first clock.
0: Inserts 1 wait cycle after a search operation. In the Longest Prefix Match mode, one wait
cycle is inserted between the first search clock and second search clock.
1:
No operation
wait_b2
Specifies whether a wait cycle is inserted after the second clock.
0: Inserts one wait cycle after the second search clock in the Longest Prefix Match mode.
1: No operation
full, fmsk
Selects a search mode ([full, fmsk] = [xx]).
00: Longest Prefix Match mode
01: Reserved
10: Full Match mode
11: Full Match with Mask mode
ff
Selects a search timing mode (normal or FF mode).
0: Normal mode.
The hit address is output one clock after data has been input in the Full Match or Full
Match with Mask mode at up to 33 MHz. In the Longest Prefix Match mode, the hit
address is output two clocks after data has been input.
1: FF mode
The hit address is output two clocks after data has been input in the Full Match or Full
Match with Mask mode at up to 50 MHz. In the Longest Prefix Match mode, the hit
address is output four clocks after data has been input.
Reserved
reserved
bit 64 to bit 6
Do not access these bits.
Remark Do not execute another operation immediately after write access to the mode register or mask data
register. Be sure to perform NOP (write the NOP register) for the duration of at least 1 clock before
executing the another operation.
2.2.4 NOP register
When data is written to the NOP register, the µPD98421 is in a no-operation status, in which it performs nothing.
Keep the µPD98421 in this status when no operations such as search memory access are being performed. An
undefined value is read from the NOP register if it is read.
13
Data Sheet S13650EJ5V0DS
µPD98421
3. FUNCTIONAL DESCRIPTION
The µPD98421 can select an operation mode for memory operation and search operation by using combinations
of the MEM, FULL, and FMSK signals, or combinations of the full and fmsk bits.
Table 3-1. Operation Modes
MEM
FULL
FMSK
Function
Memory operation
1
0
0
0
0
×
1
1
0
0
×
0
1
0
1
Full Match mode
Full Match with Mask mode
Longest Prefix Match mode
None (setting prohibited)
3.1 Memory Operation
The µPD98421 can read or write 64-bit data from or to an internal memory cell during operation, like a
synchronous SRAM.
During memory operation, the MEM pin is set to high. When data is written, the WE_B signal is asserted active;
when data is read, the OE_B signal is asserted active.
Data can be written within 1 clock in both the normal and FF modes. When data is read, the read data is output 1
clock after address input in the normal mode. In the FF mode, the read data is output 2 clocks after address input.
Note, however, that outputting the read data can be delayed by inserting a WAIT cycle.
3.2 Search Operation
A search operation is started when a search mode is set and the search data is written to the search data register.
A search mode can be set by setting the MEM, FULL, and FMSK signal lines in the search mode (refer to Table 3-1)
or by using the mode register (refer to 2.2.3 Mode register).
3.2.1 Full Match mode
In the Full Match mode, data that completely matches is searched. In this mode, entry data of 8K entries and one
mask register can be used.
To search data in the Full Match mode, set the signal lines as shown in Table 3-1 (or set the mode register), and
write the search data to the search data register.
The value of the search data register is masked by the value of the mask data register and compared with the 64-
bit value of 8K words of memory cells. The bit of the search data register corresponding to a bit of the mask data
register that is set to 0 is not used for comparison.
One clock after the search data has been written to the search data register in the normal mode (in the FF mode,
two clocks after), the HIT_B signal is asserted active. The address of the match data is output to HAD12 to HAD0 if
ENHIT_B is set to 0. If two or more match data items are found during the search operation, ERR_B goes low, and
the output to HAD12 to HAD0 is invalid.
The timing to output the hit address can be delayed by inserting WAIT_B. When the ENHIT_B signal is set to 1,
ERR_B and HAD12 to HAD0 enter a high-impedance state.
14
Data Sheet S13650EJ5V0DS
µPD98421
Example To search the data in Table 3-2 from the data shown in Table 3-3 in the Full Match mode (for the sake
of convenience, 64-bit values are indicated in hexadecimal form in units of 8 bits).
Because bits 40 to 47 and 8 to 15 of the mask data register in Table 3-2 are 0, the data of the
corresponding bits of the search register (44 and 77) is not compared when the data of memory cells is
compared.
Bits 40 to 47 (ABh) and 8 to 15 (78h) of the data stored in 0003h are different from the values of the
search data register, but this is ignored depending on the mask data register setting. All the other bits
match the values of the search data register. This data is match data, and address 0003h is the match
address.
Table 3-2. Example of Search Data
Search Data Register
Mask Data Register
11.22.33.44.55.66.77.88
FF.FF.00.FF.FF.FF.00.FF
Table 3-3. Example of Data
Address
0000h
Data
FF.FF.FF.FF.FF.FF.FF.FF.
0001h
0002h
0003h
:
11.11.22.33.44.55.66.77
11.22.33.44.55.66.77.99
11.22.AB.44.55.66.77.88
:
3.2.2 Full Match with Mask mode
In the Full Match with Mask mode, data can be masked in entry units, and the data that completely matches is
searched. In this mode, 4K entry data can be used, and the mask register is valid.
To use the Full Match with Mask mode, set the signal line as shown in Table 3-1 (or set the mode register), and
write the search data to the search data register.
Write the mask data that masks the search data to the mask data register. This must be completed before the
search data is written to the search data register.
Each bit of the search data register is compared or ignored, depending on the value of the bit of the mask data
register at the same bit position.
A bit of the mask data register that is set to 1 is compared with the corresponding bit of the search data register; a
bit of the mask register that is reset to 0 is not compared with the corresponding bit of the search data register but
ignored.
The search data is compared with a 64-bit value of 4K words of memory cells.
The data of memory cells at addresses 0000h to 0FFFh are masked by the data of memory cells at 1000h to
1FFFh.
If a match data is found, one clock after the search data was written to the search data register in the normal
mode (two clocks after in the FF mode), the HIT signal is asserted active. The address of the match data is output to
HAD12 to HAD0 if ENHIT_B is set to 0.
The timing to output the hit address can be delayed by inserting WAIT_B.
15
Data Sheet S13650EJ5V0DS
µPD98421
Example To search data in Table 3-4 from data in Table 3-5
The value of the search data register is ignored when bits 24 to 31 and 8 to 15 are searched from the
value of the mask data register.
Data of 0000h is masked by the mask of 1000h and is not compared when bits 48 to 63 are searched.
In this way, the data of 0001h is the match data because of the relationship between each data and
mask. The match address is 0001h.
The value of 1003h is exactly the same as the value of the search data register, but it is not used as
the match data because this area is used as the mask data area in the Full Match with Mask mode.
Table 3-4. Example of Search Data
Search Data Register
Mask Data Register
11.22.33.44.55.66.77.88
FF.FF.FF.FF.00.FF.00.FF
Table 3-5. Example of Data
Address
0000h
Data
11.22.33.44.55.66.77.BB
11.22.AA.44.55.66.77.88
CC.22.33.44.55.66.77.88
99.AA.BB.CC.DD.EE.FF.00
:
Address
Mask
1000h
1001h
1002h
1003h
:
00.00.FF.FF.FF.FF.FF.FF.
FF.FF.00.FF.FF.FF.FF.FF
FF.FF.FF.FF.FF.FF.00.00
11.22.33.44.55.66.77.88
:
0001h
0002h
0003h
:
16
Data Sheet S13650EJ5V0DS
µPD98421
3.2.3 Longest Prefix Match mode
The Longest Prefix Match mode can search the data with the longest match in the search data, by means of
masking in entry units. The 4K-word area of addresses 0000h to 0FFFh is used as an entry data area, and 1000h to
1FFFh are used as a mask data area corresponding to the entry data. In the Longest Prefix Match mode, contiguous
bits, starting from the least significant bit, must be masked as the mask data (refer to 2.1.2 Full Match with
Mask/Longest Prefix Match mode). The mask data register is valid, and the masking set by this register is valid for
all the entries. The contiguous bits of the mask data register must be also masked, starting from the least significant
bit. To connect two or more µPD98421 chips, the values of the mask data registers of all the chips must be the
same.
Searching in the Longest Prefix Match mode is started by setting the signal lines as shown in Table 3-1 (or setting
the mode register) and writing the search data to the search data register. Two clocks after the search has been
started in the normal mode (four clocks after in the FF mode), the HIT_B pin is asserted active. The address of the
match data is output to the HAD12 to HAD0 pins if ENHIT_B is set to 0.
The timing to output the hit address can be delayed by inserting WAIT_B.
If two or more match data are found during the search operation, the ERR_B pin goes low, and the output to the
HAD12 to HAD0 pins is invalid. If no match data is found, both the HIT_B and ERR_B pins go high.
The mask data that masks search data is written to the mask data register. This must be completed before the
search data is written to the search data register.
The search data is compared with a 64-bit value of 4K words of memory cells.
The data of the memory cells at addresses 0000h to 0FFFh is masked by the data of memory cells at addresses
1000h to 1FFFh.
Unlike the other two modes, the data of a memory cell having a bit string with the longest successive match in the
search data, starting from the MSB, is the match data.
Example 1 To search with only one chip
The data shown in Table 3-6 is searched from the data of the memory cells shown in Table 3-7.
The value of the mask data register is masked after a value has been written to the search data register. Because
all the bits of the mask data are 1, all the bits of the search data register are compared when searched.
The data stored to each memory cell is compared in the same manner as in the Full Match with Mask mode.
Of the matching data, that which has the longest number of bits that match is the final match data. In this
example, it is the data of 0001h.
17
Data Sheet S13650EJ5V0DS
µPD98421
Table 3-6. Example of Search Data
Search Data Register
Mask Data Register
FF.FF.FF.FF.FF.FF.FF.FF
11.22.33.44.55.66.77.88
Table 3-7. Example of Data
Address
0000h
Data
11.22.33.44.00.00.00.00
11.22.33.44.55.66.77.00
11.22.33.44.55.00.00.00
11.22.33.44.55.66.77.AA
:
Address
1000h
Mask
FF.FF.FF.FF.00.00.00.00
FF.FF.FF.FF.FF.FF.FF.00
FF.FF.FF.FF.FF.00.00.00
FF.FF.FF.FF.FF.FF.00.00
:
0001h
0002h
0003h
:
1001h
1002h
1003h
:
Even when two or more µPD98421 chips are connected, the data with the longest match in the search data can
be searched from all the µPD98421s. This can be done by connecting the SMD63 to SMD0 pins of all the chips.
When two or more chips are connected, make sure that the values of the mask data registers of all the chips are
the same.
Example 2 To search with two or more chips
Data in Table 3-8 is searched from the data of the memory cells shown in Tables 3-9 to 3-11. These
tables show different µPD98421 chips.
When searching is started, 0001h of chip 1, 0002h of chip 2, and 0001h of chip 3 match as the match
addresses. In this case, 0002h of chip 2 in Table 3-10 has the shortest mask bit. Therefore, the data
of 0002h of chip 2 is the match data. At this time, only the HIT_B pin of chip 2 goes low; the HIT_B
pins of chips 1 and 3 go high.
Table 3-8. Search Data
Search Data Register
Mask Data Register
6E.13.01.22.5F.C2.77.E8
FF.FF.FF.FF.FF.FF.FF.FF
Table 3-9. Memory Cells of Chip 1
Address
0000h
Data
11.22.33.44.55.00.00.00
6E.13.01.22.5F.C2.77.00
6E.13.01.22.00.00.00.00
6F.FF.FF.FF.FF.00.00.00
:
Address
Mask
1000h
1001h
1002h
1003h
:
FF.FF.FF.FF.FF.00.00.00
FF.FF.FF.FF.FF.FF.00.00
FF.FF.FF.FF.00.00.00.00
FF.FF.FF.FF.FF.00.00.00
:
0001h
0002h
0003h
:
18
Data Sheet S13650EJ5V0DS
µPD98421
Table 3-10. Memory Cells of Chip 2
Address
0000h
Data
Address
1000h
Mask
FF.FF.FF.FF.00.00.00.00
FF.FF.FF.FF.FF.FF.00.00
FF.FF.FF.FF.FF.FF.FF.00
FF.FF.FF.FF.FF.FF.00.00
:
11.22.33.44.00.00.00
6E.13.01.22.5F.C2.00.00
6E.13.01.22.5F.C2.77.00
6D.FF.FE.EF.FF.FF.00.00
:
0001h
0002h
0003h
:
1001h
1002h
1003h
:
Table 3-11. Memory Cells of Chip 3
Address
Data
Address
1000h
Mask
FF.FF.FF.FF.FF.FF.FF.00
FF.FF.FF.FF.FF.FF.00.00
FF.FF.FF.FF.FF.FF.00.00
FF.FF.FF.FF.FF.FF.00.00
:
0000h
0001h
0002h
0003h
:
6E.13.01.22.5F.C2.AA.00
6E.13.01.22.5F.C2.00.00
6E.13.01.22.5F.BF.00.00
6E.13.01.22.61.01.00.00
:
1001h
1002h
1003h
:
3.2.4 Other points to be noted
• Do not change the mode by using the MEM, FULL, and FMSK pins in a mode that operates with two or more clock
cycles. Similarly, do not change A12 to A0.
Remark Modes that operate with two or more clock cycles
In normal mode: Longest Prefix Match mode
In FF mode:
Memory/register read, Full Match mode, Full Match with Mask mode, and Longest
Prefix Match mode
• Write to the NOP register for one or more clocks when changing the operation and the search mode.
• Create an external circuit in which RESET_B becomes low after power application.
• After releasing reset, input at least 2 CLK or more NOP commands continuously.
• When a search operation is stopped temporarily using CE (CE_B) during a continuous search operation, almost
the same power is consumed as during a search operation. In this case, shift into no-operation mode by writing to
the NOP register or inserting a wait.
• When performing a continuous search operation in the normal mode, make the total search frequency 66% or
below.
19
Data Sheet S13650EJ5V0DS
µPD98421
•
Cautions when connecting multiple µPD98421s
The output load capacitance in the AC characteristics described later is 50 pF, so if the load capacitance exceeds
50 pF through the connection of multiple devices, the delay amount shown in the figure below must be added as
an output delay.
Reference this delay value when designing external circuits. The delay value in the figure is only that of the
output buffer. Note also that the level at which output of the delay value is determined is VIH (2.0 V) for the rising
delay and VIL (0.8 V) for the falling delay.
Output Buffer Load Dependence (typ.) @ Rising Delay
5.00E-09
4.50E-09
4.00E-09
3.50E-09
3.00E-09
2.50E-09
2.00E-09
1.50E-09
1.00E-09
5.00E-10
0.00E+00
0
25
50
75
100
125
150
Load exceeding 50 pF [pF]
Output Buffer Load Dependence (typ.) @ Falling Delay
5.00E-09
4.50E-09
4.00E-09
3.50E-09
3.00E-09
2.50E-09
2.00E-09
1.50E-09
1.00E-09
5.00E-10
0.00E+00
0
25
50
75
100
125
150
Load exceeding 50 pF [pF]
20
Data Sheet S13650EJ5V0DS
µPD98421
4. ELECTRICAL SPECIFICATIONS
All the rated values below are when the µPD98421 is cooled at a wind velocity of 2 m/s.
Absolute Maximum Ratings
Parameter
Supply voltage
Symbol
VDD
VI
Conditions
Rating
–0.5 to +4.6
Unit
V
Input voltage
I/O voltage
–0.5 to +VDD + 0.5
–0.5 to +VDD + 0.5
0 to 70
V
VIO
V
Operating ambient
temperature
TA
°C
Storage temperature
Tstg
–65 to +150
°C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Conditions
Parameter
Supply voltage
Symbol
VDD
Conditions
MIN.
3.15
2.0
2.4
0
TYP.
3.3
MAX.
3.45
VDD
VDD
0.8
Unit
V
Input voltage, high
VIH1
VIH2
VIL1
Other than CLK, RESET_B
CLK, RESET_B
V
V
Input voltage, low
Other than CLK, RESET_B
CLK, RESET_B
V
VIL2
0
0.4
V
Operating ambient
temperature
TA
Cooled at a wind velocity of 2 m/s or
more
0
70
°C
DC Characteristics (TA = 0 to +70°C, VDD = 3.3 V 0.15 V)
Parameter
Output voltage, high
Output voltage, low
Operating current
Symbol
VOH
Conditions
MIN.
2.4
TYP.
MAX.
Unit
V
IOH = –4.0 mA
VOL
IOL = 8.0 mA
0.4
1150
1150
10
V
Note
fclk = 33 MHz (normal mode)
fclk = 50 MHz (FF mode)
VI = 0 V to VDD
mA
mA
µA
µA
IDD
Input leakage current
Output leakage current
ILI
ILO
VIO = 0 V to VDD
10
Output: not selected
Pull-up resistance (HAD
and SMD pins)
RPU
VI = 0 V
25
50
150
kΩ
Note When performing a continuous search operation in the normal mode, make the total search frequency 66%
or below.
21
Data Sheet S13650EJ5V0DS
µPD98421
Capacitance
Parameter
Symbol
CIN
Conditions
VIN = 0 V, f = 1 MHz
MIN.
TYP.
MAX.
10
Unit
pF
Input capacitance
Output capacitance
I/O capacitance
COUT
CI/O
VIN = 0 V, f = 1 MHz
VIN = 0 V, f = 1 MHz
10
pF
10
pF
AC Characteristics (TA = 0 to 70°C, VDD = 3.3 V 0.15 V)
All the values below are at an output load capacitance of 50 pF.
CLK input
Parameter
CLK cycle time
Symbol
tCYCLK
Conditions
MIN.
30
20
13
9
TYP.
MAX.
125
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Normal mode
FF mode
125
CLK high-level width
CLK low-level width
tCLKH
Normal mode
FF mode
tCLKL
Normal mode
FF mode
13
9
CLK rise time
CLK fall time
tCLKR
tCLKF
3
3
t
CLKR
t
CLKF
2.4 V (MIN.)
2.4 V
1.5 V
V
PPCLK
0.4 V
0.4 V (MAX.)
t
CLKH
t
CLK
t
CYCLK
RESET input
Parameter
Symbol
tWRSTL
Conditions
MIN.
tCYCLK × 2
TYP.
MAX.
Unit
ns
RESET_B low-level width
22
Data Sheet S13650EJ5V0DS
µPD98421
CE and CE_B operations
Parameter
Symbol
tDCEDATA
Conditions
MIN.
TYP.
MAX.
10
Unit
ns
CE ↑ → DATA valid time
CE_B ↓ → DATA valid time
CE ↑ → HAD valid time
CE_B ↓ → HAD valid time
CE ↑ → ERR_B valid time
CE_B ↓ → ERR_B valid time
CE ↑ → SMD valid time
CE_B ↓ → SMD valid time
CE ↓ → DATA float time
CE_B ↑ → DATA float time
CE ↓ → HAD float time
CE_B ↑ → HAD float time
CE ↓ → ERR_B float time
CE_B ↑ → ERR_B float time
CE ↓ → SMD float time
CE_B ↑ → SMD float time
tDCEHAD
tDCEERR
tDCESMD
tFCEDATA
tFCEHAD
tFCEERR
tFCESMD
10
10
10
10
10
10
10
ns
ns
ns
ns
ns
ns
ns
23
Data Sheet S13650EJ5V0DS
µPD98421
Search/memory operations (1/2)
Parameter
Address setup time
Address hold time
Data setup time
Symbol
tSA
Conditions
MIN.
4
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tHA
4
tSDATA
tHDATA
tSCE
4
Data hold time
4
CE, CE_B setup time
CE, CE_B hold time
MEM setup time
4
tHCE
3
tSMEM
tHMEM
tSWE
3
MEM hold time
3
WE_B setup time
3
WE_B hold time
tDWE
3
WAIT_B setup time
WAIT_B hold time
FULL, FMSK setup time
FULL, FMSK hold time
Delay time from CLK ↑ to DATA
tSWAIT
tHWAIT
tSMODE
tHMODE
tDDATA
3
3
4
3
Normal mode
26
10
FF mode
CLK ↑ → DATA invalid time
WE_B ↑ → DATA valid time
WE_B ↓ → DATA float time
OE_B ↓ → DATA valid time
OE_B ↑ → DATA float time
ENHIT_B ↓ → HAD valid time
ENHIT_B ↑ → HAD float time
ENHIT_B ↓ → ERR_B valid time
ENHIT_B ↑ → ERR_B float time
CLK ↑ → HAD valid time
tDDATAX
tDWEDATA
tFWEDATA
tDOEDATA
tFOEDATA
tDEHHAD
tFEHHAD
tDEHERR
tFEHERR
tDHAD
Normal mode
4
10
10
10
10
10
10
10
10
26
10
26
10
Normal mode
FF mode
CLK ↑ → HAD float time
tFHAD
Normal mode
FF mode
CLK ↑ → HAD invalid time
CLK ↑ → HIT_B delay time
tDHADX
tDHIT
5
5
Normal mode
FF mode
26
10
CLK ↑ → HIT_B invalid time
CLK ↑ → ERR_B valid time
tDHITX
tDERR
Normal mode
FF mode
26
10
26
10
CLK ↑ → ERR_B float time
tFERR
Normal mode
FF mode
CLK ↑ → ERR_B invalid time
tDERRX
tSSMD
5
2
SMD setup time
24
Data Sheet S13650EJ5V0DS
µPD98421
Search/memory operations (2/2)
Parameter
SMD hold time
Symbol
tHSMD
Conditions
MIN.
3
TYP.
MAX.
Unit
ns
Note
CLK ↑ → SMD low-level valid time
Normal mode
26
10
12
ns
tDSMDL1
FF mode
ns
Note
CLK ↓ → SMD low-level valid time
Normal mode
ns
tDSMDL2
CLK ↓ → SMD high-level valid time
CLK ↑ → SMD high-level valid time
CLK ↑ → SMD float time
tDSMDH1
tDSMDH2
tFSMD
Normal mode
FF mode
2
2
2
13
10
10
ns
ns
ns
Note The
SMD low-level valid time satisfies either the tDSMDL1 or tDSMDL2 value.
(1) Memory access (normal mode)
tCYCLK
tCLKH
tCLKL
CLK
tSA
tHA
Memory write
Memory write
Memory write
Memory read
address 1
Memory read
address 2
A[12:0]
NOP
NOP
address 1
address 2
address 3
Memory read data 1
Memory read data 2
tSDATA
tHDATA
Memory write
data 1
Memory write
data 2
Memory write
data 3
DATA[63:0]
CE_B
tDDATAX
tDDATA
tDCEDATA
tDDATA
tSCE
tHCE
CE has timing identical to CE_B.
tFCEDATA
tHMEM
MEM
tSMEM
tSWE tHWE
tFWEDATA
WE_B
OE_B
tDWEDATA
tDOEDATA
tFOEDATA
tSWAIT tHWAIT
WAIT_B
FULL,FMSK
tFEHHAD
tFCEHAD
tDEHHAD
tDCEHAD
HAD[12:0]
HIT_B
tFEHERR
tFCEERR
tDEHERR
tDCEERR
Hi-Z
ERR_B
ENHIT_B
SMD[63:0]
Hi-Z
Remark CE is the inversion of CE_B.
25
Data Sheet S13650EJ5V0DS
µPD98421
(2) Memory access (FF mode)
tCYCLK
tCLKH
tHA
tCLKL
CLK
A[12:0]
DATA[63:0]
CE_B
tSA
Memory write
address 1
Memory write
address 2
Memory write
address 3
Memory read
address 1
NOP
NOP
tSDATA
tHDATA
Memory write
data 1
Memory write
data 2
Memory write
data 3
Memory read data 1
tDDATA
tSCE
tHCE
CE has timing identical to CE_B.
tHMEM
MEM
tSMEM
tSWE tHWE
tFWEDATA
WE_B
tDWEDATA
OE_B
tSWAIT tHWAIT
WAIT_B
FULL,FMSK
HAD[12:0]
tFEHHAD
tFCEHAD
tDEHHAD
tDCEHAD
HIT_B
tFEHERR
tFCEERR
tDEHERR
tDCEERR
Hi-Z
ERR_B
ENHIT_B
SMD[63:0]
Hi-Z
Remark CE is the inversion of CE_B.
26
Data Sheet S13650EJ5V0DS
µPD98421
(3) I/O access (normal mode)
tCYCLK
tCLKH
tCLKL
CLK
A[12:0]
tSA
tHA
I/O write
address 2
I/O write
address 3
I/O write
address 1
I/O read
address 1
I/O read
address 2
NOP
NOP
I/O read data 1
I/O read data 2
tSDATA
tHDATA
I/O write
data 1
I/O write
data 2
I/O write
data 3
DATA[63:0]
CE_B
tDDATAX
tDDATA
tDCEDATA
tDDATA
tSCE
tHCE
CE has timing identical to CE_B.
tFCEDATA
tHMEM
MEM
tSMEM
tSWE tHWE
tFWEDATA
WE_B
tDWEDATA
tDOEDATA
tFOEDATA
OE_B
WAIT_B
tSWAIT tHWAIT
FULL,FMSK
HAD[12:0]
HIT_B
tFEHHAD
tFCEHAD
tDEHHAD
tDCEHAD
tFEHERR
tFCEERR
tDEHERR
tDCEERR
Hi-Z
ERR_B
ENHIT_B
Hi-Z
SMD[63:0]
Remark CE is the inversion of CE_B.
27
Data Sheet S13650EJ5V0DS
µPD98421
(4) I/O access (FF mode)
tCYCLK
tCLKH
tCLKL
CLK
A[12:0]
tSA
tHA
I/O write
address 1
I/O write
I/O write
I/O read
address 1
NOP
NOP
address 2
address 3
tSDATA
tHDATA
I/O read
data 1
I/O write
data 2
I/O write
data 3
I/O write
data 1
DATA[63:0]
CE_B
tDDATA
tSCE
tHCE
CE has timing identical to CE_B.
tHMEM
MEM
tSMEM
tSWE tHWE
tFWEDATA
WE_B
tDWEDATA
OE_B
tSWAIT tHWAIT
WAIT_B
FULL,FMSK
HAD[12:0]
HIT_B
tFEHHAD
tFCEHAD
tDEHHAD
tDCEHAD
tFEHERR
tFCEERR
tDEHERR
tDCEERR
Hi-Z
ERR_B
ENHIT_B
SMD[63:0]
Hi-Z
Remark CE is the inversion of CE_B.
28
Data Sheet S13650EJ5V0DS
µPD98421
(5) Full Match search (normal mode)
tCYCLK
tCLKH
tCLKL
CLK
A[12:0]
tSA
tHA
00H
NOP
tSDATA
tHDATA
Search
data 1
Search
data 2
Search
data 3
Search
data 4
Search
data 5
Search
data 6
Search
data 7
DATA[63:0]
CE_B
Low
CE has timing identical to CE_B.
tHMEM
tSMEM
MEM
tSWE tHWE
WE_B
High
OE_B
tSWAIT tHWAIT
WAIT_B
FULL,FMSK
HAD[12:0]
HIT_B
tSMODE
tHMODE
Full match search mode
tFHAD
tDEHHAD
tDHAD
tDHAD
tDHITX
Hit
address 1
Hit
Hit
address 6
Hit
address 7
address 5
tFEHHAD
tDHIT
tDHADX
tDERR
tFEHERR
tDEHERR
Hi-Z
tFEERR
Hi-Z
ERR_B
ENHIT_B
SMD[63:0]
tDERRX
Hi-Z
Remark CE is the inversion of CE_B.
29
Data Sheet S13650EJ5V0DS
µPD98421
(6) Full Match search with Mask (normal mode)
tCYCLK
tCLKH
tCLKL
CLK
A[12:0]
tSA
tHA
00H
NOP
tSDATA
tHDATA
Search
data 1
Search
data 2
Search
data 3
Search
data 4
Search
data 5
Search
data 6
Search
data 7
DATA[63:0]
CE_B
Low
CE has timing identical to CE_B
tHMEM
tSMEM
MEM
tSWE tHWE
WE_B
High
OE_B
tSWAIT tHWAIT
WAIT_B
FULL,FMSK
HAD[12:0]
HIT_B
tSMODE
tHMODE
Full match with mask
tFHAD
tDEHHAD
tDHAD
tDHAD
tDHITX
Hit
address 1
Hit
Hit
address 6
Hit
address 7
address 5
tFEHHAD
tDHIT
tDHADX
tDERR
tFEHERR
tDEHERR
Hi-Z
tFEERR
Hi-Z
ERR_B
ENHIT_B
SMD[63:0]
tDERRX
Hi-Z
Remark CE is the inversion of CE_B.
30
Data Sheet S13650EJ5V0DS
µPD98421
(7) Longest Prefix Match search (normal mode)
tCYCLK
tCLKH
tCLKL
CLK
tSA
tHA
00H
NOP
A[12:0]
tSDATA
tHDATA
Search
data 1
Search
data 1
Search
data 1
DATA[63:0]
CE_B
MEM
Low
CE has timing identical to CE_B.
tHMEM
tSMEM
tSWE tHWE
WE_B
High
OE_B
tSWAIT tHWAIT
WAIT_B
FULL,FMSK
HAD[12:0]
HIT_B
tSMODE
tHMODE
Longest prefix match search mode
tFHAD
tDHAD
tDHAD
Hit
address 1
tDHITX
tDHADX
tDHIT
tDERR
tFEERR
Hi-Z
ERR_B
tDERRX
Low
ENHIT_B
tDSMDH tFSMD
tFSMD
tDSMDL2
Hi-Z
All high
All high
SMD[63:0]
temp data 1
temp data 2
temp data 3
tDSMDL1
Remark CE is the inversion of CE_B.
31
Data Sheet S13650EJ5V0DS
µPD98421
(8) Full Match search (FF mode)
tCYCLK
tCLKH
tCLKL
CLK
A[12:0]
tSA
tHA
00H
NOP
tSDATA
tHDATA
Search
data 1
Search
data 2
Search
data 3
Search
data 4
DATA[63:0]
CE_B
Low
CE has timing identical to CE_B.
tHMEM
tSMEM
MEM
tSWE tHWE
WE_B
High
OE_B
tSWAIT tHWAIT
WAIT_B
FULL,FMSK
HAD[12:0]
HIT_B
tSMODE
tHMODE
Full match search mode
tFHAD
tDHAD
tDHAD
Hit
address 1
tDHITX
tDHIT
tDHADX
tDERR
tFEERR
Hi-Z
ERR_B
ENHIT_B
SMD[63:0]
tDERRX
Low
Hi-Z
Remark CE is the inversion of CE_B.
32
Data Sheet S13650EJ5V0DS
µPD98421
(9) Full Match search with Mask (FF mode)
tCYCLK
tCLKH
tCLKL
CLK
A[12:0]
tSA
tHA
00H
NOP
tSDATA
tHDATA
Search
data 1
Search
data 2
Search
data 3
Search
data 4
DATA[63:0]
CE_B
Low
CE has timing identical to CE_B.
tHMEM
tSMEM
MEM
tSWE tHWE
WE_B
High
OE_B
tSWAIT tHWAIT
WAIT_B
FULL,FMSK
HAD[12:0]
HIT_B
tHMODE
tSMODE
Full match with mask search mode
tFHAD
tDHAD
tDHAD
Hit
address 1
tDHITX
tDHIT
tDHADX
tDERR
tFEERR
Hi-Z
ERR_B
ENHIT_B
SMD[63:0]
tDERRX
Low
Hi-Z
Remark CE is the inversion of CE_B.
33
Data Sheet S13650EJ5V0DS
µPD98421
(10) Longest Prefix Match search (FF mode)
tCYCLK
tCLKH
tCLKL
CLK
A[12:0]
tSA
tHA
00H
NOP
tSDATA
tHDATA
Search
data 1
DATA[63:0]
CE_B
Low
CE has timing identical to CE_B.
tHMEM
tSMEM
MEM
tSWE tHWE
WE_B
High
OE_B
tSWAIT tHWAIT
WAIT_B
FULL,FMSK
HAD[12:0]
HIT_B
tSMODE
t
HMODE
Longest prefix match
search mode
tFHAD
tDHAD
Hit
address 1
tDHADX
tDHIT
tFEERR
Hi-Z
ERR_B
Low
ENHIT_B
tFSMD
tFSMD
tDSMDH
Hi-Z
All high
SMD[63:0]
temp data 1
tDSMDL1
Remark CE is the inversion of CE_B.
34
Data Sheet S13650EJ5V0DS
µPD98421
(11) Full Match search (normal mode, insertion wait)
tCYCLK
tCLKH
tCLKL
CLK
A[12:0]
tSA
tHA
00H
NOP
tSDATA
tHDATA
Search
data 1
Search
data 2
Search
data 3
Search
data 4
DATA[63:0]
CE_B
Low
CE has timing identical to CE_B.
tHMEM
tSMEM
MEM
tSWE tHWE
WE_B
High
OE_B
tSWAIT tHWAIT
WAIT_B
tSMODE
tHMODE
FULL,FMSK
Full match search mode
tFHAD
tDHAD
tDHAD
tDHAD
tDHITX
Hit
address 1
Hit
address 1
HAD[12:0]
HIT_B
tDHIT
tDHADX
tDERR
tFEERR
Hi-Z
tFEERR
ERR_B
ENHIT_B
SMD[63:0]
tDERRX
Low
Hi-Z
Remark CE is the inversion of CE_B.
35
Data Sheet S13650EJ5V0DS
µPD98421
(12) Longest Prefix Match search (normal mode, insertion wait)
tCYCLK
tCLKH
tCLKL
CLK
tSA
tHA
A[12:0]
00H
NOP
tSDATA
tHDATA
Search
data 1
Search
data 2
DATA[63:0]
CE_B
Low
CE has timing identical to CE_B.
tHMEM
tSMEM
MEM
tSWE tHWE
WE_B
High
OE_B
tSWAIT tHWAIT
WAIT_B
FULL,FMSK
HAD[12:0]
HIT_B
tSMODE
tHMODE
Longest prefix match search mode
tDHAD
tDHADX
tDHAD
Hit
address 1
Hit
address 2
tDHADX
tDHIT
tDHIT
tFEERR
Hi-Z
ERR_B
ENHIT_B
SMD[63:0]
Low
tFSMD
tDSMDH
tFSMD
tDSMDL2
Hi-Z
All high
All high
temp data 1
temp data 2
tDSMDL1
Remark CE is the inversion of CE_B.
36
Data Sheet S13650EJ5V0DS
µPD98421
(13) Search → Memory access → Search (normal mode)
tCYCLK
tCLKH
tHA
tCLKL
CLK
tSA
Memory write
address 1
NOP
00H
A[12:0]
00H
NOP
00H
NOP
tSDATA
tHDATA
Search
data 1
Search
data 2
Memory
data 1
Search
data 3
DATA[63:0]
CE_B
Low
CE has timing identical to CE_B.
tHMEM
tSMEM
MEM
tSWE tHWE
WE_B
High
OE_B
tSWAIT tHWAIT
WAIT_B
FULL,FMSK
HAD[12:0]
HIT_B
tSMODE
t
HMODE
Full match
Longest prefix
search mode
Full match
with mask
search mode
tDHAD
Hit
address 1
Hit
address 2
tDHIT
tDHADX
Hi-Z
tFEERR
ERR_B
Low
ENHIT_B
Hi-Z
All high
SMD[63:0]
temp data 1
Remark CE is the inversion of CE_B.
37
Data Sheet S13650EJ5V0DS
µPD98421
5. RECOMMENDED SOLDERING CONDITIONS
The µPD98421 should be soldered and mounted under the following recommended conditions. For details of the
recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual
(C10535E).
For soldering methods and conditions other than those recommended below, contact your NEC sales
representative.
Surface-mount type
•
µPD98421F1-GA1: 240-pin plastic FBGA (16 × 16)
Recommended
Soldering Method
Infrared reflow
Soldering Conditions
Condition Symbol
Package peak temperature: 230°C, Time: 30 seconds max. (at 210°C or higher),
Count: Two times or less, Exposure limit: 3 daysNote (after that, prebake at
125°C for 10 hours)
IR30-103-2
Note After opening a dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
38
Data Sheet S13650EJ5V0DS
µPD98421
6. PACKAGE DRAWING
240-PIN PLASTIC FBGA (16x16)
D
w
S
B
B
D
1
ZE
A
ZD
SD
18
17
16
15
14
13
12
11
10
9
E
1
E
8
SE
7
6
5
4
3
2
1
VUTRPNMLKJHGFEDCBA
4-C1.0
w
Index mark
4-R0.3MAX.
S
A
A
A2
25°
y
1
S
S
e
y
S
A1
φ
x
M
240- b
S
A B
φ
ITEM MILLIMETERS
16.00 0.10
15.4
D
D
E
E
w
e
1
1
16.00 0.10
15.4
0.20
0.80
A
1.31 0.15
0.35 0.10
0.96
A
A
1
2
+0.05
0.50
b
−0.10
x
y
y
0.08
0.10
1
0.20
SD
SE
ZD
ZE
0.40
0.40
1.2
1.2
P240F1-80-GA1
39
Data Sheet S13650EJ5V0DS
µPD98421
[MEMO]
40
Data Sheet S13650EJ5V0DS
µPD98421
[MEMO]
41
Data Sheet S13650EJ5V0DS
µPD98421
[MEMO]
42
Data Sheet S13650EJ5V0DS
µPD98421
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
43
Data Sheet S13650EJ5V0DS
µPD98421
•
The information in this document is current as of January, 2002. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
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