RT2910A_技术文档

RT2910A

High Efficiency Inverting PWM Converter with Surge Stopper

General Description

Features

 HV Switch Driver

The RT2910A is a PWM inverting converter integrates

HV (High Voltage) Switch Driver. The HV switch driver

protects loads from high voltage transients. It regulates

the output during an over-voltage event, by controlling

the Gate of an external N-MOSFET. The output is

limited to a safe value thereby allowing the loads to

continue functioning. The RT2910A also monitors the

voltage drop between the VHV and SNS pins to protect

against over-current faults. An internal amplifier limits

the current sense voltage to 50mV. If the fault condition

persists, the MOSFET is turned off. After a certain

cooling off period, the gate is allowed to go up and turn

on the MOSFET again. Moreover, the HV switch driver

also can support back to back FETs application to

prevent reverse leakage current from output.

► Adjustable Output Clamp Voltage

► Over-Current Protection

► Wide Operation Range : 5V to 60V

► Reverse Input Protection to −60V

► Adjustable Fault Timer

► Support N-MOSFET

 Inverting PWM Converter

► 12.5V to 0.5V Output

► Integrate High-Side P-MOSFET

► 300kHz to 800kHz Switching Frequency

► Current-Mode PWM Control

► Internal Soft-Start

► Power Ok Indicator

Applications

The high-efficiency PWM inverting converter allows

designers to implement compact, low noise, negative

output DC-DC converters. This device operates from

+4V to +7V input voltage and generates 500mV to

12.5V output. To minimize switching noise, it features

a current-mode, constant frequency PWM control

scheme. The operating frequency can be set from

300kHz to 800kHz through a resistor.

 Ga-N MOSFET Bias

 Positive to Negative Conversion

 Industrial and Telecom Power Supplies

 Distributed Power System

Simplified Application Circuit

VHV

V

OUT

GATE

SNS

VHV

OUT

FB

RT2910A

V

VIN

IN

LX

NV

OUT

VB

RT

CS

COMP

PGND

NFB

FDLY

VL

SFB

VREF

TMR

5VDET

ENHV

POK

GND

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RT2910A

Marking Information

Ordering Information

RT2910A

RT2910AGQW : Product Number

YMDNN : Date Code

Package Type

QW : WQFN-24L 5x5 (W-Type)

RT2910A

GQW

YMDNN

Lead Plating System

G : Green (Halogen Free and Pb Free)

Note :

Richtek products are :

 RoHS compliant and compatible with the current

requirements of IPC/JEDEC J-STD-020.

 Suitable for use in SnPb or Pb-free soldering processes.

Pin Configuration

(TOP VIEW)

24 23 22 21 20 19

1

2

3

4

5

6

18

17

16

15

14

13

NFB

SFB

PGND

CS

VL

GND

TMR

ENHV

VHV

SNS

GND

LX

25

LX

7

8

9

10 11 12

WQFN 5x5 24L

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RT2910A

Functional Pin Description

Pin No.

Pin Name

Pin Function

Feedback voltage input. The feedback for inverting output threshold is 0.6V for

PWM inverting converter.

1

NFB

Secondary feedback voltage input. For adjusting POK threshold of Inverting.

NV_OUTfor PWM inverting converter.

2

SFB

3

4

PGND

CS

Negative rail for driver and negative current sense input. Connected to GND.

Positive current sense input for PWM inverting converter.

Switch node for PWM inverting converter.

5, 6

7, 8

9

LX

VIN

Power supply input for inverting PWM controller for PWM inverting converter.

Voltage level keeper. Connect a 0.1F ceramic capacitor to VIN.

Voltage regulation feedback input for HV switch driver.

Output voltage sense input for HV switch driver.

VB

10

11

12

13

14

15

FB

OUT

GATE

SNS

VHV

ENHV

N-MOSFET gate drive output for HV switch driver.

HVIN current sense input for HV switch driver.

Positive supply voltage input for HV switch driver.

Enable control input for HV switch driver.

Fault timer setting for HV switch driver. Connect a 22nF at least ceramic

capacitor to GND. There is a 3ms sense blanking time after POK pull high.

16

TMR

GND

VL

17,

Ground. The exposed PAD must be soldered to a large PCB and connected to

GND for maximum power dissipation.

25 (Exposed Pad)

Low dropout regulator output for PWM inverting converter. Connect a ceramic

capacitor from VL to GND. The capacitor value range from 0.47F to 1F.

Logic output. Active high when SFB voltage is lower than its threshold and FDLY

is higher than 1.25V. This pin can be used as HV swap controller enable control

for PWM inverting converter.

18

19

POK

Delay set input for PWM inverting converter. There is an internal 10A from VL

after V_TMRhigher than 0.6V threshold. POK is low during FDLY charge time.

Connect a ceramic capacitor to GND for setting Fault delay time.

20

FDLY

21

22

5VDET

COMP

VIN detection set input. For PWM Inverting Converter.

Compensation node for error amplifier for PWM inverting converter.

Oscillator frequency setting for PWM inverting converter. Connect a resistor to

GND for adjusting switching frequency from 300kHz to 800kHz.

23

24

RT

1.25V reference output. Bypass only with a 0.1F ceramic capacitor from VREF

to GND for PWM inverting converter.

VREF

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RT2910A

Functional Block Diagram

VHV SNS

GATE

OUT

FB

Current

Limit

+

-

1.25V

VHV

-

+

CP_EN

ENHV

TMR

-

+

0.6V

+

-

VIN

VL

Control

Circuitry

1.4V

LDO

LX

VB

RT

CS

+

OC

VREF

Reference

PGND

-

100mV

0.6V

COMP

NFB

VL

+

-

10µA

+

-

FDLY

POK

+

-

SFB

1.25V

5VDET

+

-

Fault

1V

TMR

0.6V

+

-

1µA

GND

Operation

HV Power-Switch

OUT pin to ground and the internal 1.25V reference. If

the over-voltage/current is detected, a current source

starts charging up the capacitor connected at the TMR

pin to ground .The pass transistor stays on until the

TMR pin reaches 1.45V, at which point the GATE pin

pulls low turning off the N-MOSFET.

The HV power switch embedded an over-voltage

protection regulator that drives an external N-MOSFET

only as the pass transistor. It can operate within a wide

supply voltage range from 5V to 60V. The internal

charge pump turns on the N-MOSFET to supply current

to the loads with very little power loss. This improves the

efficiency and increases the available supply voltage

level to the load circuitry. Normally, the pass transistor

is fully on, powering the loads with very little voltage

drop. When the supply voltage surges too high, the

Voltage Amplifier (VA) controls the Gate of the N-

MOSFET and regulates the voltage at the OUT pin to a

level that is set by the external resistive divider from the

The potential at the TMR pin starts decreasing as soon

as the over-voltage condition disappears. As the voltage

at the TMR pin reaches 0.5V, the GATE pin begins to

rise and turn on the MOSFET again.

The RT2910A senses an over-current condition by

monitoring the voltage across a sense resistor placed

between the VHV and SNS pins. An active current limit

circuit controls the GATE pin to limit the sense voltage

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DS2910A-00 August 2017

RT2910A

to 50mV. A current is generated to start charging up the

TMR pin when over current condition is detected. The

MOSFET is turned off when it reaches 1.45V.

reference voltage. Connect resistor between inductor

and PGND to set peak inductor current limit threshold.

5VDET pin is VIN detection. After soft-start beginning, if

5VDET pin above 1V and SFB pin less 0.6V POK will

pull high.

PWM Inverting Converter

PWM inverting converter can act a current mode non-

synchronous Buck-Boost converter to generated

negative output voltage, embedded an internal P-

MOSFET. The UVLO (under-voltage lockout) function

ensures PWM converter operates correctly with

If HV-Switch Over-current/Over-voltage is triggered, the

TMR pin will be charge. When V_TMRabove 0.6V. POK

will pull low immediately to turn off GATE.

At the same time, a 10A current source is charging the

FDLY capacitor. When the FDLY pin is a above 1.25V,

POK will pull high to turn on GATE again.

minimum VIN voltage. The VB regulator provides (V_IN



5V) voltage for circuit powered directly by VIN. Connect

a resistor from the RT pin to GND to set PWM switching

frequency between 300kHz to 800kHz. Current limit

comparator compares the CS pin voltage with 100mV

The PWM converter also provides Over Temperature

Protection (OTP).

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RT2910A

Absolute Maximum Ratings (Note 1)

 VHV, SNS to GND--------------------------------------------------------------------------- 60V to 85V

 ENHV to GND -------------------------------------------------------------------------------- 0.3V to 45V

 ENHV Input Current------------------------------------------------------------------------- 1mA

 OUT to GND ---------------------------------------------------------------------------------- 0.3V to 65V

 GATE to GND--------------------------------------------------------------------------------- 0.3V to (OUT+AMR(GATE to OUT))

 GATE to OUT --------------------------------------------------------------------------------- Note 5

 FB, TMR to GND----------------------------------------------------------------------------- 0.3V to 10V

 SFB, CS, VB, POK, FDLY, COMP, RT, VREF, NFB, VL to GND ----------------- 0.3V to 6V

 VIN, 5VDET to GND ------------------------------------------------------------------------ 0.3V to 8V

 LX to VIN--------------------------------------------------------------------------------------- 20V to 0.3V

 TMR, FB, OUT, GATE (Note 6) ------------------------------------------------------- 10mA

 Power Dissipation, PD @ TA = 25°C

WQFN-24L 5x5------------------------------------------------------------------------------- 3.57W

 Package Thermal Resistance

(Note 2)

WQFN-24L 5x5, _JA----------------------------------------------------------------------- 28°C/W

WQFN-24L 5x5, _JC----------------------------------------------------------------------- 7°C/W

 Lead Temperature (Soldering, 10 sec.) ----------------------------------------------- 260C

 Junction Temperature --------------------------------------------------------------------- 150C

 Storage Temperature Range ------------------------------------------------------------ 65C to 150C

 ESD Susceptibility

(Note 3)

CDM (Discharge Device Model)---------------------------------------------------------- 1kV

HBM (Human Body Model)---------------------------------------------------------------- 2kV

MM (Machine Model) ----------------------------------------------------------------------- 200V

Recommended Operating Conditions

(Note 4)

 HV Supply Input Voltage at VHV--------------------------------------------------------- 5V to 60V

 HV Output Voltage at OUT ---------------------------------------------------------------- 4.5V to 60V

 Supply Input Voltage at VIN--------------------------------------------------------------- 4V to 7V

 Inverting Output Voltage, NV_OUT--------------------------------------------------------- 12.5V to 0.5V

 Junction Temperature Range ------------------------------------------------------------- 40C to 125C

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RT2910A

Electrical Characteristics

(V_IN= V_ENHV= 5V, R_RT= 300k, C_REF= 0.1F, V_HV= 12V, T_J= 40°C to 125°C, unless otherwise specified)

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Hot Swap Regulator with Over-Voltage Protection

V_ENHV= 0V

V_ENHV= 5V (V_GATEV_OUT

--

7

25

5

A

VHV Supply Current

I_VHV

)

2.3

mA

GATE Output High Voltage

(Note 5)

V_GATE

I_{GATE_UP}

8V < V_HV< 80V (V_GATEV_OUT

)

10

12

16

V

V_GATE= 12V

15

30

40

70

60

GATE Pull-Up Current

A

V_GATE= V_HV= 48V

120

Over voltage, V_FB= 1.4V,

V_GATE= 12V

45

1

80

3

150

4

Over current, V_HV V_SNS

120mV, V_GATE= 12V

=

GATE Pull-Down Current

I_{GATE_DN}

mA

Shutdown mode, V_ENHV= 0V,

V_GATE= 12V

45

80

150

Output

FB Voltage

FB Input Current

V_FB

I_FB

V_GATE= 12V, V_OUT= 12V

V_FB= 1.25V

1.18

--

1.25

0.3

50

1.32

1

V

A

V_HV= 12V

V_HV V_SNS

40

38

--

58

56

--

Over Current Threshold

SNS Input Current

V_SNS

I_SNS

mV

V_HV= 48V

48

V_SNS= V_HV= 12V to 48V

V_SNS= V_HV= 12V

120

200

0.5

--

A

--

500

2

OUT Pin Input Current

I_OUT

V_OUT= V_HV= 12V, V_ENHV= 0V

V_HV= 12V to 48V

--

mA

V_{ENHV_H}

V_{ENHV_L}

I_ENHV

3

--

ENHV Input Voltage

ENHV Input Current

V

V_HV= 12V to 48V

--

0.5

--

V_ENHV= 3V

--

0.4

A

Sourcing, V_TMR= 1V, V_FB= 1.5V

or V_SNS= 60mV

Sinking, V_TMR= 1V, V_FB= 1V or

V_SNS= 0V

I_{TMR_SO}

I_{TMR_SI}

20

25

30

5

TMR Current

2.5

3.5

A

Inverting PWM Converter

VIN Supply Voltage Range

V_IN

I_VIN

4

--

7

V

V_NFB= 0.6V, V_IN> V_UVLO

V_COMP= 0V

,

VIN Supply Current

UVLO Threshold

--

0.75

1.5

mA

V_INrising

V_INfalling

No load

--

3.2

0.585

--

3.6

3.5

0.6

0.1

3.9

--

V_UVLO

V

NFB Threshold

V_NFB

I_NFB

0.615

--

V

NFB Input Current

V_NFB= 0.6V

A

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RT2910A

Parameter

Symbol

V_SFB

Test Conditions

SFB rising

Min

0.585

90

Typ

0.6

100

--

Max

0.615

110

Unit

V

SFB Threshold

Current Limit Threshold

V_CS

mV

V

Inverting Output Voltage Range NV_OUT

12.5

0.5

TMR Fault Detection

POK pull low, FDLY source

10A CURRENT

TMR Threshold

V_{TMR_FT}

--

0.6

3

--

V

TMR blank sensing after POK

High

TMR Sense Blank Time

V_{TMR_BLK}

ms

FDLY

FDLY Threshold

FDLY Output Current

Reference & LDO

VREF Output Voltage

VL Output Voltage

VL Load Regulation

Oscillator

V_FDLY

I_FDLY

Rising edge

--

1.25

10

--

V

A

V_REF

I_REF= 50A

1.225 1.25 1.275

V

V_VL

V_IN= 5V, I_VL= 0A

V_IN= 5V, 0 < I_VL< 2mA

3.85

--

4.25

4.65

V_{VL_Load}

20

60

mV

Oscillator Frequency

Maximum Duty

f_SW

R_RT= 300k

400

--

500

85

600

--

kHz

%

D_MAX

300kHz to 800kHz

5VDET

5VDET Threshold

R_DS(ON)& Thermal Shutdown

V_5VDET

Falling edge, hys = 50mV

V_IN= 5V, I_LX= 10mA

0.92

1

1.08

V

Internal P-MOSFET

On-Resistance

R_DS(ON)

--

80

120

--

m

Thermal Shutdown Temperature T_SD

150

°C

Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress

ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the

operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect

device reliability.

Note 2. _JAis measured under natural convection (still air) at T_A= 25C with the component mounted on a high effective-thermal-

conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard. _JCis measured at the exposed pad

of the package.

Note 3. Devices are ESD sensitive. Handling precaution is recommended.

Note 4. The device is not guaranteed to function outside its operating conditions.

Note 5. GATE to OUT voltage is internally generated and clamped. External driving at GATE pin is forbidden because it may

damage the device.

Note 6. All currents into device pins are positive, all currents out of device pins are negative. All voltages are referenced to GND

unless otherwise specified.

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RT2910A

Typical Application Circuit

2m

IPB027N10N3

12V to 48V

Output

R3

91k

820µF

0

10µF

12

V

IN

GATE

13

14

11

10

R4

2k

SNS

OUT

FB

1k

VHV

RT2910A

15

19

IPB027N10N3

ENHV

POK

CMSH5-20

10k

7, 8

4.5V to 7V

VIN

20μF

0.1μF

2N7002

NV

33k

9

VB

21

CDBB540-G

OUT

5VDET

5, 6

4

LX

-5V@1A

-10V@0.5A

2.2nF 10k

200k

15

10μH

47μF x 4

RT

CS

22

COMP

30m

2.2pF

3

1

200k

PGND

NFB

112k

3.3nF

20

FDLY

VL

112k

4.7μF

13k

2

SFB

18

13.7k

0.47μF

16

24

VREF

0.1μF

TMR

17,

22nF

6.8M

GND

25 (Exposed Pad)

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RT2910A

Typical Operating Characteristics

Inverting Power On from V

IN

V

= 5.5V , NVOUT = -5V , INVOUT = 0A

V

IN

= 5.5V , NVOUT = -5V , INVOUT = 1A

NVOUT

(5V/Div)

IN

NVOUT

(5V/Div)

5VDET

(1V/Div)

POK

5VDET

(1V/Div)

POK

(4V/Div)

PH

(4V/Div)

PH

(7V/Div)

Time (5ms/Div)

Time (2ms/Div)

Inverting Power Off from V

IN

V

= 5.5V , NVOUT = -5V , INVOUT = 0.1A

V

IN

= 5.5V , NVOUT = -5V , INVOUT = 1A

NVOUT

(5V/Div)

NVOUT

(5V/Div)

IN

5VDET

(1V/Div)

POK

(4V/Div)

PH

(4V/Div)

PH

(7V/Div)

Time (10ms/Div)

HV Switch Turn On from ENHV

Inverting Load Transient

V

= 55V , I

= 0A

OUT

V

= 5.5V , NVOUT = 5V , INVOUT = 0.1A to 1A

HV

IN

NVOUT

(2V/Div)

NVOUT

(100mV/Div)

GATE TO GND

INVOUT

(1A/Div)

(0V/Div)

OUT TO GND

(30V/Div)

ENHV

PH

(7V/Div)

(5V/Div)

Time (5ms/Div)

Time (1ms/Div)

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RT2910A

HV Switch Turn Off from ENHV

HV Switch Turn On from ENHV

V

= 55V , I

= 0A , INVOUT = 1A

OUT

V

= 55V , I

= 10A

OUT

HV

NVOUT

(5V/Div)

NVOUT

(2V/Div)

GATE TO GND

(50V/Div)

OUT TO GND

(30V/Div)

GATE TO GND

OUT TO GND

(30V/Div)

ENHV

(50V/Div)

ENHV

(5V/Div)

Time (1ms/Div)

Time (500s/Div)

HV Switch Turn Off from ENHV

HV Switch OCP

NVOUT

(5V/Div)

NVOUT

(5V/Div)

GATE TO GND

(50V/Div)

OUT TO GND

(30V/Div)

IIN

(10A/Div)

OUT TO GND

(50V/Div)

ENHV

(5V/Div)

V

= 55V , I

= 10A , INVOUT = 1A

V

= 55V , I

= 5A TO 10A , INVOUT = 1A

OUT

HV

OUT

HV

Time (500s/Div)

Efficiency vs. Output Current

HV Switch OVP

90

85

80

75

70

65

60

55

50

45

40

NVOUT

(5V/Div)

OUT TO GND

(50V/Div)

GATE TO OUT

(50V/Div)

ENHV

V

= 5.5V , NVOUT = 5V

IN

V

= 65V , I

= 0A , INVOUT = 1A

OUT

(5V/Div)

HV

0

0.2

0.4

0.6

0.8

1

1.2

Time (5ms/Div)

Output Current (A)

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RT2910A

Quiescent Current vs. Ambient Temperature

950

NVOUT vs. Output Voltage

5.019

5.018

5.017

5.016

5.015

5.014

5.013

5.012

5.011

5.010

5.009

900

850

800

750

T

= 105°C

= 25°C

A

T

A

700

650

600

550

T

A

= 40°C

V

= 5.5V , NVOUT = 5V

IN

V

= 5.5V , NVOUT = 5V

IN

0

0.2

0.4

0.6

0.8

1

1.2

4

5

6

7

8

Output Current (A)

Input Voltage (V)

NVOUT VS. Ambient Temperature

5.035

5.030

5.025

5.020

5.015

5.010

5.005

I

= 0A

OUT

I

= 0.5A

OUT

V

= 5.5V , NVOUT = 5V, T = 40°C to 105°C

A

IN

-50

-25

0

25

50

75

100

125

Ambient Temperature (°C)

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RT2910A

Application Information

The RT2910A is a PWM inverting converter integrates

HV power switch driver. Features of the inverting

converters include programmable constant switching

frequency, current mode topology with slope

compensation in case of sub-harmonic at over 50% duty

cycle operation , internal linear regulator , and internal

0.6V NFB reference with soft-start control allows output

voltage to be precisely regulated at adjustable output

voltage .Protection features include adjustable current

limit and over-temperature protection.

V_{OUT_OVP}= 1.25 x (1 + R3 / R4)

Where, R3 and R4 are the voltage divider from VOUT

to GND with the divider center node connected to FB

pin.

Over-Current Protection

The RT2910A features an adjustable current limit that

protects against short circuits or excessive load current.

During an over-current event, the GATE pin is regulated

to limit the current sense voltage between the VHV and

SNS pins to 50mV. The current limit is set by the

following equation:

The HV power switch is suited for hot swap applications

as an over-voltage protection regulator with

programmable current limit threshold equals 50mV that

drives an external N-MOSFET as the pass transistor. It

features a TMR function for over-voltage protection and

over-current protection to avoid N-Channel MOSFET

damaged.

I_LIM= 50mV/R_SNS

An over-current fault occurs when the current limit

circuitry has been engaged for longer than the time-out

delay set by the TMR pin timer capacitor. The GATE pin

is then immediately pulled low to GND turning off the

MOSFET.

It operates from a wide supply voltage range of 5V to

60V. The internal charge pump circuit is included to turn

on the N-Channel MOSFET to supply current to the

loads with very little power loss.

Fault Timer

The RT2910A includes an adjustable fault timer pin.

Connecting a capacitor from the TMR pin to ground sets

the delay timer period before the MOSFET is turned off.

The same capacitor also sets the cool off period before

the MOSFET is allowed to turn back on after the fault

condition has disappeared. The TMR pin should be tied

to ground if this feature is not used.

HV Power Switch Driver

Over-Voltage Protection

The RT2910A is equipped with over-voltage protection

(OVP) function. When the voltage at FB pin exceeds a

threshold of approximate 1.25V, the MOSFET is turned

off. The MOSFET can be turned on again once the

voltage at FB pin drops below 1.25V

Once a fault condition, either over-voltage or over-

current event, is detected, a current source charges up

the TMR capacitor. The timer charge up current is fixed

around 25A. When the voltage at the TMR pin,

reaches the 0.6V threshold,

During this period, the N-MOSFET is still on, and

continues to supply current to the load. This allows

uninterrupted operation during short over-voltage

transient events. When the voltage regulation loop is

engaged for longer than the time-out period, set by the

timer capacitor connected from the TMR pin to ground,

the GATE pin is pulled low to turn off the MOSFET. This

prevents the N-MOSFET from being damaged during a

long period of over-voltage. The OVPvoltage can be set

by the following equation:

1. POK pin is pulled low.

2. The ENHV pin is pulled low.

3. The V_{GATE_OUT}is pulled low.

4. C_FDLYstart to charge , when V_TMRdrop to 0.2V.

5. POK pin is pulled high again.

The fault sequence is as Figure 1.

is a registered trademark of Richtek Technology Corporation.

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13

RT2910A

 gate threshold (for lower VIN applications)

OCP/OVP

Trigger Signal

0.6V

For most of the time the MOSFET will be fully on. In that

state, the voltage loss and power dissipation are a

simple matter of R_DS(ON)and current. Choose a device

that doesn’t drop more voltage than is acceptable

considering the minimum value the intended input

voltage and the voltage requirements of the load, and

one that can handle the required continuous current.

Avoid logic-level MOSFETs with their low VGS

maximum ratings, or add a GATE-VOUT clamp to avoid

damaging. The RT2910A GATE drive voltage may be

as high as 14V so standard-threshold MOSFETs with

20V VGS ratings are recommended.

0.2V

V

TMR

V

GATE to OUT

V

POK

1.25V

V

FDLY

When the MOSFET is turned off (whether in shutdown

or in OVP or OCP) the full input voltage appears across

the MOSFET. Choose a MOSFET with a maximum

drain-source voltage exceeding your maximum input

surge voltage.

Figure 1. OCP/OVP Fault Sequence

If the fault condition persist, fault sequence as Figure 2.

C_FDLYis charge to 1.25V POK (ENHV) , GATE pull high.

HV switch is operation, but fault condition is still exist,

C_TMRis charge to 1.45V within 3ms TMR blank time.

POK (ENHV) , GATE pull low again. C_TMRis discharge

by 3.5uA until 3ms time out. Because POK (ENHV) pull

low, so V_TMRis discharged to 0.2V, C_FDLYstart charge

again.

During an over-voltage (OV) event the MOSFET will

linear regulate the output voltage delivered to the load.

According to the timing determined by the capacitor

connected at the TMR pin, the circuit will turn the load

on and off periodically until the over-voltage ends. While

linear-regulating, the MOSFET will dissipate power and

heat up. Since TMR charges at twice the rate that it

discharges, the MOSFET will linear regulate with a duty

cycle of about 12% during a long continuous OV event.

If the OV event is shorter than the TMR charge timing

then examine the MOS ET’s safe operating area (SOA)

graph, using (V_HV– V_OUT) for MOSFET drain to source

voltage and I_LOAD(VOUT)for the drain current, to

determine if the over-voltage event will cause MOSFET

damage. It may be helpful to adjust C_TMRto meet the

MOS ET’s SOA limits.

OCP/OVP

Trigger Signal

1.45V

3.5uA discharge

Decay Down

25uA charge CTMR

0.6V

0.2V

TMR

GATE TO OUT

3ms TMR blank time

1.25V

POK

FDLY

Figure 2. OCP/OVP Fault Condition Persist Sequence

If the OV event lasts more than one TMR cycle then the

MOSFET will turn on and off, dissipating power each

time it is on and linear regulating and cooling down

when it is off. In this case, use one of the longer-timed

areas of the SOA graph but adjust the drain current

value by the 12% duty cycle of the MOSFET on periods

determine if the MOSFET will work. For thermal

management, the MOSFET dissipation during long

over-voltage events is :

MOSEFT Selection

The N-Channel MOSFET load switch is the critical

component for the protection circuit. Choosing an

appropriate device is not difficult but there are many

important requirements. The most important are :

 on-resistance (R_DS(ON)

)

 maximum current rating

 maximum drain-source voltage

 maximum gate-source voltage

 power dissipation and safe operating area (SOA)

PD_MOSFET(OV)= DC x (V_HV– V_OUT) x I_LOAD(VOUT)

where DC is the duty cycle of linear regulation, typically

about 12%.

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DS2910A-00 August 2017

RT2910A

During an over-current (OC) event the MOSFET will

regulate the output current delivered to the load and the

output voltage will collapse to whatever voltage is

needed to sustain the OC threshold current. According

to the timing determined by the capacitor connected at

the TMR pin, the circuit will turn the load on and off

periodically until the over-current event ends. While

regulating the load current, the MOSFET will dissipate

power and heat up. Unlike an OV event, the output

voltage and the MOSFET’s drain-source voltage may

not be easily predicted. If the output is shorted the

voltage may collapse nearly to zero, placing the entire

input voltage across the MOSFET. Further, this type of

event is likely to continue for long periods. If the output

voltage during the OC event is not easily determined,

higher thresholds, perhaps dramatically more. It’s

generally best to assume that one device will be

subjected to the entire SOA stress.

Application Design Example

Using the typical applications circuit as a design

example with the following specifications: Automotive

Application

V_HV= 48V to 55V DC with transients up to 80V.

Output Voltage : V_OUT<60V

Current Limit (I_LIM) : 10A

Over-voltage Duration : 5ms

Output Over-voltage Protection Setting :

Set the OVP threshold at 58V, choose R4 as 2k and

calculate R3 according to the following equation:

V_{OUT_OVP}= 1.25 x (1 + R3 / R4)

use zero for V_OUT

.

For the rare OC event that is short compared to the TMR

timing, examine the MOSFET’s safe operating area

(SOA) graph, using (V_HV– V_OUT) for MOSFET drain to

source voltage and your I_{OC_THRESHOLD}for drain

current, to determine if the over-current event will cause

Select R3 as a standard 1% value of 91k and calculate

the resulting threshold as :

V_{OUT_OVP}= 1.25 x (1 + 91K / 2K) = 58.125V

Calculate the sense resistor, R_SNS, according to the

following formula :

MOSFET damage.

If the OC event lasts more than one TMR cycle then the

MOSFET will turn on and off, dissipating power each

time it is on and cooling down when it is off. In this case,

use one of the longer timed areas of the SOA graph

(perhaps the DC area) but adjust the I_{OC_THRESHOLD}

value by the 12% duty cycle of the MOSFET on periods

to determine if the MOSFET will work. For thermal

management, the MOSFET dissipation during long

over-current events is :

R_SNS= (V_SNS/ I_LIM) = (50m / 10A) = 5m

Calculate the power dissipation of RSNS to avoid

overheating the sense resistor :

PD_(RSNS)= 1.2 x (I_LIM)²x R_SNS= 1.2 x (10)²x 5m

= 0.6W

PD_MOSFET(OC)= DC x (V_HV– V_OUT) x I_{OC_THRESHOLD}

Select a 1W sense resistor consider a parallel

combination of lower-wattage resistors.

Over-voltage/Over-current Timer Setting :

where DC is the duty cycle of current regulation,

typically about 12%.

Parallel MOSFETs

Calculate the value of fault timing capacitor (C_TMR

)

Select a single MOSFET for most applications. If the

R_DS(ON)target is very low and difficult to achieve at the

necessary voltage rating, multiple devices may be used

in parallel. Parallel devices can decrease the voltage

drop in normal operation and reduce dissipation.

However, SOA requirements must generally be met by

a single device.

using the typical TMR pull-up current and TMR latch

threshold with the following formula :

C_TMR= (t_LATCHx I_{TMR_UP}) / V_TMR= (5ms x 25A) / 1.45

= 0.086F

Select the standard value of 0.1F and calculate the

resulting fault timing :

In OV and OC conditions, GATE will decrease until the

programmed output voltage or current is maintained. In

that state, the MOSFET with the lowest threshold will

carry more current than other parallel MOSFETs with

T_Latch= (C_TMRx V_TMR) / I_{TMR_UP}= (0.1 x 1.45) / 25=

5.8ms.

During an over-voltage or over-current event, GATE will

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15

RT2910A

regulate the output voltage or current while CTMR

charges. When the voltage on the timing capacitor

(V_TMR) reaches the fault threshold (V_{TMR_F}, 1.45V

typical) GATE will turn off the external MOSFET soon.

In the event of a long fault, GATE will turn on and off

repeatedly. The on and off timings (t_{GATE_ON}and

t_{GATE_OFF}) are controlled by the TMR charge and

discharge currents (I_{TMR_UP}and I_{TMR_DN}) and the

voltage difference between the TMR latch and unlatch

thresholds (V_{TMR_L}- V_{TMR_UL}) :

PWM Inverting Converter

Internal Soft-start

The RT2910A feature a “digital soft-start” that is preset

and requires no external capacitor. Upon startup, the

NFB threshold decrements from the reference voltage

0.6V in 128 steps, and each step is 18 clock cycle. So

soft-start time can be calculated as below

T_SS= (128 x 18) / F_S

Where F_Sis PWM switching frequency.

Soft-start is implemented:

1. When exiting under-voltage lockout.

2. When V_5VDETis above 1V.

t_{GATE_ON}= [C_TMRx (V_{TMR_L}V_{TMR_UL}) / I_{TMR_UP}

t_{GATE_ON}= [0.1F x (1.45V 0.4V) / 25A] = 4.2ms

t_{GATE_OFF}= [C_TMRx (V_{TMR_L}V_{TMR_UL}) / I_{TMR_DN}

]

3. When exiting OTP.

Once POK is high, soft-stare is canceled and NFB

reference pulled to 0.6V immediately.

]

t_{GATE_OFF}= [0.1F x (1.45V 0.4V) / 3.5A] = 30ms

Internal Regulator

Choose the MOSFET

The RT2910A incorporates an internal low-dropout

regulator (LDO). This LDO has a 4.25V output and

provides PWM converter internal circuit power request.

The internal LDO has under-voltage lockout circuit

which monitors the voltage of VL. The under-voltage

lockout threshold is typical 3.6V. For best performance,

it is recommended to connect VL to VIN when the input

supply is less than 4.5V and connect a 0.47F capacitor

to GND to compensate loop and decoupling.

Select the MOSFET VDS rating, allowing for your

maximum input voltage and transients. Then select an

operating R_DS(ON)to meet any voltage drop

specifications and your on-state dissipation allowance.

Finally, its package must be able to handle that

dissipation and control its operating temperature.

Most manufacturers list a maximum R_DS(ON)at 25°C

and provide a typical characteristics curve from which

values at other temperatures can be estimated. You

can also use the below equation to estimate maximum

R_DS(ON)from the 25°C specification :

UVLO (Under-Voltage Lockout)

The RT2910A have an internal under-voltage lockout

circuit that monitors the voltage of VIN. If VIN falls below

the UVLO threshold (Typ. 3.5V) the control logic turns

off the internal P-MOSFET. The other internal circuits

are still powered and operating. When VIN higher than

UVLO falling threshold plus 100mV, the RT2910A

resumes operation from a start-up condition (soft-start).

R_{DS(ON)_MAX}= T_J(MAX) 25°C) x 0.5% / 1°C

Given the 48V minimum input and the 10A output

current, the R_DS(ON)must be very low to avoid dropping

a large percentage of the input voltage. To limit the drop

to 1% of 48V (48mV) requires an 4.8m maximum. The

package needs to dissipate about (10A)²x 4.8m =

0.48W into a hot automotive ambient temperature.

Something like the IR Rectifier IRFS4310PbF, with its

V_D-Sat 100V rating, 5.6m R_DS(ON)(typ.) can be to

parallel in order to reduce thermal on MOSFET. D²PAK

package should be more than adequate.

Oscillator Frequency

The RT2910A is a current mode constant switching

frequency converter and it provides the RT pin for

switching frequency setting. User can set switching

frequency by resistor (R_TON) connected from the RT pin

to GND. The switching frequency calculation is shown

as below :

F_S= 1 / [(R // R_TON) x C + 0.2294s]

Where R is inverting resistor: R = 325k

C = 11.4pF

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DS2910A-00 August 2017

RT2910A

Power On/Off Sequence :

V

IN

The RT2910A use a POK indicator to enable HV-Switch

gate driver.

V

<1V

5VDET

Connects POK pin and ENHV pin. POK pulls high to

enable HV-Switch gate driver to turn on external N-

MOSFET.

V

POK

V

GATE

POK go high must satisfy the below conditions :

1. V_INis above POR threshold.

2. V_TMRis lower than 0.6V (HV Switch protection is

not triggered).

V

OUT

3. V_SFBpin is lower than 0.6V.

Start discharge V

OUT

4. V_5VDETpin is above 1V.

5. Not in OTP status.

In order to avoid inrush current on inductor, we suggest

POK rising when NV_OUT= 4.75V (95% of NV_OUT

5V)

=

NV

floating

OUT

The power on sequence must be NV_OUTrising to 4.75V

then POK pull high to enable HV-Switch driver to turn

on N-MOSFET, the power off sequence must be HV-

Switch output voltage falling to 10% level, then NV_OUT

start to falling.

NV

OUT

-5V

Figure 3. (b) Power Off Sequence

Connect a resistor divider at SFB between NV_OUTand

V_REFto adjust POK falling edge threshold. The

threshold voltage is set according to the following

equation :

The detail power on/off sequence is as Figure 3.

The power on/off sequence bases on typical application

circuit.

NV_OUT= V_REF (V_REF V_SFB) x [(R_SFB1+ R_SFB2

)

/R_SFB2

]

Where V_REFis a reference voltage, V_SFBis scaled

output voltage.

POR

V

IN

1ms

NV

OUT

0V

NV

OUT

R

SFB1

SFB2

V

SFB

= 0.6V

SFB

-5V

R

VREF

FDLY

V

POK

C

DLY

C

REF

V

GATE

Figure 4. POK Threshold Voltage and Fault Delay

Time Setting

V

OUT

Set Fault delay time by connecting FDLY pin with a

capacitor (C_DLY) to GND. It utilizes the internal 10A

current source to charge C_DLYto 1.25V when V_TMRis

over 0.6V threshold voltage. This calculation formula is

as below :

Figure 3. (a) Power On Sequence

C_DLYx V_REF= I_Cx T_DLY

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RT2910A

Output Voltage Setting

T_DLY= (C_DLYx V_REF) / I_C

Where V_REFis 1.25V, I_Cis internal current source (Typ.

10A) and C_DLYis external component.

Connect a resistor divider at the NFB pin and VREF pin

to adjust the output voltage. The output voltage is set

according to the following equation :

The RT2910A has a FDLY pin discharge monitor circuit

to ensure the FDLY pin charging starts when the FDLY

pin voltage is low enough (Typ. 0.2V). The function

avoids POK low short pulse and provides enough Fault

delay time. The detail sequence of FDLY pin is as Figure

5.

NV_OUT= V_REF (V_REF V_NFB) x [(R_NFB1+ R_NFB2

)

/R_NFB2

]

Where V_REFis a reference voltage 1.25V, V_NFBis

scaled output voltage.

NV

OUT

R

NFB1

NFB2

OC/OV Triggered

0.6V

NFB

R

VREF

C

V

TMR

REF

V

POK

Figure 7. Setting Output Voltage with a Voltage Divider

1.25V

Input Capacitor selection

V

FDLY

High quality ceramic input decoupling capacitor, such as

X5R or X7R, with values greater than 20F are

recommended for the input capacitor. The X5R and X7R

ceramic capacitors are usually selected for power

regulator capacitors because the dielectric material has

less capacitance variation and more temperature

stability.

Figure 5. Fault Sequence when OC/OV

Current Limit

The RT2910A provides a cycle-by-cycle current limit

control. The current limit circuit implement a peak

current sensing mechanism. If the inductor current is

over the current limit threshold, the PWM controller

turns off the internal P-MOSFET to stop charging the

inductor. The RT2910A sensing the inductor current by

an external sensing resistor. We suggest that the OCP

trigger point is set at 1.1 to 1.5 times of load current,

where, we select 1.25 times.

Voltage rating and current rating are the key parameters

when selecting an input capacitor. Generally, selecting

an input capacitor with voltage rating 1.5 times greater

than the maximum input voltage is a conservatively safe

design.

The next step is to select a proper capacitor for RMS

current rating. One good design uses more than one

capacitor with low Equivalent Series Resistance (ESR)

in parallel to from a capacitor bank.

The current limit calculation formula as below :

I_{L_OC}= [(I_OUTx 1.25) / (1  D)]

R_SENSE= V_{CS_REF}/ I_{L_OC}

Where V_{CS_REF}is current limit threshold.

The input capacitance value determines the input ripple

voltage of the regulator. The input voltage ripple can be

approximately calculated using the following equation :

V = [I_INx (1 – D)] / (C_INx F_S) = (I_Ox D) / (C_INx F_S)

C_IN= (I_Ox D) / (V x F_S)

I

L

D

OUT

LX

+

-

L

-

CS

NV

OUT

C

R

OUT

+

-

R

SENSE

V

OC_REF

+

-

+

100mV

V

CS

Output Capacitor Selection

The purpose of the output capacitor is to reduce the

output ripple. We can use the following equation to

Figure 6.Over-Current Setting

calculation C_OUT

.

C_OUT> (I_OUTx D_MAX) / V_OUTx F_S

When load transient condition occurs, the output

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DS2910A-00 August 2017

RT2910A

capacitor supplies the load current before the controller

can respond.

dissipation depends on the thermal resistance of the IC

package, the PCB layout, the rate of surrounding airflow,

and the difference between the junction and ambient

temperatures. The maximum power dissipation can be

calculated using the following formula :

Therefore, the ESR will dominate the output voltage

SAG during load transient. The output voltage under-

shoot (V_SAG) can be calculated by the following

equation :

P_D(MAX)= (T_J(MAX) T_A) / _JA

V_SAG= ΔI_LOAD* ESR

where T_J(MAX)is the maximum junction temperature, T_A

is the ambient temperature, and _JAis the junction-to-

ambient thermal resistance.

For a given output voltage sag specification, the ESR

value can be determined.

Another parameter that has influence on the output

voltage sag is the equivalent series inductance (ESL).

The rapid change in load current results in di/dt during

transient.

For continuous operation, the maximum operating

junction temperature indicated under Recommended

Operating Conditions is 125C. The junction-to-

ambient thermal resistance, _JA, is highly package

dependent. For a WQFN-24L 5x5 package, the thermal

resistance, _JA, is 28C/W on a standard JEDEC 51-7

high effective-thermal-conductivity four-layer test board.

The maximum power dissipation at T_A= 25C can be

calculated as below :

Therefore, the ESL contributes to part of the voltage sag.

Using a capacitor with low ESL can obtain better

transient performance. Generally, using several

capacitors connected in parallel can have better

transient performance than using a single capacitor for

the same total ESR.

P_D(MAX)= (125C  25C) / (28C/W) = 3.57W for a

Inductor selection

WQFN-24L 5x5 package.

There are different ways to calculate the required

inductance. A good way to do this is to design the

inductor current ripple current ΔI_Lbetween 20%~30% of

the average inductor current I_L. This will make the

regulator designed into a good load transient response

with an acceptable output ripple voltage.

Therefore, we suggest peak-to peak inductor current

ripple I_Lis designed as :

The maximum power dissipation depends on the

operating ambient temperature for the fixed T_J(MAX)and

the thermal resistance, _JA. The derating curves in

Figure 2 allows the designer to see the effect of rising

ambient temperature on the maximum power

dissipation.

4.0

Four-Layer PCB

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

I_L= 0.2 to 0.3 x I_L

So required inductance :

L = (V_INx D) / (F_Sx I_L)

Where D = V_OUT/ (V_IN+ V_OUT

)

Thermal Protection

The device implements an internal thermal shutdown

function when the junction temperature exceeds 150°C.

The thermal shutdown forces the device to stop loop

regulation and pull low POK. Once OTP release, the

RT2910A will soft-start again.

0

25

50

75

100

125

Ambient Temperature (°C)

Thermal Considerations

Figure 8. Derating Curve of Maximum Power

Dissipation

The junction temperature should never exceed the

absolute maximum junction temperature T_J(MAX), listed

under Absolute Maximum Ratings, to avoid permanent

damage to the device. The maximum allowable power

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19

RT2910A

Outline Dimension

Dimensions In Millimeters

Dimensions In Inches

Symbol

Min

Max

Min

Max

A

A1

A3

b

0.700

0.000

0.175

0.250

4.950

3.100

4.950

3.100

0.800

0.050

0.250

0.350

5.050

3.400

5.050

3.400

0.028

0.000

0.007

0.010

0.195

0.122

0.195

0.122

0.031

0.002

0.010

0.014

0.199

0.134

0.199

0.134

D

D2

E

E2

e

0.650

0.026

L

0.350

0.450

0.014

0.018

W-Type 24L QFN 5x5 Package

Richtek Technology Corporation

14F, No. 8, Tai Yuen 1^stStreet, Chupei City

Hsinchu, Taiwan, R.O.C.

Tel: (8863)5526789

Richtek products are sold by description only. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that

such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product.

Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any

infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights

of Richtek or its subsidiaries.

is a registered trademark of Richtek Technology Corporation.

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20

DS2910A-00 August 2017


型号：	RT2910A
厂家：	RICHTEK TECHNOLOGY CORPORATION
描述：	暂无描述
文件：	总20页 (文件大小：1521K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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