RT9245BGC [RICHTEK]
Multi-Phase PWM Controller for K8 CPU Core Power Supply; 多相PWM控制器的K8 CPU内核电源
| 型号： | RT9245BGC |
| 厂家： | 
RICHTEK TECHNOLOGY CORPORATION |
| 描述： | Multi-Phase PWM Controller for K8 CPU Core Power Supply |
| 文件： | 总23页 (文件大小：424K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RT9245B
Multi-Phase PWM Controller for K8 CPU Core Power Supply
General Description
Features
l Multi-Phase Power Conversion with Automatic
Phase Selection
RT9245B is a multi-phase buck DC/DC controller
integrated with all control functions forAMD K8 CPU. The
RT9245B could be operated with 2, 3 or 4 buck switching
stages operating in interleaved phase set automatically.
The multiphase architecture provides high output current
while maintaining low power dissipation on power devices
and low stress on input and output capacitors. The high
equivalent operating frequency also reduces the
component dimension and the output voltage ripple in load
transient.
l 6-bit AMD K8 M2 DAC Output with Active Droop
Compensation for Fast Load Transient
l Smooth VCORE Transition at VID Jump
l Power Stage Thermal Balance by DCR Current
Sense
l Hiccup Mode Over-Current Protection
l Programmable Switching Frequency (50kHz to
400kHz per Phase), Under-Voltage Lockout and Soft-
Start
RT9245B implements both voltage and current loops to
achieve good regulation, response and power stage
thermal balance.
l High Ripple Frequency Times Channel Number
l 28-TSSOP Package
l RoHS Compliant and 100% Lead (Pb)-Free
RT9245B applies theDCR sensing technology newly. The
RT9245B extracts the ESR of output inductor as sense
component to deliver a precise load line regulation and
good thermal balance for next generation processor
application.
Applications
l AMD K8 Processors Voltage Regulator
l Low Output Voltage, High CurrentDC-DC Converters
l Voltage Regulator Modules
Current sense setting, droop tuning, VCORE initial offset
and over current protection are independent on
compensation circuit of voltage loop. The feature greatly
facilitates the flexibility of CPU power supply design and
tuning. The DAC output of RT9245B supports AMD K8
6-bit VID, precise offset value & smooth VCORE transient
at VID jump. The ICmonitors the VCORE voltage forPGOOD
and over-voltage protection. Soft-start, over-current
protection and programmable under-voltage lockout are
also provided to assure the safety of microprocessor and
power system. The RT9245B comes to a small footprint
packageTSSOP-28.
Pin Configurations
(TOP VIEW)
VID4
VID3
VID2
VID1
VID0
VID5
SGND
FB
VCC
28
27
26
25
24
23
22
21
PWM1
PWM2
PWM3
PWM4
CSP4
CSP2
CSP3
CSP1
GND
2
3
4
5
6
7
8
COMP
PGOOD
DVD
SS
RT
VOSS
9
20
19
18
17
16
15
10
11
12
13
14
ADJ
IOUT
CSN
IMAX
Ordering Information
RT9245B
TSSOP-28
Package Type
C : TSSOP-28
Note :
RichTek Pb-free and Green products are :
Operating Temperature Range
P : Pb Free with Commercial Standard
G : Green (Halogen Free with Commer-
cial Standard)
}RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
}Suitable for use in SnPb or Pb-free soldering processes.
}100% matte tin (Sn) plating.
DS9245B-02 March 2007
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RT9245B
Typical Application Circuit
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DS9245B-02 March 2007
RT9245B
Functional Pin Description
VID4 (Pin 1), VID3 (Pin 2), VID2 (Pin 3), VID1 (Pin 4),
VID0 (Pin 5), VID5 (Pin 6)
IOUT (Pin 17)
Output Current Indication Pin. The current through IOUT
pin is proportional to the output current.
DAC voltage identification inputs for K8. These pins are
internally pulled to 1.2V if left open.
ADJ (Pin 18)
SGND (Pin 7)
Current sense output for active droop adjust. Connect a
resistor from this pin to GND to set the load droop.
VCORE differential sense negative input.
FB (Pin 8)
GND (Pin 19)
Inverting input of the internal error amplifier.
Ground for the IC.
COMP (Pin 9)
CSP1 (Pin 20), CSP2 (Pin 22), CSP3 (Pin 21) & CSP4
(Pin 23)
Output of the error amplifier and input of the PWM
comparator.
Current sense positive inputs for individual converter
channel current sense.
PGOOD (Pin 10)
PWM1 (Pin 27), PWM2 (Pin 26), PWM3 (Pin 25) &
PWM4 (Pin 24)
Power good open-drain output.
DVD (Pin 11)
PWM outputs for each driven channel. Connect these pins
to the PWM input of the MOSFET driver. For systems
which use 3 channels, connect PWM4 high. Two channel
systems connect PWM3 high.
Programmable power UVLO detection input. Trip threshold
= 1.0V at VDVD rising.
SS (Pin 12)
Connect this SS pin to GND with a capacitor to set the
soft-start time interval.
VCC (Pin 28)
IC power supply. Connect this pin to a 5V supply.
RT (Pin 13)
Switching frequency setting. Connect this pin toGND with
a resistor to set the frequency.
VOSS (Pin 14)
VCORE initial value offset. Connect this pin toGND with a
resistor to set the negative offset value. Connect this pin
to VCC to set positive offset value.
IMAX (Pin 15)
Programmable over currert setting.
CSN (Pin 16)
Current sense negative input of all channels.
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RT9245B
Function Block Diagram
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DS9245B-02 March 2007
RT9245B
Table 1. Output Voltage Program
Pin Name
Nominal Output Voltage DACOUT
VID5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
VID4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
VID3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
VID2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
VID1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.5500
1.5250
1.5000
1.4750
1.4500
1.4250
1.4000
1.3750
1.3500
1.3250
1.3000
1.2750
1.2500
1.2250
1.2000
1.1750
1.1500
1.1250
1.1000
1.0750
1.0500
1.0250
1.0000
0.9750
0.9500
0.9250
0.9000
0.8750
0.8500
0.8250
0.8000
0.7750
0.7625
0.7500
To be continued
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RT9245B
Table 1. Output Voltage Program
Pin Name
Nominal Output Voltage DACOUT
VID5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID4
VID3
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
VID2
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
VID1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0.7375
0.7250
0.7125
0.7000
0.6875
0.6750
0.6625
0.6500
0.6375
0.6250
0.6125
0.6000
0.5875
0.5750
0.5625
0.5500
0.5375
0.5250
0.5125
0.5000
0.4875
0.4750
0.4625
0.4500
0.4375
0.4250
0.4125
0.4000
0.3875
0.3750
Note: (1) 0 : Connected to GND
(2) 1 : Open
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DS9245B-02 March 2007
RT9245B
Absolute Maximum Ratings (Note 1)
l Supply Voltage, VCC ------------------------------------------------------------------------------------------ 7V
l Input, Output or I/O Voltage -------------------------------------------------------------------------------- GND - 0.3V to VCC + 0.3V
l PowerDissipation, PD @ TA = 25°C
TSSOP-28 ------------------------------------------------------------------------------------------------------ 1W
l Package Thermal Resistance (Note 4)
TSSOP-28, qJA ------------------------------------------------------------------------------------------------ 100°C/W
l JunctionTemperature ---------------------------------------------------------------------------------------- 150°C
l Lead Temperature (Soldering, 10 sec.)------------------------------------------------------------------- 260°C
l StorageTemperature Range -------------------------------------------------------------------------------- - 65°C to 150°C
l ESD Susceptibility (Note 2)
HBM (Human Body Mode) ---------------------------------------------------------------------------------- 2kV
MM (Machine Mode) ----------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions
(Note 3)
l Supply Voltage, VCC ----------------------------------------------------------------------------------------- 5V ± 10%
l Junction Temperature Range ------------------------------------------------------------------------------- - 40°C to 125°C
l AmbientTemperature Range ------------------------------------------------------------------------------- - 40°C to 85°C
Electrical Characteristics
(VCC = 5V, TA = 25°C, unless otherwise specified)
Parameter
Supply Current
Symbol
Test Conditions
Min
Typ
Max Units
V
CC
Nominal Supply Current
Power-On Reset
POR Threshold
Hysteresis
I
PWM 1,2,3,4 Open
--
12
16
mA
CC
V
V
V
V
V
CC
Rising
4.0
0.2
0.94
--
4.2
0.5
1.0
50
4.5
--
V
V
CCRTH
CCHYS
DVDTP
DVDHYS
Trip (Low to High)
Hysteresis
Enable
1.06
--
V
V
DVD
Threshold
mV
Oscillator
Free Running Frequency
f
f
R
R
= 20kW
= 20kW
170
200
230
kHz
OSC
RT
RT
Frequency Adjustable Range
Ramp Amplitude
50
--
--
400
--
kHz
V
OSC_ADJ
DV
1.9
1.0
OSC
Ramp Valley
V
V
0.7
--
V
RV
Maximum Duty of Each Channel
RT Pin Voltage
58
64
70
%
V
R
= 20kW
0.9
1.0
1.1
RT
RT
Reference and DAC
V
V
³ 1V
- 1
- 10
--
--
--
--
--
+1
+10
0.8
--
%
mV
V
DAC
DACOUT Voltage Accuracy
DV
DAC
< 1V
DAC
DAC (VID0-VID5) Input Low
DAC (VID0-VID5) Input High
V
V
ILDAC
IHDAC
1.2
V
To be continued
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RT9245B
Parameter
Symbol
Test Conditions
Min
2.5
--
Typ
3.5
2.1
1.0
Max
4.5
--
Units
kW
V
DAC (VID0-VID5) pull up resistor
DAC Pull Up Voltage
VOSS Pin Voltage
V
VOSS
R
= 100kW
0.9
1.1
V
VOSS
Error Amplifier
DC Gain
--
--
--
60
10
6
--
--
--
dB
Gain-Bandwidth Product
Slew Rate
GBW
SR
MHz
V/ms
COMP = 10pF
Current Sense GM Amplifier
CSN Full Scale Source Current
CSN Current for OCP
Protection
100
150
--
--
--
--
mA
mA
I
ISPFSS
320
0.9
400
1.0
450
1.1
mV
V
Over-Voltage Trip (V - V
)
D
R
= 0W
ADJ
FB
DAC
OVT
IMAX Voltage
V
IMAX
R
IMAX
= 20kW
Power Good
Output Low Voltage
--
--
0.2
V
V
I
= 4mA
PGOODL
PGOOD
Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are
for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. The device is not guaranteed to function outside its operating conditions.
Note 4. qJA is measured in the natural convection at TA = 25°C on a low effective single layer thermal conductivity test board of
JEDEC 51-3 thermal measurement standard.
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DS9245B-02 March 2007
RT9245B
Typical Operating Characteristics
PWM vs. VCOMP
Adjustable Frequency
700
70
60
50
40
30
20
10
0
RRT = 16kW
600
500
400
300
200
100
0
0
10
20
30
40
50
60
70
0.5
1
1.5
2
2.5
3
3.5
RRT
(kW)
VCOMP (V)
Relationship Between Inductor
Current and VADJ
Power-Off @ IOUT = 60A
CH1:(5V/Div)
CH2:(5V/Div)
PWM
PWM
CH1:(5V/Div)
CH2:(20V/Div)
VSS
UGATE
CH3:(10V/Div)
CH4:(1V/Div)
VADJ
LGATE
VCOMP
CH3:(50mV/Div)
CH4:(20A/Div)
IL
Time (10ms/Div)
Time (25ms/Div)
Power-On @ IOUT = 60A
Ripple
CH1:(5V/Div)
CH2:(5V/Div)
VSS
PWM
VCORE
(5mV/Div)
UGATE
LGATE
CH3:(20V/Div)
CH4:(10V/Div)
L = 0.3mH, C = 5600mF
Time (2.5ms/Div)
Time (10ms/Div)
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RT9245B
DVID at Rising
DVID at Falling
VCORE
(500mV/Div)
(500mV/Div)
VCORE
VID5
VID5
(2V/Div)
(2V/Div)
Time (50ms/Div)
Time (50ms/Div)
Transient Response
Transient Falling
(20mV/Div)
VCORE
(20mV/Div)
Time (5ms/Div)
Time (500ns/Div)
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DS9245B-02 March 2007
RT9245B
Application Information
RT9245B is a multi-phaseDC/DC controller that precisely
regulates CPU core voltage and balances the current of
different power channels. The converter consisting of
RT9245B and its companion MOSFET driver RT9619
provides high quality CPUpower and all protection functions
to meet the requirement of modern VRM.
VADJ = 8 x IX x RADJ
VADJ is then subtracted from VID_DAC output as the real
referencevoltage atnon-invertinginput of the error amplifier
as shown if Figure 1. Consequently, load line slope is
calculated as :
ΔVCORE 8 x RADJ xDCR
LoadLine =
=
ΔICORE
N xRCSN
Voltage Control
RT9245B senses the CPU VCORE by SGND pin to sense
the return of CPU to minimize the voltage drop on PCB
trace at heavy load. OVP is sensed at FB pin. The internal
high accuracyVIDDAC provides the reference voltage for
K8 compliance. Control loop consists of error amplifier,
multi-phase pulse width modulator, driver and power
components. As conventional voltage mode PWM
controller, the output voltage is locked at the VREF of
error amplifier and the error signal is used as the control
signal of pulse width modulator. The PWM signals of
different channels are generated by comparison of EA
output and split-phase sawtooth wave. Power stage
transforms VIN to output by PWM signal on-time ratio.
whereN is the phase number of operation.
I
/4
VOSS
R
CSN
V
-
CORE
EA
+
V
ADJ
DAC
8I
X
R
ADJ
Figure 1. Load Line and Offset Function
Fault Detection
The chip detects FB for over voltage and power good
detection. The “hiccup mode” operation of over current
protection is adopted to reduce the short circuit current.
The in-rush current at the start up is suppressed by the
soft start circuit through clamping the pulse width and
output voltage.
Current Balance
RT9245B senses the inductor current via inductor'sDCR
forchannel currentbalance and drooptuning. The differential
sensing GM amplifier converts the voltage on the sense
component (can be a sense resistor or the DCR of the
inductor) to current signal into internal balance circuit.
The current balance circuit sums and averages the current
signals and then produces the balancing signals injected
to pulse width modulator. If the current of some power
channel is larger than average, the balancing signal
reduces that channels pulse width to keep current balance.
The use of singleGM amplifier via time sharing technique
to sense all inductor currents can reduce the offset errors
and linearity variation between GMs. Thus it can greatly
improve signal processing especially when dealing with
such small signal as voltage drop acrossDCR.
Phase Setting and Converter Start Up
RT9245B interfaces with companion MOSFET drivers (like
RT9619, RT9607 series) for correct converter initialization.
The tri-state PWM output (high, low and high impedance)
senses its interface voltage when IC POR acts (both VCC
andDVD trip). The channel is enabled if the pin voltage is
1.2V less than VCC. Tie the PWM to VCC and the
corresponding current sense pins to GND or left float if
the channel is unused. For example, for 3-Channel
application, connect PWM4 high.
Droop & Load Line Setting
Current Sensing Setting
RT9245B injects averaged current IX into the resistor RADJ
connected to ADJ pin to generate a load-current-
dependent voltage RADJ for droop setting:
RT9245B senses the current flowing through inductor via
itsDCR for channel current balance and droop tuning.
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11
RT9245B
The differential sensingGM amplifier converts the voltage
on the sense component (can be a sense resistor or the
DCR of the inductor) to current signal into internal circuit
(see Figure 2).
Figure 5 shows the time sharing technique ofGM amplifier.
We apply test signal at phase 4 and observe the waveforms
at both pins of GM amplifier. The waveforms show time
sharing mechanism and the perfomance of GM to hold
both input pins equal when the shared time is on.
L
V
C
= R´ C V = DCR´ I
I =
X
C
L
DCR
R
CSN
L
R
Time Sharing of GM
DCR
CH1:(2V/Div)
+V -
C
CH2:(50mV/Div)
CH3:(50mV/Div)
C
+
-
PWM3
R
CSN
GMx
VCSP4
I
x
Figure 2. Current Sense Circuit
VCSP4
and
VCSN
VCSN
Figure 3 is the test circuit forGM. We apply test signal at
GM inputs and observe its signal process output at ADJ
pin. Figure 4 shows the variation of signal processing of
all channels. We observe zero offsets and good linearity
between phases.
Time (1ms/Div)
Figure 5
Over Current Protection
CSPX
RT9245B uses an external resistor RIMAX to set a
programmable over current trip point. OCP comparator
compares each inductor current with this reference current.
RT9245B uses hiccup mode to eliminate fault detection
of OCP or reduce output current when output is shorted
to ground.
V
C
ADJ
+
SUM/M
ADJ
MUX
GM
-
CSN
+
R
CSN
1k
R
1k
V
ADJ
-
I
x
Figure 3. The Test Circuit of GM
1
2
VIMAX
RIMAX
1
3
IL x DCR
x
Û
x
RCSN
GM
300
250
200
150
100
50
OCP Comparator
1/3 I
+
-
X
1/2 I
IMAX
OCP
Setting
V
IMX
R
IMX
0
0
25
50
75
100
125
150
Figure 6. Over Current Comparator
VC (mV)
Figure 4. The Linearity of GMx
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DS9245B-02 March 2007
RT9245B
Over Current Protection
For some case with preferable current ratio instead of
current balance, the corresponding technique is provided.
Due to different physical environment of each channel, it
is necessary to slightly adjust current loading between
channels. Figure 9 shows the application circuit of GM for
current ratio requirement. Applying KVL along L+DCR
branch and R1+C//R2 branch :
CH1:(5V/Div)
CH2:(5V/Div)
PWM
dIL
dt
VC
R2
dVC
dt
L
+DCR´ IL = R1(
dVC R1 +R2
+C
)+ VC
VSS
= R1C
+
VC
dt
R2
R2
R1 +R2
For VC =
DCR´ IL
Time (25ms/Div)
Look for its corresponding conditions :
Figure 7. The Over Current Protection in the soft start
interval
dI
dI
L
L
L
+DCR´ I = (R1//R2)´ C´ DCR´
+DCR´ I
L
L
dt
dt
L
Over Current Protection
Let
= (R1//R2)´ C
DCR
CH1:(5V/Div)
CH2:(5V/Div)
L
= (R1//R2)´ C
Thus if
Then
DCR
R2
PWM
VC
=
´ DCR´ IL
R1+R2
With internal current balance function, this phase would
share (R1+R2)/R2 times current than other phases.
Figure 10 & 11 show different settings for the power stages.
Figure 12 shows the performance of current ratio compared
with conventional current balance function in Figure 13.
VSS
Time (25ms/Div)
I
Figure 8. Over Current Protection at steady state
L
0.3uH
0.6m
Current Ratio Setting
470
I
1uF
470
L
L
DCR
Figure 10. GM4 Setting for current ratio function
+V -
C
R1
I
C
L
0.3uH
0.6m
R2
Figure 9. Application circuit for current ratio setting
DS9245B-02 March 2007
470
1uF
Figure 11. GM1~3 Setting for current ratio function
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13
RT9245B
Load Line without dead zone at light loads
Current Ratio Function
35
30
25
20
15
10
5
1.31
IL4
1.3
1.29
1.28
1.27
1.26
1.25
1.24
1.23
w/o Dead Zone Compensation
RCSN open
IL3
IL2
IL1
RCSN = 82k
w/i Dead Zone Compensation
0
0
15
30
45
60
75
90
0
5
10
15
20
25
IOUT (A)
IOUT (A)
Figure 14
Figure 12
LX
R
LX
I
LX
Current Balance Function
30
25
20
15
10
5
R
X
C
X
V
OUT
+
-
V
X
+
-
IL1
R
CSN
GMx
Ix
IL2
R
CSN2
Figure 15. Application circuit of GM
Referring to Figure 15, IX is expressed as :
0
0
20
40
60
80
100
VOUT
ILX_50% x RLX
RCSN2
ILX_50% x RLX
RCSN
(1)
IX =
+
+
IOUT (A)
Figure 13
Dead Zone Elimination
RCSN2
where ILX_50% is the of inductor current at 50% period. To
make sure RT9245B could sense the inductor current,
right hand side of Equation (1) should always be positive:
RT9245B samples and holds inductor current at 50%
period by time-sharing sourcing a current IX to RCSN. At
light load condition when inductor current is not balance,
voltageVX across the sensing capacitor would be negative.
It needs a negative IX to sense the voltage. However,
RT9245B CANNOTprovide a negative IX and consequently
cannot sense negative inductor current. This results in
dead zone of load line performance as shown in Figure
14. Therefore a technique as shown in Figure 15 is required
to eliminate the dead zone of load line at light load
condition.
VOUT
ILX_50% x RLX ILX_50% xRLX
(2)
+
+
³ 0
RCSN2
RCSN2
RCSN
Since RCSN2 >> RCSN in practical application, Equation (2)
could be simplified as :
VOUT
ILX_50% x RLX
RCSN
³
RCSN2
Figure 14 shows that dead zone of load line at light load
is eliminated by applying this technique.
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14
DS9245B-02 March 2007
RT9245B
VID on the Fly
Output Voltage Offset Function
With external pull up resistors tied to VID pins, RT9245B
converters different VID codes from CPU into output
voltage. Figure 16 and Figure 17 show the waveforms of
VID on the fly function.
To meet AMD K8 requirement of initial offset of load line,
RT9245B provides programmable initial offset function.
External resistor RVOSS and voltage source at VOSS pin
VVOSS
generate offset current
IVOSS
=
RVOSS
, where VVOSS is 1V typical. One quarter of IVOSS flows
through RB1 as shown in Figure 18. Error amplifier would
hold the inverting pin equal to VDAC - VADJ. Thus output
voltage is subtracted from VDAC -VADJ for a constant offset
VID on the Fly (Falling)
PWM
VCORE
voltage.
VCORE = VDAC - VADJ
RFB1
4´ RVOSS
VFB
-
A positive output voltage offset is possible by connecting
RVOSS to VDD instead of to GND. Please note that when
RVOSS is connected to VDD, VVOSS is VDD - 2V typically
and half of IVOSS flows through RFB1. VCORE is rewritten as:
CH3:(500mV/Div)
CH4:(1V/Div)
CH1:(5V/Div)
CH2:(500mV/Div)
VID5
RFB1
VCORE = VDAC - VADJ +
RVOSS
VDAC = 1.500, IOUT = 5A
Time (25ms/Div)
Voltage Offset Function
1.284
Figure 16
1.282
1.28
VID on the Fly (Rising)
1.278
1.276
1.274
1.272
1.27
PWM
VCORE
VFB
CH1:(5V/Div)
CH2:(500mV/Div)
CH3:(500mV/Div)
CH4:(1V/Div)
1.268
50
60
70
80
90
100
110
R
OSS (kW)
VID5
VDAC = 1.500, IOUT = 5A
Figure 19
Time (25ms/Div)
Load Line Setting and Thermal Compensation
Figure 17
VADJ = 8 x AVG(IX) x RADJ
VOUT = VDAC - VADJ
1/4 I
VOSS
AVG(IX) is a PTC current. By properly use anNTC resistor
at ADJ. Load line can be thermally compensated.
RB1
-
EA
+
V
-V
DAC ADJ
Figure 18. Offset Setting
DS9245B-02 March 2007
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15
RT9245B
PGOOD Function
If the fault condition is OV, V(SS) and PGOOD will be pulled
low immediately also. RT9245B will try to turn on low
side MOSFET and turn off high side MOSFET. VOUT will
fall quickly to protect CPU from high voltage. The typical
waveform is shown in Figure 23.
During start-up, RT9245B will detect 5VCC and 12VIN
(throughDVD pin). In Figure 21, 5VCC or 12VIN is not ready
during T1. V(SS) (in Figure 20) is pulled toGND by FAULT.
V(EAP) is also equal to GND. V(FB) and VOUT will try to
follow V(EAP) thus both V(FB) and VOUT are equal to GND
during T1. During T2, both 5VCC and 12VIN are ready,
FAULT = low, OPSS starts charging up CSS. In the design
of RT9245B, ISS (the maximal current sink and source
capability of OPSS) is limited and time-variant. DuringT2
(V1 = 0.4V > V(SS) > 0), ISS(T2) is equal to about 10uA.
Z2
V
-
FB
N1
Z1
OUT
EA
COMP
+
5V
CC
OPSS
EAP
V
+
DAC
-
V1
T2 = CSS x
@ 4x104 x CSS
ISS(T2)
SS
FAULT
C
After V(SS) > V1, ISS changes to about 20uA. The rising
speed of V(SS) becomes about 2 times faster than in T1.
In Figure 20, MOSFETN1 will turn on only if V(SS) > VTH_N1
(threshold voltage of N1) @ 0.7V = V2. Before N1 turns
on, V(EAP) is still 0V.
SS
Figure 20. Soft Start Circuit
5V _ready
CC
and DVD_ready
(V2- V1)
T3 = CSS x
@ 1.5x104 x CSS
ISS(T3)
PGOOD
AfterV(SS) > V2, MOSFETN1 turns on, V(EAP) starts rising.
ISS(T4) is still equal to about 20uA. V(SS,EAP) is equal to
VTH_N1. Due to the body effect of MOSFET N1, VTH_N1
increases with higher V(EAP). For example, if VOUT target
is 1.4V, V(SS,EAP) will be equal to about 0.7V at the
beginning of T4 and equal to about 1.1V at the end of T4.
V4
V3
V
(SS)
V
OUT
V2
V1
(V4 - V2)
T4 = CSS x
@ 9x104 x CSS
ISS(T4)
T2
T3
T4
T5
T6
T1
Figure 21. Soft Start Waveform
At the end of T4, VOUT is very close to the target (within
the range of ±40mV). An internal 1ms timer starts. After
about 1ms(T5), The open-drain output PGOOD releases.
PGOOD
After PGOOD releases, ISS(T6) becomes about 320uA to
accelerate OPSS. RT9245B enters normal operation mode
and is capable to follow VID on the fly.
V
(SS)
When any of the fault conditions happens, V(SS) and
PGOOD will be pulled lowimmediately. If thefault condition
is one of 5VCC low, DVD low, OC or VID_OFF, RT9245B
will try to turn off both high side MOSFET and low side
MOSFET. VOUT will fall slowly to avoid negative VOUT. The
typical waveform is shown in Figure 22.
V
OUT
5V _Low + DVD_Low + OC + VID_OFF
CC
Figure 22. Waveform for 5VCC_Low, DVD_Low, OC or
VID_OFF
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16
DS9245B-02 March 2007
RT9245B
EA Rising Slew Rate
PGOOD
VFB
V
(SS)
V
OUT
OV
CH1:(500mV/Div)
CH2:(2V/Div)
Figure 23. Waveform for OV
VCOMP
Error Amplifier Characteristic
Time (250ns/Div)
For fast response of converter to meet stringent output
current transient response, RT9245B provides large slew
rate capability and high gain-bandwidth performance.
Figure 25. EA Falling Transient with 10pF Loading;
Slew Rate = 8V/us
4.7k
EA Falling Slew Rate
4.7k
B
-
A
EA
+
V
DAC
VFB
Figure 26. Gain-Bandwidth Measurement by signal A
divided by signal B
CH1:(500mV/Div)
CH2:(2V/Div)
VCOMP
Time (250ns/Div)
Figure 24. EA Rising Transient with 10pF Loading; Slew
Rate = 8V/us
DS9245B-02 March 2007
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17
RT9245B
0dB
180°
Figure 27. EA Frequency Response with closed loop gain set at 0db to observe gain-bandwidth product; -3dB at
10.86MHz
Design Procedure Suggestion
PCB Layout
a.Output filter pole and zero (Inductor, output capacitor
value & ESR).
a.Kelvin sense for current senseGM amplifier input.
b.Refer to layout guide for other items.
b.Error amplifier compensation & sawtooth wave amp-
litude (compensation network).
Voltage Loop Setting
Design Example
c.Kelvin sense for VCORE
.
Given:
Current Loop Setting
Apply for four phase converter
a.GM amplifier S/H current (current sense component
DCR, CSN pin external resistor value).
VIN = 12V
b.Over-current protection trip point (RIMAX resistor).
VCORE = 1.4V
ILOAD = 30A to 125A
VRM Load Line Setting
VDROOP = 95mV with load (1mW Load Line)
OCP trip point set at 40A for each channel (S/H)
DCR = 0.6mW of inductor at 25°C
L = 0.3mH
a.Droop amplitude (ADJ pin resistor).
b.No load offset (RCSN2
)
c.DAC offset voltage setting (VOSS pin & compen- sation
network resistor RB1).
COUT = 5600mF with 1mW equivalent ESR.
Power Sequence & SS
DVD pin external resistor and SS pin capacitor.
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18
DS9245B-02 March 2007
RT9245B
1. Compensation Setting
C2 5.6pF
a. ModulatorGain, Pole and Zero:
C3 680pF
C1
RB2
From the following formula:
15k
-
2.7nF
RB1
1.5k
Modulator Gain = VIN/VRAMP = 12/1.9 = 6.3 (i.e 16dB)
where VRAMP : Ramp amplitude of saw-tooth wave
LC Filter Pole = 3.88kHz and
EA
+
Figure 28. Type 3 compensation network of EA
The over all loop gain with load is shown in Figure 29 to
Figure 31.
ESR Zero = 28kHz
b. EA CompensationNetwork:
3. Over-Current Protection Setting
Select RB1 = 1.5k, RB2 = 15k, C1 = 2.7nF, C2 = 5.6pF,
C3 = 680pF and use the Type 3 compensation scheme
shown in Figure 28. By calculation.
Consider the temperature coefficient of copper
3900ppm/°C,
1
V
1
IL ´ DCR
IMAX
´
Û
´
1
FZ1 =
FZ2 =
FP =
=156kHz
= 3.9kHz
2 RIMAX
3 RCOMMON
2p xRB1x C3
1 1.690V
1 40A ´ 1.39mW
1
´
Û
´
2
RIMAX
3
330W
2p x RB2 x C1
Let RIMAX = 14kW
1
= 5.8kHz
2p x RB2 x (C2//C1)
4. Soft-Start Capacitor Selection
MiddleBand Gain =10 (i.e.20dB)
For most application cases, 0.1mF is a good engineering
value.
Figure 29. The Frequency Response withNo Load
DS9245B-02 March 2007
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19
RT9245B
Figure 30. The Frequency Response with Middle Load
Figure 31. The Frequency Response with Heavy Load
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20
DS9245B-02 March 2007
RT9245B
Layout Guide
Place the high-power switching components first, and separate them from sensitive nodes.
1. Most critical path: the current sense circuit is the most sensitive part of the converter. The current sense
resistors tied to CSP1,2,3,4 and CSN should be located not more than 0.5 inch from the IC and away from
the noise switching nodes. The PCB trace of sense nodes should be parallel and as short as possible.
2. Switching ripple current path:
a. Input capacitor to high side MOSFET.
b. Low side MOSFET to output capacitor.
c. The return path of input and output capacitor.
d. Separate the power and signal GND.
e. The switching nodes (the connection node of high/low side MOSFET and inductor) is the most noisy points.
Keep them away from sensitive small-signal node.
f. Reduce parasitic R, L by minimum length, enough copper thickness and avoiding of via.
3. MOSFET driver should be closed to MOSFET.
4. The compensation, bypass and other function setting components should be near the IC and away from the noisy
power path.
L1
SW1
VOUT
VIN
RIN
COUT
RL
CIN
V
L2
SW2
Figure 32. Power Stage Ripple Current Path
DS9245B-02 March 2007
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21
RT9245B
Next to IC
C
+12V or +5V
+12V
VCC
PWM
PWM
+5V
VCC
IN
0.1uF
C
BP
RT
BOOT
BOOT
UGATE
PHASE
VOSS
Next to IC
COMP
SGND
L
O1
VCORE
C
C
C
R
RT9245B
CSN
OUT
CSN
C
RT9619
LGATE
PGND
IN
R
C
Locate next
to FB Pin
FB
R
FB
CSPx
ADJ
Locate near MOSFETs
GND
For Thermal Couple
Figure 33. Layout Consideration
Figure 34. Layout of power stage
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22
DS9245B-02 March 2007
RT9245B
Outline Dimension
D
L
E
E1
e
A2
A
A1
b
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
1.200
0.152
1.050
0.305
9.804
Min
Max
0.047
0.006
0.041
0.012
0.386
A
A1
A2
b
0.850
0.050
0.800
0.178
9.601
0.033
0.002
0.031
0.007
0.378
D
e
0.650
0.026
E
6.300
4.293
0.450
6.500
4.496
0.762
0.248
0.169
0.018
0.256
0.177
0.030
E1
L
28-Lead TSSOP Plastic Package
Richtek Technology Corporation
Headquarter
Richtek Technology Corporation
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
8F, No. 137, Lane 235, Paochiao Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)89191466 Fax: (8862)89191465
Email: marketing@richtek.com
DS9245B-02 March 2007
www.richtek.com
23
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