RT9245CPC_技术文档

RT9245C

Multi-Phase PWM Controller for CPU Core Power Supply

General Description

Features

^zMulti-Phase Power Conversion with Automatic

RT9245C is a multi-phase buck DC/DC controller

integrated with all control functions for AMD K8 CPU or

Intel^®GHz CPU which is VRD10.x-compliant. The

RT9245C could be operated with 2, 3 or 4 buck switching

stages operating in interleaved phase set automatically.

The multiphase architecture provides high output current

while maintaining low power dissipation on power devices

and low stress on input and output capacitors. The high

equivalent operating frequency also reduces the

component dimension and the output voltage ripple in load

transient.

Phase Selection

^z6-bits VRD10.x or 5-bit K8 DAC Output with Active

Droop Compensation for Fast Load Transient

^zSmooth V_CORETransition at VID Jump

^zPower Stage Thermal Balance by DCR Current

Sense

^zHiccup Mode Over-Current Protection

^zProgrammable Switching Frequency (50kHz to

400kHz per Phase), Under-Voltage Lockout and Soft-

Start

^zHigh Ripple Frequency Times Channel Number

z 28-TSSOP Package

RT9245C implements both voltage and current loops to

achieve good regulation, response and power stage

thermal balance.

z RoHS Compliant and 100% Lead (Pb)-Free

RT9245C applies theDCR sensing technology newly. The

RT9245C extracts the DCR of output inductor as sense

component to deliver a precise load line regulation and

good thermal balance for next generation processor

application.

Applications

z Intel^®Processors Voltage Regulator : VRD10.x andAMD

K8

z Low Output Voltage, High CurrentDC-DC Converters

z Voltage Regulator Modules

Current sense setting, droop tuning, V_COREinitial offset

and over current protection are independent on

compensation circuit of voltage loop. The feature greatly

facilitates the flexibility of CPU power supply design and

tuning. The DAC output of RT9245C supports AMD K8

5-bit VIDand Intel^®VRD10.x with 6-bit VIDinput, precise

offset value & smooth V_COREtransient at VID jump. The

IC monitors the V_COREvoltage for PGOODand over-voltage

protection. Soft-start, over-current protection and

programmable under-voltage lockout are also provided to

assure the safety of microprocessor and power system.

The RT9245C comes to a small footprint package

TSSOP-28.

Pin Configurations

(TOP VIEW)

VID4

VID3

VID2

VCC

28

27

26

25

24

23

22

21

PWM1

PWM2

PWM3

PWM4

CSP4

CSP2

CSP3

CSP1

GND

2

3

4

5

6

7

8

VID1

VID0

VID125/VIDSEL

SGND

FB

9

20

19

18

17

16

15

COMP

PGOOD

DVD

SS

RT

VOSS

10

11

12

13

14

ADJ

IOUT

CSN

IMAX

TSSOP-28

Ordering Information

Note :

RichTek Pb-free and Green products are :

RT9245C

Package Type

C : TSSOP-28

`RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

Operating Temperature Range

P : Pb Free with Commercial Standard

G : Green (Halogen Free with Commer-

cial Standard)

`Suitable for use in SnPb or Pb-free soldering processes.

`100% matte tin (Sn) plating.

DS9245C-02 March 2007

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RT9245C

Typical Application Circuit

+

Figure A. For Intel

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DS9245C-02 March 2007

RT9245C

+

Figure B. For AMD

DS9245C-02 March 2007

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RT9245C

Functional Pin Description

VID4 (Pin 1), VID3 (Pin 2), VID2 (Pin 3), VID1 (Pin 4),

VID0 (Pin 5)

IMAX (Pin 15)

Programmable over currert setting.

DAC voltage identification inputs for VRD10.x. These pins

are internally pulled to 1.2V (VRD10.x) or 2.1V (K8) if left

open.

CSN (Pin 16)

Current sense negative input of all channels.

VID125/VIDSEL (Pin 6)

IOUT (Pin 17)

When this pin pull low or left pen -->VR10 VID input, pull

high to 5V -->K8.

Output Current Indication Pin. The current through IOUT

pin is proportional to the output current.

SGND (Pin 7)

ADJ (Pin 18)

V_COREdifferential sense negative input.

Current sense output for active droop adjust. Connect a

resistor from this pin to GND to set the load droop.

FB (Pin 8)

GND (Pin 19)

Inverting input of the internal error amplifier.

Ground for the IC.

COMP (Pin 9)

CSP1 (Pin 20), CSP2 (Pin 22), CSP3 (Pin 21) & CSP4

(Pin 23)

Output of the error amplifier and input of the PWM

comparator.

Current sense positive inputs for individual converter

channel current sense.

PGOOD (Pin 10)

Power good open-drain output.

PWM1 (Pin 27), PWM2 (Pin 26), PWM3 (Pin 25) &

PWM4 (Pin 24)

DVD (Pin 11)

Programmable power UVLO detection input. Trip threshold

= 1.0V at V_DVDrising.

PWM outputs for each driven channel. Connect these pins

to the PWM input of the MOSFET driver. For systems

which use 3 channels, connect PWM4 high. Two channel

systems connect PWM3 high.

SS (Pin 12)

Connect this SS pin to GND with a capacitor to set the

soft-start time interval.

VCC (Pin 28)

IC power supply. Connect this pin to a 5V supply.

RT (Pin 13)

Switching frequency setting. Connect this pin toGNDwith

a resistor to set the frequency.

VOSS (Pin 14)

V_COREinitial value offset. Connect this pin to GND with a

resistor to set the negative offset value. Connect this pin

to VCC to set positive offset value.

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DS9245C-02 March 2007

RT9245C

Function Block Diagram

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RT9245C

Table 1. Output Voltage Program (VRD 10.x)

Pin Name

Nominal Output oltage DACOUT

ID4

1

0

1

ID3

ID2

1

0

1

0

1

0

ID1

1

0

1

0

1

0

1

0

1

ID0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

ID125

X

0

1

0

1

No CPU

0.8375

0.8500

0.8625

0.8750

0.8875

0.9000

0.9125

0.9250

0.9375

0.9500

0.9625

0.9750

0.9875

1.0000

1.0125

1.0250

1.0375

1.0500

1.0625

1.0750

1.0875

1.1000

1.1125

1.1250

1.1375

1.1500

1.1625

1.1750

1.1875

1.2000

1.2125

To be continued

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

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DS9245C-02 March 2007

RT9245C

Table 1. Output Voltage Program (VRD 10.x)

Pin Name

Nominal Output oltage DACOUT

ID4

1

0

ID3

1

0

1

ID2

0

1

0

1

0

ID1

0

1

0

1

0

1

0

1

ID0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

ID125

1

1.2250

1.2375

1.2500

1.2625

1.2750

1.2875

1.3000

1.3125

1.3250

1.3375

1.3500

1.3625

1.3750

1.3875

1.4000

1.4125

1.4250

1.4375

1.4500

1.4625

1.4750

1.4875

1.5000

1.5125

1.5250

1.5375

1.5500

1.5625

1.5750

1.5875

1.6000

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Note: (1) 0 : Connected to GND

(2) 1 : Open

^{(3) X : Don}'t Care

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RT9245C

Table 2. Output Voltage Program (K8)

VID4

0

1

VID3

0

1

0

1

VID2

0

1

0

1

0

1

0

1

VID1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

VID0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Nominal Output Voltage DACOUT

1.550

1.525

1.500

1.475

1.450

1.425

1.400

1.375

1.350

1.325

1.200

1.275

1.250

1.225

1.200

1.175

1.150

1.125

1.100

1.075

1.050

1.025

1.000

0.975

0.950

0.925

0.900

0.875

0.850

0.825

0.800

Shutdown

Note: (1) 0 : Connected to GND

(2) 1 : Open

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RT9245C

Absolute Maximum Ratings (Note 1)

z Supply Voltage, V_CC------------------------------------------------------------------------------------------- 7V

z Input, Output or I/O Voltage ---------------------------------------------------------------------------------- GND − 0.3V to V_CC+ 0.3V

z Power Dissipation, P_D@ T_A= 25°C

TSSOP-28-------------------------------------------------------------------------------------------------------- 1W

z Package Thermal Resistance (Note 4)

TSSOP-28, θ_JA-------------------------------------------------------------------------------------------------- 100°C/W

z Junction Temperature ------------------------------------------------------------------------------------------ 150°C

z Lead Temperature (Soldering, 10 sec.)-------------------------------------------------------------------- 260°C

z Storage Temperature Range --------------------------------------------------------------------------------- −65°C to 150°C

z ESD Susceptibility (Note 2)

HBM (Human Body Mode) ----------------------------------------------------------------------------------- 2kV

MM (Machine Mode) ------------------------------------------------------------------------------------------- 200V

Recommended Operating Conditions

(Note 3)

z Supply Voltage, V_CC------------------------------------------------------------------------------------------- 5V 10%

z Junction Temperature Range--------------------------------------------------------------------------------- −40°C to 125°C

z Ambient Temperature Range--------------------------------------------------------------------------------- −40°C to 85°C

Electrical Characteristics

(V_CC= 5V, T_A= 25°C, unless otherwise specified)

Parameter

Supply Current

Symbol

Test Conditions

Min

Typ

Max Units

V

CC

Nominal Supply Current

Power-On Reset

POR Threshold

Hysteresis

PWM 1,2,3,4 Open

--

12

16

mA

I

CC

4.0

0.2

0.94

--

4.2

0.5

1.0

50

4.5

--

V

CC

Rising

CCRTH

CCHYS

DVDTP

DVDHYS

Trip (Low to High)

Hysteresis

Enable

1.06

--

V

DVD

Threshold

mV

Oscillator

Free Running Frequency

Frequency Adjustable Range

Ramp Amplitude

170

50

--

200

--

230

400

--

kHz

V

f

R

= 20kΩ

OSC

RT

f

OSC_ADJ

1.9

1.0

64

ΔV

= 20kΩ

OSC

Ramp Valley

0.7

58

0.9

--

V

RV

Maximum Duty of Each Channel

RT Pin Voltage

70

1.1

%

1.0

V

R

= 20kΩ

≥ 1V

RT

Reference and DAC

--

+0.5

+5

%

−0.5

−5

V

DAC

DACOUT Voltage Accuracy

ΔV

DAC

mV

< 1V

DAC

To be continued

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RT9245C

Parameter

Symbol

Test Conditions

VRD 10.x

Min

--

Typ

--

Max

0.4

0.8

--

Units

V

ILDAC

DAC (VID0-VID125) Input Low

K8

--

V

VRD 10.x

K8

0.8

1.2

2.5

--

V

IHDAC

DAC (VID0-VID125) Input High

DAC (VID0-VID125) pull up resistor

DAC Pull Up Voltage

--

V

3.5

1.2

2.1

1.0

4.5

--

kΩ

V

VRD 10.x

K8

--

V

VOSS Pin Voltage

Error Amplifier

0.9

1.1

V

VOSS

R

VOSS

= 100kΩ

DC Gain

--

60

10

6

--

dB

Gain-Bandwidth Product

Slew Rate

GBW

SR

MHz

V/μs

COMP = 10pF

Current Sense GM Amplifier

CSN Full Scale Source Current

CSN Current for OCP

Protection

100

150

--

μA

I

ISPFSS

320

0.9

400

1.0

450

1.1

mV

V

Over-Voltage Trip (V − V

)

Δ

R

= 0Ω

ADJ

FB

DAC

OVT

IMAX Voltage

V

R = 20kΩ

IMAX

Power Good

Output Low Voltage

--

0.2

V

I

= 4mA

PGOODL PGOOD

Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are

for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the

operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for

extended periods may remain possibility to affect device reliability.

Note 2. Devices are ESD sensitive. Handling precaution recommended.

Note 3. The device is not guaranteed to function outside its operating conditions.

Note 4. θ_JAis measured in the natural convection at T_A= 25°C on a low effective single layer thermal conductivity test board of

JEDEC 51-3 thermal measurement standard.

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DS9245C-02 March 2007

RT9245C

Typical Operating Characteristics

PWM vs. V_COMP

Adjustable Frequency

700

70

60

50

40

30

20

10

0

R_RT= 16kΩ

600

500

400

300

200

100

0

10

20

30

40

50

60

70

0.5

1

1.5

2

2.5

3

3.5

R

(kW)

_RT(kΩ)

V_COMP(V)

Relationship Between Inductor

Current and V_ADJ

Power-Off @ I_OUT= 60A

CH1:(5V/Div)

CH2:(5V/Div)

PWM

CH1:(5V/Div)

CH2:(20V/Div)

V_SS

UGATE

CH3:(10V/Div)

CH4:(1V/Div)

V_ADJ

LGATE

V_COMP

CH3:(50mV/Div)

CH4:(20A/Div)

I_L

Time (10μs/Div)

Time (25ms/Div)

Power-On @ I_OUT= 60A

Ripple

CH1:(5V/Div)

CH2:(5V/Div)

V_SS

PWM

V_CORE

(5mV/Div)

UGATE

LGATE

CH3:(20V/Div)

CH4:(10V/Div)

L = 0.3μH, C = 5600μF

Time (10ms/Div)

Time (2.5μs/Div)

DS9245C-02 March 2007

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RT9245C

DVID at Rising

DVID at Falling

V_CORE

(500mV/Div)

V_CORE

VID125

(2V/Div)

Time (50μs/Div)

Transient Response

Transient Falling

(20mV/Div)

V_CORE

(20mV/Div)

Time (5ms/Div)

Time (500ns/Div)

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DS9245C-02 March 2007

RT9245C

Application Information

RT9245C is a multi-phaseDC/DC controller that precisely

regulates CPU core voltage and balances the current of

different power channels. The converter consisting of

RT9245C and its companion MOSFET driver RT9619

provides high quality CPU power and all protection

functions to meet the requirement of modern VRM.

VADJ = 8 x IX x RADJ

V_ADJis then subtracted from VID_DAC output as the real

reference voltage at non-inverting input of the error amplifier

as shown if Figure 1. Consequently, load line slope is

calculated as :

ΔV^CORE8 x R^ADJx DCR

LoadLine =

=

ΔICORE

N x RCSN

Voltage Control

RT9245C senses the CPU V_COREby SGND pin to sense

the return of CPU to minimize the voltage drop on PCB

trace at heavy load. OVP is sensed at FB pin. The internal

high accuracy VIDDAC provides the reference voltage for

VRD10.x compliance. Control loop consists of error

amplifier, multi-phase pulse width modulator, driver and

power components. As conventional voltage mode PWM

controller, the output voltage is locked at the V_REFof error

amplifier and the error signal is used as the control signal

of pulse width modulator. The PWM signals of different

channels are generated by comparison of EA output and

split-phase sawtooth wave. Power stage transforms VIN

to output by PWM signal on-time ratio.

where Nis the phase number of operation.

I

/4

VOSS

R

CSN

V

-

CORE

EA

+

V

ADJ

DAC

8I

X

R

ADJ

Figure 1. Load Line and Offset Function

Fault Detection

The chip detects FB for over voltage and power good

detection. The “hiccup mode” operation of over current

protection is adopted to reduce the short circuit current.

The in-rush current at the start up is suppressed by the

soft start circuit through clamping the pulse width and

output voltage.

Current Balance

RT9245C senses the inductor current via inductor'sDCR

for channel current balance and droop tuning. The

differential sensing GM amplifier converts the voltage on

the sense component (can be a sense resistor or the

DCR of the inductor) to current signal into internal balance

circuit.

Phase Setting and Converter Start Up

The current balance circuit sums and averages the current

signals and then produces the balancing signals injected

to pulse width modulator. If the current of some power

channel is larger than average, the balancing signal

reduces that channels pulse width to keep current balance.

The use of singleGM amplifier via time sharing technique

to sense all inductor currents can reduce the offset errors

and linearity variation between GMs. Thus it can greatly

improve signal processing especially when dealing with

such small signal as voltage drop across DCR.

RT9245C interfaces with companion MOSFET drivers (like

RT9619, RT9607 series) for correct converter initialization.

The tri-state PWM output (high, low and high impedance)

senses its interface voltage when IC POR acts (both VCC

andDVDtrip). The channel is enabled if the pin voltage is

1.2V less than VCC. Tie the PWM to VCC and the

corresponding current sense pins to GND or left float if

the channel is unused. For example, for 3-Channel

application, connect PWM4 high.

Current Sensing Setting

Droop & Load Line Setting

RT9245C senses the current flowing through inductor via

itsDCR for channel current balance and droop tuning.

RT9245C injects averaged current I_Xinto the resistor R_ADJ

connected to ADJ pin to generate a load-current-

dependent voltage R_ADJfor droop setting :

DS9245C-02 March 2007

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13

RT9245C

The differential sensingGM amplifier converts the voltage

on the sense component (can be a sense resistor or the

DCR of the inductor) to current signal into internal circuit

(see Figure 2).

Figure 5 shows the time sharing technique ofGM amplifier.

We apply test signal at phase 4 and observe the waveforms

at both pins of GM amplifier. The waveforms show time

sharing mechanism and the perfomance of GM to hold

both input pins equal when the shared time is on.

L

V

C

= R×C V = DCR×I

I =

X

C

L

DCR

R

CSN

Time Sharing of GM

L

DCR

CH1:(2V/Div)

+V -

C

CH2:(50mV/Div)

CH3:(50mV/Div)

R

C

+

-

PWM3

R

CSN

GMx

V_CSP4

I

x

Figure 2. Current Sense Circuit

V_CSP4

and

V_CSN

Figure 3 is the test circuit for GM. We apply test signal at

GM inputs and observe its signal process output at ADJ

pin. Figure 4 shows the variation of signal processing of

all channels. We observe zero offsets and good linearity

between phases.

Time (1μs/Div)

Figure 5

Over Current Protection

CSPX

RT9245C uses an external resistor R_IMAXto set a

programmable over current trip point. OCP comparator

compares each inductor current with this reference current.

RT9245C uses hiccup mode to eliminate fault detection

of OCP or reduce output current when output is shorted

to ground.

V

C

+

ADJ

SUM/M

ADJ

MUX

GM

-

CSN

+

R

CSN

1k

R

1k

V

ADJ

-

I

x

Figure 3. The Test Circuit of GM

1

2

V^IMAX

1

3

I^Lx DCR

x

⇔

x

RIMAX

RCSN

GM

300

250

200

150

100

50

OCP Comparator

1/3 I

1/2 I

+

-

X

IMAX

OCP

Setting

V

IMX

R

IMX

0

25

50

75

100

125

150

Figure 6. Over Current Comparator

V_C(mV)

Figure 4. The Linearity of GMx

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DS9245C-02 March 2007

RT9245C

Over Current Protection

For some case with preferable current ratio instead of

current balance, the corresponding technique is provided.

Due to different physical environment of each channel, it

is necessary to slightly adjust current loading between

channels. Figure 9 shows the application circuit ofGM for

current ratio requirement. Applying KVL along L+DCR

branch and R1+C//R2 branch :

CH1:(5V/Div)

CH2:(5V/Div)

PWM

dI_L

dt

V_C

R₂

dV_C

dt

L

+DCR×I_L= R₁(

dV_CR₁+R₂

+ C

)+ V_C

V_SS

= R₁C

+

V_C

dt

R₂

R2

R₁+R₂

For V_C

=

DCR×I_L

Time (25ms/Div)

Figure 7. The Over Current Protection in the soft start

interval

Look for its corresponding conditions :

dI

L

+DCR×I = (R1//R2)×C×DCR×

+DCR×I

L

dt

L

Over Current Protection

Let

= (R1//R2)×C

DCR

CH1:(5V/Div)

CH2:(5V/Div)

L

= (R1//R2)×C

Thus if

Then

DCR

PWM

R2

V_C

=

×DCR×I_L

R1+R2

With internal current balance function, this phase would

share (R₁+R₂)/R₂times current than other phases.

Figure 10 & 11 show different settings for the power stages.

Figure 12 shows the performance of current ratio compared

with conventional current balance function in Figure 13.

V_SS

Time (25ms/Div)

I

L

Figure 8. Over Current Protection at steady state

0.3uH

0.6m

Current Ratio Setting

470

1uF

470

I

L

DCR

Figure 10. GM4 Setting for current ratio function

+V -

C

I

R1

L

C

0.3uH

0.6m

R2

Figure 9. Application circuit for current ratio setting

DS9245C-02 March 2007

470

1uF

Figure 11. GM1~3 Setting for current ratio function

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RT9245C

Load Line without dead zone at light loads

Current Ratio Function

35

30

25

20

15

10

5

1.31

I_L4

1.3

1.29

1.28

1.27

1.26

1.25

1.24

1.23

w/o Dead Zone Compensation

R_CSNopen

I_L3

I_L2

I_L1

R_CSN= 82k

w/i Dead Zone Compensation

0

15

30

45

60

75

90

0

5

10

15

20

25

I_OUT(A)

Figure 14

Figure 12

LX

R

LX

I

LX

Current Balance Function

30

25

20

15

10

5

R

X

C

X

I_L3

V

OUT

+

-

V

I_L4

X

+

-

I_L1

R

CSN

GMx

Ix

I_L2

R

CSN2

Figure 15. Application circuit of GM

Referring to Figure 15, I_Xis expressed as :

0

20

40

60

80

100

V^OUT

I^LX_50%x R^LXI^LX_50%x R^LX

(1)

I^X=

+

I_OUT(A)

Figure 13

Dead Zone Elimination

RCSN2

RCSN

where I_{LX_50%}is the of inductor current at 50% period. To

make sure RT9245C could sense the inductor current,

right hand side of Equation (1) should always be positive:

RT9245C samples and holds inductor current at 50%

period by time-sharing sourcing a current I_Xto R_CSN. At

light load condition when inductor current is not balance,

voltage V_Xacross the sensing capacitor would be negative.

It needs a negative I_Xto sense the voltage. However,

RT9245C CANNOT provide a negative I_Xand consequently

cannot sense negative inductor current. This results in

dead zone of load line performance as shown in Figure

14. Therefore a technique as shown in Figure 15 is required

to eliminate the dead zone of load line at light load

condition.

V^OUT

I^LX_50%x R^LXI^LX_50%x R^LX

(2)

+

≥ 0

RCSN2

RCSN

Since R_CSN2>> R_CSNin practical application, Equation (2)

could be simplified as :

V^OUT

I^LX_50%x R^LX

≥

RCSN2

RCSN

Figure 14 shows that dead zone of load line at light load

is eliminated by applying this technique.

www.richtek.com

16

DS9245C-02 March 2007

RT9245C

VID on the Fly

Output Voltage Offset Function

With external pull up resistors tied to VID pins, RT9245C

converters different VID codes from CPU into output

voltage. Figure 16 and Figure 17 show the waveforms of

VID on the fly function.

To meet Intel^®requirement of initial offset of load line,

RT9245C provides programmable initial offset function.

External resistor R_VOSSand voltage source at VOSS pin

V_VOSS

generate offset current

I_VOSS

=

R_VOSS

, where V_VOSSis 1V typical. One quarter of I_VOSSflows

through RB1 as shown in Figure 18. Error amplifier would

hold the inverting pin equal to V_DAC- V_ADJ. Thus output

voltage is subtracted from V_DAC- V_ADJfor a constant offset

VID on the Fly (Falling)

PWM

V_CORE

voltage.

V_CORE= V_DAC- V_ADJ

R_FB1

4×R_VOSS

V_FB

-

A positive output voltage offset is possible by connecting

R_VOSSto VDD instead of to GND. Please note that when

R_VOSSis connected to VDD, V_VOSSis V_DD− 2V typically

and half of I_VOSSflows through R_FB1. V_COREis rewritten as:

CH3:(500mV/Div)

CH4:(1V/Div)

CH1:(5V/Div)

CH2:(500mV/Div)

VID125

R^FB1

V^CORE= V^DAC- V^ADJ+

RVOSS

V_DAC= 1.500, I_OUT= 5A

Time (25μs/Div)

Voltage Offset Function

Figure 16

1.284

1.282

1.28

VID on the Fly (Rising)

1.278

1.276

1.274

1.272

1.27

PWM

V_CORE

V_FB

CH1:(5V/Div)

CH2:(500mV/Div)

CH3:(500mV/Div)

CH4:(1V/Div)

1.268

50

60

70

80

90

100

110

VID125

R

(k )

ٛ

_OSS(kΩ)

V_DAC= 1.500, I_OUT= 5A

Figure 19

Time (25μs/Div)

Figure 17

Load Line Setting and Thermal Compensation

V_ADJ= 8 x AVG(I_X) x R_ADJ

1/4 I

VOSS

V_OUT= V_DAC- V_ADJ

RB1

AVG(I_X) is a PTC current. By properly use anNTC resistor

at ADJ. Load line can be thermally compensated.

-

EA

+

V

-V

DAC ADJ

Figure 18. Offset Setting

DS9245C-02 March 2007

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17

RT9245C

PGOOD Function

If the fault condition is OV, V_(SS)and PGOODwill be pulled

low immediately also. RT9245C will try to turn on low

side MOSFET and turn off high side MOSFET. V_OUTwill

fall quickly to protect CPU from high voltage. The typical

waveform is shown in Figure 23.

During start-up, RT9245C will detect 5V_CCand 12V_IN

(throughDVDpin). In Figure 21, 5V_CCor 12V_INis not ready

during T1. V_(SS)(in Figure 20) is pulled toGNDby FAULT.

V_(EAP)is also equal to GND. V_(FB)and V_OUTwill try to

follow V_(EAP)thus both V_(FB)and V_OUTare equal to GND

during T1. During T2, both 5V_CCand 12V_INare ready,

FAULT = low, OPSS starts charging up C_SS. In the design

of RT9245C, I_SS(the maximal current sink and source

capability of OPSS) is limited and time-variant. During T2

(V1 = 0.4V > V_(SS)> 0), I_SS(T2) is equal to about 10uA.

Z2

V

-

FB

N1

Z1

OUT

EA

COMP

+

5V

CC

OPSS

EAP

V

+

DAC

-

V1

T2 = C^SSx

≅ 4x10⁴x CSS

I^SS(T2)

SS

FAULT

C

After V_(SS)> V1, I_SSchanges to about 20uA. The rising

speed of V_(SS)becomes about 2 times faster than in T1.

In Figure 20, MOSFETN1 will turn on only if V_(SS)> V_{TH_N1}

(threshold voltage of N1) ≅ 0.7V = V2. Before N1 turns

on, V_(EAP)is still 0V.

SS

Figure 20. Soft Start Circuit

5V _ready

CC

and DVD_ready

(V2- V1)

T3 = C^SSx

≅ 1.5x10⁴x CSS

I^SS(T3)

PGOOD

After V_(SS)> V2, MOSFETN1 turns on, V_(EAP)starts rising.

I_SS(T4) is still equal to about 20uA. V_(SS,EAP)is equal to

V_{TH_N1}. Due to the body effect of MOSFET N1, V_{TH_N1}

increases with higher V_(EAP). For example, if V_OUTtarget

is 1.4V, V_(SS,EAP)will be equal to about 0.7V at the

beginning of T4 and equal to about 1.1V at the end of T4.

V4

V3

V

(SS)

V

OUT

V2

V1

(V4 - V2)

T4 = C^SSx

≅ 9x10⁴x CSS

I^SS(T4)

T2

T3

T4

T5

T6

T1

Figure 21. Soft Start Waveform

At the end of T4, V_OUTis very close to the target (within

the range of 40mV). An internal 1ms timer starts. After

about 1ms(T5), The open-drain output PGOODreleases.

PGOOD

After PGOODreleases, I_SS(T6) becomes about 320uAto

accelerate OPSS. RT9245C enters normal operation mode

and is capable to follow VID on the fly.

V

(SS)

When any of the fault conditions happens, V_(SS)and

PGOODwill be pulled low immediately. If the fault condition

is one of 5V_CClow, DVD low, OC or VID_OFF, RT9245C

will try to turn off both high side MOSFET and low side

MOSFET. V_OUTwill fall slowly to avoid negative V_OUT. The

typical waveform is shown in Figure 22.

V

OUT

5V _Low + DVD_Low + OC + VID_OFF

CC

Figure 22. Waveform for 5V_CC_Low, DVD_Low, OC or

VID_OFF

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18

DS9245C-02 March 2007

RT9245C

EA Rising Slew Rate

PGOOD

V_FB

V

(SS)

V

OUT

OV

CH1:(500mV/Div)

CH2:(2V/Div)

Figure 23. Waveform for OV

V_COMP

Error Amplifier Characteristic

Time (250ns/Div)

For fast response of converter to meet stringent output

current transient response, RT9245C provides large slew

rate capability and high gain-bandwidth performance.

Figure 25. EA Falling Transient with 10pF Loading;

Slew Rate = 8V/us

4.7k

B

EA Falling Slew Rate

-

A

EA

+

V

DAC

V_FB

Figure 26. Gain-Bandwidth Measurement by signalA

divided by signal B

CH1:(500mV/Div)

CH2:(2V/Div)

V_COMP

Time (250ns/Div)

Figure 24. EA Rising Transient with 10pF Loading; Slew

Rate = 8V/us

DS9245C-02 March 2007

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19

RT9245C

0dB

180°

Figure 27. EA Frequency Response with closed loop gain set at 0db to observe gain-bandwidth product; -3dB at

10.86MHz

Design Procedure Suggestion

PCB Layout

a.Output filter pole and zero (Inductor, output capacitor

value & ESR).

a.Kelvin sense for current sense GM amplifier input.

b.Refer to layout guide for other items.

b.Error amplifier compensation & sawtooth wave amp-

litude (compensation network).

Voltage Loop Setting

Design Example

c.Kelvin sense for V_CORE

.

Given :

Current Loop Setting

Apply for four phase converter

a.GM amplifier S/H current (current sense component

DCR, CSN pin external resistor value).

V_IN= 12V

b.Over-current protection trip point (R_IMAXresistor).

V_CORE= 1.4V

I_LOAD= 30A to 125A

VRM Load Line Setting

V_DROOP= 95mV with load (1mΩ Load Line)

OCP trip point set at 40A for each channel (S/H)

DCR = 1mΩ of inductor at 25°C

L = 0.3μH

a.Droop amplitude (ADJ pin resistor).

b.No load offset (R_CSN2

)

c.DAC offset voltage setting (VOSS pin & compen- sation

network resistor RB1).

C_OUT= 5600μF with 1mΩ equivalent ESR.

Power Sequence & SS

DVD pin external resistor and SS pin capacitor.

www.richtek.com

20

DS9245C-02 March 2007

RT9245C

Figure 30. The Frequency Response with Middle Load

Figure 31. The Frequency Response with Heavy Load

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22

DS9245C-02 March 2007

RT9245C

Layout Guide

Place the high-power switching components first, and separate them from sensitive nodes.

1. Most critical path: the current sense circuit is the most sensitive part of the converter. The current sense

resistors tied to CSP1,2,3,4 and CSN should be located not more than 0.5 inch from the IC and away from

the noise switching nodes. The PCB trace of sense nodes should be parallel and as short as possible.

2. Switching ripple current path:

a. Input capacitor to high side MOSFET.

b. Low side MOSFET to output capacitor.

c. The return path of input and output capacitor.

d. Separate the power and signalGND.

e. The switching nodes (the connection node of high/low side MOSFET and inductor) is the most noisy points.

Keep them away from sensitive small-signal node.

f. Reduce parasitic R, L by minimum length, enough copper thickness and avoiding of via.

3. MOSFET driver should be closed to MOSFET.

4. The compensation, bypass and other function setting components should be near the IC and away from the noisy

power path.

L1

SW1

V_OUT

V_IN

R_IN

C_OUT

R_L

C_IN

V

L2

SW2

Figure 32. Power Stage Ripple Current Path

DS9245C-02 March 2007

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23

RT9245C

Next to IC

C

+12V or +5V

+12V

VCC

PWM

+5V

VCC

IN

0.1uF

C

BP

RT

BOOT

UGATE

PHASE

VOSS

Next to IC

COMP

L

O1

V_CORE

C

R

RT9245C

OUT

CSN

RT9619

LGATE

PGND

C

IN

R

C

CSN

Locate next

to FB Pin

FB

R

FB

CSPx

ADJ

SGND

Locate near MOSFETs

For Thermal Couple

GND

Figure 33. Layout Consideration

Figure 34. Layout of power stage

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24

DS9245C-02 March 2007

RT9245C

Outline Dimension

D

L

E

E1

e

A2

A

A1

b

Dimensions In Millimeters

Dimensions In Inches

Symbol

Min

Max

Min

Max

A

A1

A2

b

0.850

0.050

0.800

0.178

9.601

1.200

0.152

1.050

0.305

9.804

0.033

0.002

0.031

0.007

0.378

0.047

0.006

0.041

0.012

0.386

D

e

0.650

0.026

E

6.300

4.293

0.450

6.500

4.496

0.762

0.248

0.169

0.018

0.256

0.177

0.030

E1

L

28-Lead TSSOP Plastic Package

Richtek Technology Corporation

Headquarter

Richtek Technology Corporation

Taipei Office (Marketing)

5F, No. 20, Taiyuen Street, Chupei City

Hsinchu, Taiwan, R.O.C.

8F, No. 137, Lane 235, Paochiao Road, Hsintien City

Taipei County, Taiwan, R.O.C.

Tel: (8863)5526789 Fax: (8863)5526611

Tel: (8862)89191466 Fax: (8862)89191465

Email: marketing@richtek.com

DS9245C-02 March 2007

www.richtek.com

25


型号：	RT9245CPC
厂家：	RICHTEK TECHNOLOGY CORPORATION
描述：	Multi-Phase PWM Controller for CPU Core Power Supply 多相PWM控制器，用于CPU核心供电多相元件控制器
文件：	总25页 (文件大小：545K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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