RT9245PC [RICHTEK]
Multi-Phase PWM Controller for CPU Core Power Supply; 多相PWM控制器，用于CPU核心供电
| 型号： | RT9245PC |
| 厂家： | 
RICHTEK TECHNOLOGY CORPORATION |
| 描述： | Multi-Phase PWM Controller for CPU Core Power Supply |
| 文件： | 总22页 (文件大小：421K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RT9245
Multi-Phase PWM Controller for CPU Core Power Supply
General Description
Features
z Multi-Phase Power Conversion with Automatic
RT9245 is a multi-phase buckDC/DC controller integrated
with all control functions for Intel® GHz CPU which is
VRD10.X-compliant. The RT9245 could be operated with
2, 3 or 4 buck switching stages operating in interleaved
phase set automatically. The multiphase architecture
provides high output current while maintaining low power
dissipation on power devices and low stress on input and
output capacitors. The high equivalent operating frequency
also reduces the component dimension and the output
voltage ripple in load transient.
Phase Selection
z 6-bits VRD10.x DAC Output with Active Droop
Compensation for Fast Load Transient
z Smooth VCORE Transition at VID Jump
z Power Stage Thermal Balance by DCR Current
Sense
z Hiccup Mode Over-Current Protection
z Programmable Switching Frequency (50kHz to
400kHz per Phase), Under-Voltage Lockout and Soft-
Start
RT9245 implements both voltage and current loops to
achieve good regulation, response and power stage
thermal balance.
z High Ripple Frequency Times Channel Number
z 28-TSSOP Package
z RoHS Compliant and 100% Lead (Pb)-Free
RT9245 applies the DCR sensing technology newly. The
RT9245 extracts the ESR of output inductor as sense
component to deliver a precise load line regulation and
good thermal balance for next generation processor
application.
Applications
z Intel® Processors Voltage Regulator : VRD10.x
z Low Output Voltage, High CurrentDC-DC Converters
z Voltage Regulator Modules
Current sense setting, droop tuning, VCORE initial offset
and over current protection are independent on
compensation circuit of voltage loop. The feature greatly
facilitates the flexibility of CPU power supply design and
tuning. TheDAC output of RT9245 supports VRD10.x with
6-bit VID input, precise offset value & smooth VCORE
transient at VID jump. The IC monitors the VCORE voltage
for PGOODand over-voltage protection. Soft-start, over-
current protection and programmable under-voltage lockout
are also provided to assure the safety of microprocessor
and power system. The RT9245 comes to a small footprint
package TSSOP-28.
Pin Configurations
(TOP VIEW)
VID4
VID3
VID2
VCC
28
27
26
25
24
23
22
21
PWM1
PWM2
PWM3
PWM4
CSP4
CSP2
CSP3
CSP1
GND
ADJ
NC
CSN
IMAX
2
3
4
5
6
7
8
VID1
VID0
VID125
SGND
FB
COMP
PGOOD
DVD
SS
RT
VOSS
9
20
19
18
17
16
15
10
11
12
13
14
Ordering Information
RT9245
TSSOP-28
Note :
RichTek Pb-free and Green products are :
Package Type
C : TSSOP-28
Operating Temperature Range
P : Pb Free with Commercial Standard
G : Green (Halogen Free with Commer-
cial Standard)
`RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
`Suitable for use in SnPb or Pb-free soldering processes.
`100% matte tin (Sn) plating.
DS9245-06 March 2007
www.richtek.com
1
RT9245
Typical Application Circuit
+
+
+
+
+
+
+
+
+
www.richtek.com
2
DS9245-06 March 2007
RT9245
Functional Pin Description
VID4 (Pin 1), VID3 (Pin 2), VID2 (Pin 3), VID1 (Pin 4),
VID0 (Pin 5) & VID125 (Pin 6)
IMAX (Pin 15)
Programmable over currert setting.
DAC voltage identification inputs for VRD10.x. These pins
are internally pulled to 1.2V if left open.
CSN (Pin 16)
Current sense negative input of all channels.
SGND (Pin 7)
NC (Pin 17)
VCORE differential sense negative input.
No Connection.
FB (Pin 8)
ADJ (Pin 18)
Inverting input of the internal error amplifier.
Current sense output for active droop adjust. Connect a
resistor from this pin to GND to set the load droop.
COMP (Pin 9)
Output of the error amplifier and input of the PWM
comparator.
GND (Pin 19)
Ground for the IC.
PGOOD (Pin 10)
CSP1 (Pin 20), CSP2 (Pin 22), CSP3 (Pin 21) & CSP4
(Pin 23)
Power good open-drain output.
DVD (Pin 11)
Current sense positive inputs for individual converter
channel current sense.
Programmable power UVLO detection input. Trip threshold
= 1.2V at VDVD rising.
PWM1 (Pin 27), PWM2 (Pin 26), PWM3 (Pin 25) &
PWM4 (Pin 24)
SS (Pin 12)
Connect this SS pin to GND with a capacitor to set the
soft-start time interval. Pulling this pin below 1V (ramp
valley of sawtooth wave in pulse width modulator) would
make all PWMs low, turn on low side MOSFETs, and turn
off high side MOSFETs.
PWM outputs for each driven channel. Connect these pins
to the PWM input of the MOSFET driver. For systems
which use 3 channels, connect PWM4 high. Two channel
systems connect PWM3 high.
VCC (Pin 28)
RT (Pin 13)
IC power supply. Connect this pin to a 5V supply.
Switching frequency setting. Connect this pin toGNDwith
a resistor to set the frequency.
VOSS (Pin 14)
VCORE initial value offset. Connect this pin to GND with a
resistor to set the negative offset value. Connect this pin
to VCC to set positive offset value.
DS9245-06 March 2007
www.richtek.com
3
RT9245
Function Block Diagram
www.richtek.com
4
DS9245-06 March 2007
RT9245
Table 1. Output Voltage Program
Pin Name
Nominal Output Voltage DACOUT
VID4
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
VID3
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
VID2
1
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
VID1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
0
0
1
1
1
1
VID0
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
0
VID125
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
No CPU
0.8375V
0.850V
0.8625V
0.875V
0.8875V
0.900V
0.9125V
0.925V
0.9375V
0.950V
0.9625V
0.975V
0.9875V
1.000V
1.0125V
1.025V
1.0375V
1.050V
1.0625V
1.075V
1.0875V
1.100V
1.1125V
1.125V
1.1375V
1.150V
1.1625V
1.175V
1.1875V
1.200V
1.2125V
To be continued
DS9245-06 March 2007
www.richtek.com
5
RT9245
Table 1. Output Voltage Program
Pin Name
Nominal Output Voltage DACOUT
VID4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
VID3
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
VID2
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
VID1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
VID0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
VID125
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.225V
1.2375V
1.250V
1.2625V
1.275V
1.2875V
1.300V
1.3125V
1.325V
1.3375V
1.350V
1.3625V
1.375V
1.3875V
1.400V
1.4125V
1.425V
1.4375V
1.450V
1.4625V
1.475V
1.4875V
1.500V
1.5125V
1.525V
1.5375V
1.550V
1.5625V
1.575V
1.5875V
1.600V
Note: (1) 0 : Connected to GND
(2) 1 : Open
(3) X : Don't Care
www.richtek.com
6
DS9245-06 March 2007
RT9245
Absolute Maximum Ratings (Note 1)
z Supply Voltage, VCC ------------------------------------------------------------------------------------------- 7V
z Input, Output or I/O Voltage ---------------------------------------------------------------------------------- GND − 0.3V to VCC + 0.3V
z Package Thermal Resistance
TSSOP-28, θJA -------------------------------------------------------------------------------------------------- 100°C/W
z Junction Temperature ------------------------------------------------------------------------------------------ 150°C
z Lead Temperature (Soldering, 10 sec.)-------------------------------------------------------------------- 260°C
z Storage Temperature Range --------------------------------------------------------------------------------- −65°C to 150°C
z ESD Susceptibility (Note 2)
HBM (Human Body Mode) ----------------------------------------------------------------------------------- 2kV
MM (Machine Mode) ------------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions
(Note 3)
z Supply Voltage, VCC ------------------------------------------------------------------------------------------- 5V 10%
z Ambient Temperature Range--------------------------------------------------------------------------------- 0°C to 70°C
z Junction Temperature Range--------------------------------------------------------------------------------- 0°C to 125°C
Electrical Characteristics
(VCC = 5V, TA = 25°C, unless otherwise specified)
Parameter
Supply Current
Symbol
Test Conditions
Min
Typ
Max Units
V
CC
Nominal Supply Current
Power-On Reset
POR Threshold
Hysteresis
PWM 1,2,3,4 Open
--
12
16
mA
I
CC
4.0
0.2
1.1
--
4.2
0.5
1.2
50
4.5
--
V
V
V
V
V
V
V
CC
Rising
CCRTH
CCHYS
DVDTP
DVDHYS
Trip (Low to High)
Hysteresis
Enable
1.3
--
V
V
DVD
Threshold
mV
Oscillator
Free Running Frequency
Frequency Adjustable Range
Ramp Amplitude
170
50
--
200
--
230
400
--
kHz
kHz
V
f
R
R
= 32kΩ
OSC
RT
f
OSC_ADJ
1.9
1.0
66
ΔV
= 32kΩ
OSC
RT
Ramp Valley
0.7
62
1.4
--
V
V
RV
Maximum On-Time of Each Channel
RT Pin Voltage
75
1.8
%
1.60
V
V
R
RT
= 32kΩ
≥ 1V
RT
Reference and DAC
--
--
+1
+10
0.4
--
%
mV
V
−1
−10
--
V
V
DAC
DACOUT Voltage Accuracy
ΔV
DAC
< 1V
DAC
DAC (VID0-VID125) Input Low
DAC (VID0-VID125) Input High
DAC (VID0-VID125) Bias Current
VOSS Pin Voltage
--
V
V
ILDAC
0.8
25
--
V
IHDAC
50
1.65
75
μA
V
I
BIAS_DAC
1.5
1.8
V
R
VOSS
= 100kΩ
VOSS
To be continued
DS9245-06 March 2007
www.richtek.com
7
RT9245
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
Error Amplifier
DC Gain
--
--
--
85
10
3
--
--
--
dB
Gain-Bandwidth Product
Slew Rate
GBW
SR
MHz
V/μs
COMP = 10pF
Current Sense GM Amplifier
CSN Full Scale Source Current
CSN Current for OCP
Protection
100
150
--
--
--
--
μA
μA
I
ISPFSS
SS Current
8
13
18
150
1.8
μA
%
V
I
V
= 1V
SS
SS
Over-Voltage Trip (VSEN/DACOUT)
IMAX Voltage
130
1.4
140
1.60
Δ
OVT
V
R
= 32k
IMAX
IMAX
Power Good
Output Low Voltage
--
--
0.2
V
V
I
= 4mA
PGOODL
PG
Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are
for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. The device is not guaranteed to function outside its operating conditions.
www.richtek.com
8
DS9245-06 March 2007
RT9245
Typical Operating Characteristics
GM1
GM2
300
300
250
200
150
100
50
VADJ
VADJ
250
200
VP
VP
150
100
VN
VN
50
0
0
0
25
50
75
100
125
150
0
25
50
75
100
125
150
Vx (mV)
Vx (mV)
GM3
GM4
300
250
200
150
100
50
300
250
200
150
100
50
VADJ
VADJ
VP
VP
VN
VN
0
0
0
25
50
75
100
125
150
0
25
50
75
100
125
150
Vx (mV)
Vx (mV)
Adjustable Frequency
Linearity of each PWM
450
400
350
300
250
200
150
100
50
3
2.8
2.6
2.4
2.2
2
PWM2
PWM3
PWM1
PWM4
1.8
1.6
1.4
1.2
1
fOSC = 200k
0
0
25
50
75
R
100
125
150
175
0
500
1000 1500 2000 2500 3000 3500
Pulse Width (ns)
RT (kΩ)
DS9245-06 March 2007
www.richtek.com
9
RT9245
Load Transient Response
Load Transient Response
VCORE
VCORE
Phase1
Phase2
Phase
CH1: (500mV/Div)
IOUT
VADJ
CH2: (10V/Div)
CH3: (50A/Div)
CH4: (100mV/Div)
Phase3
CH1: (500mV/Div), CH2: (10V/Div)
CH3: (10V/Div), CH4: (10V/Div)
Time (5μs/Div)
Time (5μs/Div)
Relationship Between Inductor
Current and VADJ
Power-Off @ IOUT = 60A
CH1:(5V/Div)
CH2:(5V/Div)
PWM
PWM
CH1:(5V/Div)
CH2:(20V/Div)
VSS
UGATE
CH3:(10V/Div)
CH4:(1V/Div)
VADJ
LGATE
VCOMP
CH3:(50mV/Div)
CH4:(20A/Div)
IL
Time (10μs/Div)
Time (25ms/Div)
Power-On @ IOUT = 60A
CH1:(5V/Div)
CH2:(5V/Div)
VSS
PWM
UGATE
LGATE
CH3:(20V/Div)
CH4:(10V/Div)
Time (10ms/Div)
www.richtek.com
10
DS9245-06 March 2007
RT9245
Application Information
Load Droop
RT9245 is a multi-phase DC/DC controller that precisely
regulates CPU core voltage and balances the current of
different power channels. The converter consisting of
RT9245 and its companion MOSFET driver RT9603/
RT9603A provides high quality CPUpower and all
protection functions to meet the requirement of modern
VRM.
The sensed power channel current signals regulate the
reference of DAC to form an output voltage droop
proportional to the load current. The droop or so call “active
voltage positioning” can reduce the output voltage ripple
at load transient and the LC filter size.
Fault Detection
The chip detects FB for over voltage and power good
detection. The “hiccup mode” operation of over current
protection is adopted to reduce the short circuit current.
The in-rush current at the start up is suppressed by the
soft start circuit through clamping the pulse width and
output voltage.
Voltage Control
RT9245 senses the CPU VCORE by SGND pin to sense
the return of CPU to minimize the voltage drop on PCB
trace at heavy load. OVP is sensed at FB pin. The internal
high accuracy VIDDAC provides the reference voltage for
VRD10.X compliance. Control loop consists of error
amplifier, multi-phase pulse width modulator, driver and
power components. As conventional voltage mode PWM
controller, the output voltage is locked at the VREF of
error amplifier and the error signal is used as the control
signal of pulse width modulator. The PWM signals of
different channels are generated by comparison of EA
output and split-phase sawtooth wave. Power stage
transforms VIN to output by PWM signal on-time ratio.
Phase Setting and Converter Start Up
RT9245 interfaces with companion MOSFET drivers (like
RT9603, RT9602 series) for correct converter initialization.
The tri-state PWM output (high, low and high impedance)
senses its interface voltage when IC POR acts (both VCC
andDVDtrip). The channel is enabled if the pin voltage is
1.2V less than VCC. Tie the PWM to VCC and the
corresponding current sense pins to GND or left float if
the channel is unused. For example, for 3-Channel
application, connect PWM4 high.
Current Balance
RT9245 senses the inductor current via inductor's DCR
for channel current balance and droop tuning. The
differential sensing GM amplifier converts the voltage on
the sense component (can be a sense resistor or the
DCR of the inductor) to current signal into internal balance
circuit.
Current Sensing Setting
RT9245 senses the current flowing through inductor via
itsDCR for channel current balance and droop tuning. The
differential sensing GM amplifier converts the voltage on
the sense component (can be a sense resistor or the
DCR of the inductor) to current signal into internal circuit
(see Figure 1).
The current balance circuit sums and averages the current
signals and then produces the balancing signals injected
to pulse width modulator. If the current of some power
channel is larger than average, the balancing signal
reduces that channels pulse width to keep current balance.
The use of singleGM amplifier via time sharing technique
to sense all inductor currents can reduce the offset errors
and linearity variation between GMs. Thus it can greatly
improve signal processing especially when dealing with
such small signal as voltage drop across DCR.
L
V
C
= R×C V = DCR×I
I =
X
C
L
DCR
R
CSN
DCR
L
R
C
+
-
R
CSN
GMx
I
x
Figure 1. Current Sense Circuit
DS9245-06 March 2007
www.richtek.com
11
RT9245
Figure 2 is the test circuit for GM. We apply test signal at
GM inputs and observe its signal process output at ADJ
pin. Figure 3 shows the variation of signal processing of
all channels. We observe zero offsets and good linearity
between phases.
Time Sharing of GM
CH1:(2V/Div)
CH2:(50mV/Div)
CH3:(50mV/Div)
PWM3
L
DCR
VCSP4
VCSP4
and
VCSN
VCSN
ESR
R
V
X
V
V
CSP
+
-
CSN
CSN
GMx
Time (1μs/Div)
1k
I
Figure 4
x
Figure 2. The Test Circuit of GM
Over Current Protection
RT9245 uses an external resistor RIMAX to set a
programmable over current trip point. OCP comparator
compares each inductor current with this reference current.
RT9245 uses hiccup mode to eliminate fault detection of
OCP or reduce output current when output is shorted to
ground.
GM
300
250
200
150
100
50
1
V
1
I ×DCR
L
IMAX
×
⇔
×
2 R
3 R
COMMON
IMAX
OCP Comparator
1/3 I
1/2 I
+
-
X
IMAX
0
0
25
50
75
100
125
150
Figure 5. Over Current Comparator
Vx (mV)
Over Current Protection
Figure 3. The Linearity of GMx
CH1:(5V/Div)
CH2:(5V/Div)
Figure 4 shows the time sharing technique ofGM amplifier.
We apply test signal at phase 4 and observe the waveforms
at both pins of GM amplifier. The waveforms show time
sharing mechanism and the perfomance of GM to hold
both input pins equal when the shared time is on.
PWM
VSS
Time (25ms/Div)
Figure 6. The Over Current Protection in the soft start
interval
www.richtek.com
12
DS9245-06 March 2007
RT9245
L
= (R1//R2)×C
Thus if
Then
Over Current Protection
DCR
CH1:(5V/Div)
CH2:(5V/Div)
R2
R1+R2
VC
=
×DCR×IL
PWM
With internal current balance function, this phase would
share (R1+R2)/R2 times current than other phases.
Figure 9 &10 show different settings for the power stages.
Figure 11 shows the performance of current ratio compared
with conventional current balance function in Figure 12.
VSS
Time (25ms/Div)
Figure 7. Over Current Protection at steady state
Current Ratio Setting
Figure 9. GM4 Setting for current ratio function
Figure 8. Application circuit for current ratio setting
Figure 10. GM1~3 Setting for current ratio function
For some case with preferable current ratio instead of
current balance, the corresponding technique is provided.
Due to different physical environment of each channel, it
is necessary to slightly adjust current loading between
channels. Figure 8 shows the application circuit ofGM for
current ratio requirement. Applying KVL along L+DCR
branch and R1+C//R2 branch :
Current Ratio Function
35
IL4
30
25
20
IL3
dIL
dt
VC
R2
dVC
dt
IL2
IL1
L
+DCR×IL = R1(
dVC R1 +R2
+ C
)+ VC
15
10
5
= R1C
+
VC
dt
R2
R2
R1 +R2
For VC
=
DCR×IL
0
0
15
30
45
60
75
90
Look for its corresponding conditions :
IOUT (A)
dI
dI
L
L
L
+DCR×I = (R1//R2)×C×DCR×
+DCR×I
L
L
dt
dt
Figure 11
L
Let
= (R1//R2)×C
DCR
DS9245-06 March 2007
www.richtek.com
13
RT9245
Current Balance Function
Assume the negative inductor valley current is −5A at no
load, then for
30
25
20
15
10
5
IL3
IL4
RCSN1 = 330Ω, RADJ = 160Ω, VOUT = 1.300
1.3V
−5A ×1mΩ
330Ω
IL1
≥
RCSN2
IL2
RCSN2 ≤ 85.8kΩ
Choose RCSN2 = 82kΩ
Load Line without dead zone at light loads
1.31
0
0
20
40
60
80
100
1.3
IOUT (A)
1.29
1.28
1.27
1.26
1.25
1.24
1.23
Figure 12
L
RCSN2 open
RCSN2 = 82k
DCR
C
ESR
V
V
CSP
CSN
R
+
-
0
5
10
15
20
25
CSN1
GMx
Ix
IOUT (A)
Figure 14
R
CSN2
VID on the Fly
Figure13. Application circuit of GM
With external pull up resistors tied to VID pins, RT9245
converters different VID codes from CPU into output
voltage. Figure 12 and Figure 13 show the waveforms of
VID on the fly function.
For load line design, with application circuit in Figure 13,
it can eliminate the dead zone of load line at light loads.
VCSP = VOUT +IL x DCR
if GM holds input voltages equal, then
VCSP = VCSN
VID on the Fly (Falling)
VCSN
IL × DCR
IX
=
+
PWM
VCORE
RCSN2
RCSN1
VOUT + IL × DCR IL × DCR
VFB
=
+
RCSN2
RCSN1
CH3:(500mV/Div)
CH4:(1V/Div)
CH1:(5V/Div)
CH2:(500mV/Div)
VOUT
IL × DCR IL × DCR
=
+
+
RCSN2
RCSN2
RCSN1
For the lack of sinking capability of GM, RCSN2 should be
small enough to compensate the negative inductor valley
current especially at light loads.
VID125
VDAC = 1.500, IOUT = 5A
Time (25μs/Div)
VCSN
IL ×DCR
RCSN1
≥
RCSN2
Figure 15
www.richtek.com
14
DS9245-06 March 2007
RT9245
Voltage Offset Function
VID on the Fly (Rising)
1.284
1.282
1.28
PWM
VCORE
1.278
1.276
1.274
1.272
1.27
VFB
CH1:(5V/Div)
CH2:(500mV/Div)
CH3:(500mV/Div)
CH4:(1V/Div)
VID125
VDAC = 1.500, IOUT = 5A
1.268
50
60
70
80
90
100
110
Time (25μs/Div)
ROSS (kΩ)
Figure 16
Figure 18
PGOOD Waveform
1/4 I
VOSS
CH1:(500mV/Div)
CH2:(5V/Div)
CH3:(5V/Div)
RB1
-
EA
+
V
-V
DAC ADJ
VCORE
Figure 17
PGOOD
Output Voltage Offset Function
To meet Intel's requirement of initial offset of load line,
RT9245 provides programmable initial offset function. With
an external resistor RVOSS and voltage source at VOSS pin
to set offset current IVOSS. One quart of IVOSS flows through
RB1. Error amplifier would hold the inverting pin equal to
VDAC-VADJ. Thus output voltage is subtracted from
VDAL − VADJ for a constant offset voltage.
VSS
Time (10ms/Div)
Figure 19
VDD
PGOOD Function
R
PGOOD
To indicate the condition of multiphase converter, RT9245
provides PGOODsignal through an open drain connection.
The waveforms of PGOOD function are shown in Figure
15.
V
PGOOD
Figure 20. PGOOD Test Circuit
DS9245-06 March 2007
www.richtek.com
15
RT9245
ErrorAmplifier Characteristic
EA Rising Slew Rate
For fast response of converter to meet stringent output
current transient response, RT9245 provides large slew
rate capability and high gain-bandwidth performance.
VFB
EA Falling Slew Rate
CH1:(500mV/Div)
CH2:(2V/Div)
VFB
VCOMP
Time (250ns/Div)
Figure 22. EA Falling Transient with 10pF Loading;
Slew Rate=8V/us
CH1:(500mV/Div)
VCOMP
CH2:(2V/Div)
4.7k
Time (250ns/Div)
4.7k
B
-
A
EA
Figure 21. EA Rising Transient with 10pF Loading; Slew
Rate=10V/us
+
V
REF
Figure 23. Gain-Bandwidth Measurement by signalA
divided by signal B
0dB
180°
Figure 24. EA Frequency Response with closed loop gain set at 0db to observe gain-bandwidth product; -3dB at
10.86MHz
www.richtek.com
16
DS9245-06 March 2007
RT9245
Design Procedure Suggestion
1. Compensation Setting
a.Output filter pole and zero (Inductor, output capacitor
value & ESR).
a. ModulatorGain, Pole and Zero:
From the following formula:
b.Error amplifier compensation & sawtooth wave amp-
litude (compensation network).
Modulator Gain =VIN/VRAMP =12/2.4=5 (i.e 14dB)
where VRAMP : ramp amplitude of saw-tooth wave
LC Filter Pole = = 1.45kHz and
c.Kelvin sense for VCORE.
Current Loop Setting
ESR Zero =3.98kHz
a.GM amplifier S/H current (current sense component
DCR, CSN pin external resistor value).
b. EA Compensation Network:
Select R1 = 4.7k, R2 = 15k, C1 = 12nF, C2 = 68pF and
use the Type 2 compensation scheme shown in Figure
25. By calculation, the FZ = 0.88kHz, FP = 322kHz and
Middle Band Gain is 3.19 (i.e 10.07dB).
b.Over-current protection trip point (RIMAX resistor).
VRM Load Line Setting
a.Droop amplitude (ADJ pin resistor).
b.No load offset (RCSN2
)
C2 68pF
c.DAC offset voltage setting (VOSS pin & compen- sation
network resistor RB1).
C1
RB2
15k
12nF
RB1
4.7k
-
Power Sequence & SS
EA
+
DVD pin external resistor and SS pin capacitor.
Figure 25. Type 2 compensation network of EA
PCB Layout
a.Kelvin sense for current sense GM amplifier input.
The bode plot of EA compensation is shown as Figure 26.
b.Refer to layout guide for other items.
The bode plot of power stage is shown as Figure 27. The
total loop gain is in Figure 28.
Voltage Loop Setting
Design Example
3. Over-Current Protection Setting
Consider the temperature coefficient of copper
Given:
3900ppm/°C,
Apply for four phase converter
1
V
1
IL ×DCR
IMAX
VIN = 12V
×
⇔
×
2 RIMAX
3 RCOMMON
VCORE = 1.5V
1 1.690V
1 40A×1.39mΩ
3
×
⇔
×
ILOAD (MAX) = 100A
2
RIMAX
330Ω
VDROOP = 100mV at full load (1mΩ Load Line)
OCP trip point set at 40A for each channel (S/H)
DCR = 1mΩ of inductor at 25°C
L = 1.5μH
Let RIMAX = 14kΩ
4. Soft-Start Capacitor Selection
For most application cases, 0.1μF is a good engineering
value.
COUT = 8000μF with 5mΩ equivalent ESR.
DS9245-06 March 2007
www.richtek.com
17
RT9245
0dB
-180°
Figure 26. The Frequency Response of the CompensatorNetwork
0dB
-180°
Figure 27. The Frequency Response of Power Stage
www.richtek.com
18
DS9245-06 March 2007
RT9245
0dB
-180°
Figure 28. The LoopGain of Converter
Layout Guide
Place the high-power switching components first, and separate them from sensitive nodes.
1. Most critical path: the current sense circuit is the most sensitive part of the converter. The current sense
resistors tied to CSP1,2,3,4 and CSN should be located not more than 0.5 inch from the IC and away from
the noise switching nodes. The PCB trace of sense nodes should be parallel and as short as possible.
Kelvin connection of the sense component (additional sense resistor or Inductor DCR) ensures the accurate
stable current sensing.
Keep well Kelvin sense to ensure the stable operation!
2. Switching ripple current path:
a. Input capacitor to high side MOSFET.
b. Low side MOSFET to output capacitor.
c. The return path of input and output capacitor.
d. Separate the power and signalGND.
e. The switching nodes (the connection node of high/low side MOSFET and inductor) is the most noisy points.
Keep them away from sensitive small-signal node.
f. Reduce parasitic R, L by minimum length, enough copper thickness and avoiding of via.
3. MOSFET driver should be closed to MOSFET.
4. The compensation, bypass and other function setting components should be near the IC and away from the noisy
power path.
DS9245-06 March 2007
www.richtek.com
19
RT9245
L1
SW1
VOUT
VIN
RIN
COUT
RL
CIN
V
L2
SW2
Figure 29. Power Stage Ripple Current Path
Next to IC
C
+12V or +5V
PWM
+12V
+5V
VCC
IN
0.1uF
C
BP
RT
BOOT
VCC
BST
DRVH
SW
VOSS
SGND
Next to IC
PVCC
COMP
L
O1
VCORE
C
C
IN
C
OUT
R
CSN
RT9245
CSN
C
RT9603
DRVL
IN
R
C
Kelvin
Sense
Locate next
to FB Pin
FB
GND
R
FB
CSPx
ADJ
Locate near MOSFETs
GND
For Thermal Couple
Figure 30. Layout Consideration
www.richtek.com
20
DS9245-06 March 2007
RT9245
Figure 31. Layout of power stage
Test Conditions :
VIN : 12V
VOUT : 1.300V
FSW : 200kHz
IOUT : 80A
Phase Number : 4 Phases
U-MOSFET : IR3707 x 1 (9.5mΩ x 9.6nC)
L-MOSFET : IR8113 x 2 (6.0mΩ x 22nC)
L : 1.5uH
DCR : 1m
CIN : 1000uF x 8
COUT : 1000uF x 8
Snubber : 2R2+3.3nF
Air Speed : Using MAGIC MGA8012HS FAN with 5VDC drive.
P1
P1
M1
P1
M2
P1
M3
P2
P2
M4
P2
M5
P2
M6
Driver
55°C
Driver
56°C
58°C
58°C
56°C
60°C
60°C
60°C
P3
P3
M7
P3
M8
P3
M9
P4
P4
P4
P4
Driver
55°C
Driver
59°C
M10
69°C
M11
66°C
M12
61°C
64°C
64°C
65°C
η
Note: VIN= 10.835V; IIN = 10.6A; VOUT = 1.2127V; IOUT = 80A; =84.47%
DS9245-06 March 2007
www.richtek.com
21
RT9245
Outline Dimension
D
L
E
E1
e
A2
A
A1
b
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
A1
A2
b
0.850
0.050
0.800
0.178
9.601
1.200
0.152
1.050
0.305
9.804
0.033
0.002
0.031
0.007
0.378
0.047
0.006
0.041
0.012
0.386
D
e
0.650
0.026
E
6.300
4.293
0.450
6.500
4.496
0.762
0.248
0.169
0.018
0.256
0.177
0.030
E1
L
28-Lead TSSOP Plastic Package
Richtek Technology Corporation
Headquarter
Richtek Technology Corporation
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
8F, No. 137, Lane 235, Paochiao Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)89191466 Fax: (8862)89191465
Email: marketing@richtek.com
www.richtek.com
22
DS9245-06 March 2007
相关型号：
©2020 ICPDF网 联系我们和版权申明