RTQ2521A_技术文档

®

RTQ2521A

1.5A, 6.5V, Ultra Low Noise, Ultra Low Dropout Linear Regulator

General Description

Features

^Input Voltage Range : 1.1V to 6.5V

^Output Voltage Range : 0.5V to 5.5V

^Accurate Output Voltage Accuracy (1%) Over Line,

Load and Temperature

The RTQ2521A is a high-current (1.5A), low-noise

(7μV_RMS), high accuracy (1% over line, load, and

temperature), low-dropout linear regulator (LDO) capable

of sourcing 1.5Awith extremely low dropout (max. 110mV).

The device supports single input supply voltage as low to

1.1V that makes it easy to use.

^Ultra High PSRR : 38dB at 500kHz

^Excellent Noise Immunity

^^7μV_RMSat 0.5V Output

^^10μV_RMSat 3.3V Output

^Ultra Low Dropout Voltage : 110mV at 1.5A

^Enable Control

The low noise, high PSRR and high output current capability

makes the RTQ2521A ideal to power noise-sensitive

devices such as analog-to-digital converters (ADCs),

digital-to-analog converters (DACs), and RF components.

With very high accuracy, remote sensing, and soft-start

capabilities to reduce inrush current, the RTQ2521A is

ideal for powering digital loads such as FPGAs, DSPs,

andASICs.

^Programmable Soft-Start Output

^Stable with a 10μF or Larger Ceramic Output

Capacitor

 Support Power-Good Indicator Function

 RoHS Compliant and Halogen Free

The external enable control and power good indicator

function makes the sequence control easier. The output

noise immunity is enhanced by adding external bypass

capacitor onNR/SS pin. The device is fully specified over

the temperature range of T_J= −40°C to 125°C and is offered

in the WDFN-8EL 3x3 package.

Applications

 Portable ElectronicDevice

 Wireless Infrastructure : SerDes, FPGA, DSP

 RF, IF Components : VCO, ADC, DAC, LVDS

Simplified Application Circuit

RTQ2521A

V

VIN

IN

VOUT

V

OUT

C

IN

R1

R2

C

OUT

FF

Power Good

FB

R3

V

OUT

PGOOD

Enable

EN

NR/SS

C

NR/SS

GND

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RTQ2521A

Ordering Information

RTQ2521A

Pin Configuration

(TOP VIEW)

Package Type

QW : WDFN-8EL 3x3 (W-type)

1

2

3

4

8

7

6

5

VOUT

FB

GND

VIN

EN

NR/SS

NC

Lead Plating System

G : Green (Halogen Free and Pb Free)

9

PGOOD

WDFN-8EL 3x3

Note :

Richtek products are :

 RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

Marking Information

QY= : Product Code

 Suitable for use in SnPb or Pb-free soldering processes.

YMDNN : Date Code

QY=YM

DNN

Functional Pin Description

Pin No.

Pin Name

Pin Function

LDO output pins. A 10F or larger ceramic capacitor (4.7F or greater of

effective capacitance) is required for stability. Place the output capacitor as

close to the device as possible and minimize the impedance between VOUT

pin to load.

1

VOUT

Feedback voltage input. This pin is used to set the desired output voltage via

an external resistive divider. The feedback reference voltage is 0.5V typically.

2

FB

3,

Ground. The exposed pad must be soldered to a large PCB and connected

to GND for maximum the power dissipation.

GND

9 (Exposed Pad)

Power good indicator output. An open-drain output and active high when the

output voltage reaches 88% of the target. The pin is pulled to ground when

the output voltage is lower than its specified threshold, EN shutdown, OCP

and OTP.

4

5

6

PGOOD

NC

No internal connection. Leave these pins floating doesn’t affect the chip

functionality. By connecting these pins to GND, design engineers could

extend the GND copper coverage on the PCB top layer to enhance the

thermal convection.

Noise-reduction and soft-start pin. Decouple this pin to GND with an external

capacitor C_NR/SScan not only reduce output noise to very low levels but also

slow down the VOUT rise like a soft-start behavior. For low noise applications,

a 10nF to 1F C_NR/SSis suggested.

NR/SS

Enable control input. Connecting this pin to logic high enables the regulator

or driving this pin low puts it into shutdown mode.

7

8

EN

The device can operate with V_INand V_ENsequenced in any order. Mostly,

enabling the device after V_INis present can achieve precise timing control.

Supply input. A minimum of 10F ceramic capacitor or greater of capacitance

is required and should be placed as close as possible to this pin for better

noise rejection.

VIN

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RTQ2521A

Functional Block Diagram

VOUT

VIN

Charge

Pump

Active

Discharge

Current

Limit

Gate

Driver

Thermal

Protection

PGOOD

0.45V

UVLO

+

-

Enable

Control

Logic

UVLO

-

EN

FB

Bandgap

Reference

INR/SS

NR/SS GND

Operation

The RTQ2521Aoperates with single supply input ranging

from 1.1V to 6.5V and capable to deliver 1.5A current to

the output. The device features high PSRR and low noise

provides a clean supply to the application.

input as close as possible to prevent voltage droops on

the VIN line from triggering the enable circuit.

Programmable Soft-Start

The noise-reduction capacitor (C_NR/SS) accomplishes dual

purpose of both noise-reduction and programming the soft-

start ramp time during turn-on. When ENand UVLO exceeds

the respective threshold voltage, the RTQ2521A active a

quick-start circuit to charge the noise reduction capacitor

(C_NR/SS) and then the output voltage ramps up.

A low-noise reference and error amplifier are included to

reduce device noise. TheNR/SS capacitor filters the noise

from the reference and feed-forward capacitor filters the

noise from the error amplifier. The high power-supply

rejection ratio (PSRR) of the RTQ2521A minimize the

coupling of input supply noise to the output.

Power Good

Enable and Shutdown

The power-good circuit monitors the feedback pin voltage

to indicate the status of the output voltage. The open-

drain PGOOD pin requires an external pull-up resistor to

an external supply, any downstream device can receive

power-good as a logic signal that can be used for

sequencing. Pull-up resistor from 10kΩ to 100kΩ is

recommended. Make sure that the external pull-up supply

voltage results in a valid logic signal for the receiving device

or devices.

The RTQ2521A provides an EN pin, as an external chip

enable control, to enable or disable the device. V_ENbelow

0.5 V turns the regulator off and enters the shutdown mode,

while V_ENabove 1.1V turns the regulator on. When the

regulator is shutdown, the ground current is reduced to a

maximum of 25μA. The enable circuitry has hysteresis

(typically 50mV) for use with relatively slowly ramping

analog signals.

If not used, connect EN to the largest capacitance on the

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RTQ2521A

After start-up, the PGOODpin becomes high impedance

when the feedback voltage exceeds V_{PGOOD_HYS}(Typically

90% of 0.5V reference voltage level). The PGOOD is pulled

to GND when the feedback pin voltage falls below the

V_{IT_PGOOD}, EN low, current limit, and OTP.

Output Active Discharge

When the device is disabled, the RTQ2521A discharges

the LDO output (via VOUT pins) through an internal several

hundred ohms to ground. Do not rely on the active

discharge circuit for discharging a large amount of output

capacitance after the input supply has collapsed because

reverse current can possibly flow from the output to the

input. External current protection should be added if the

device may work at reverse voltage state.

Under-Voltage Lockout (UVLO)

The UVLO circuit monitors the input voltage to prevent

the device from turning on before VIN rises above the V_UVLO

threshold. The UVLO circuit also disables the output of

the device when VIN fall below the lockout voltage

(V_UVLO− ΔV_UVLO). The UVLO circuit responds quickly to

glitches on VIN and attempts to disable the output of the

device if VINcollapse.

Internal Current Limit (I_LIM

)

The RTQ2521A continuously monitors the output current

to protect the pass transistor against abnormal operations.

When an overload or short circuit is encountered, the

current limit circuitry controls the pass transistor's gate

voltage to limit the output within the predefined range.

Thermal shutdown can activate during a current limit event

because of the high power dissipation typically found in

these conditions. To ensure proper operation of the current

limit, minimize the inductances to the input and load.

Continuous operation in current limit is not recommended.

By reason of the build-in body diode, the pass transistor

conducts current when the output voltage exceeds input

voltage. Since the current is not limited, external current

protection should be added if the device may work at

reverse voltage state.

Over-Temperature Protection (OTP)

The RTQ2521A implements thermal shutdown protection.

The device is disable when the junction temperature (T_J)

exceeds 160°C (typical). The LDO automatically turn-on

again when the temperature falls to 140°C (typical).

For reliable operation, limit the junction temperature to a

maximum of 125°C. Continuously running the RTQ2521A

into thermal shutdown or above a junction temperature of

125°C reduces long-term reliability.

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RTQ2521A

Absolute Maximum Ratings (Note 1)

 VIN, PGOOD, EN -------------------------------------------------------------------------------------------------- −0.3V to 7V

 VOUT ------------------------------------------------------------------------------------------------------------------ −0.3V to (V_IN+ 0.3V)

 NR/SS, FB ----------------------------------------------------------------------------------------------------------- −0.3V to 3.6V

 Power Dissipation, P_D@ T_A= 25°C

WDFN-8EL 3x3 ----------------------------------------------------------------------------------------------------- 3.27W

 Package Thermal Resistance (Note 2)

WDFN-8EL 3x3, θ_JA------------------------------------------------------------------------------------------------ 30.5°C/W

WDFN-8EL 3x3, θ_JC----------------------------------------------------------------------------------------------- 7.5°C/W

 Lead Temperature (Soldering, 10 sec.)------------------------------------------------------------------------ 260°C

 Junction Temperature ---------------------------------------------------------------------------------------------- 150°C

 Storage Temperature Range ------------------------------------------------------------------------------------- −65°C to 150°C

 ESD Susceptibility (Note 3)

HBM (Human Body Model)--------------------------------------------------------------------------------------- 2kV

Recommended Operating Conditions (Note 4)

 Supply Input Voltage, VIN ---------------------------------------------------------------------------------------- 1.1V to 6.5V

 Junction Temperature Range------------------------------------------------------------------------------------- −40°C to 125°C

Electrical Characteristics

Over operating temperature range (T_J= −40°C to 125°C), (1.1V ≤ V_IN< 6.5V and V_IN≥ V_OUT(TARGET)+ 0.3 V, V_OUT(TARGET)= 0.5V,

VOUT connected to 50Ω to GND, V_EN= 1.1 V, C_IN= 10μF, C_OUT= 10μF, C_NR/SS= 0nF, C_FF= 0nF, and PGOOD pin pulled up to

V_INwith 100 kΩ, unless otherwise noted. (Note 5)

Parameter

Symbol

Test Conditions

Min

Typ

Max Unit

Operating Input

Voltage Range

V_IN

1.1

--

6.5

V

Feedback Reference

Voltage

V_REF

--

0.5

--

NR/SS Pin Voltage

V_NR/SS

V_UVLO

--

---

V

V_INincreasing

Hysteresis

1.02 1.085

Under-Voltage

Lock-Out

V_UVLO

150

--

mV

0.5V

1.5%

5.5V

+1%

Output Voltage Range

--

V

_IN= V_OUT+ 0.3V, 0.5V  V_OUT 0.8V

1.5

1

--

+1.5

+1

5mA  I_OUT 1.5A

Output Voltage

V_OUT

%

Accuracy

(Note 6)

V_IN= V_OUT+ 0.3V, 0.8V  V_OUT 5.5V

5mA  I_OUT 1.5A

Line Regulation

Load Regulation

Dropout Voltage

V_OUT/V_INI_OUT= 5mA, 1.4V  V_IN 6.5 V

V_OUT/I_OUT5mA  I_OUT 1.5A

--

0.05

0.08

--

%/V

%/A

mV

V_DROP

I_OUT= 1.5A, V_FB= 0.5V  3%

_OUT= 90% V_OUT(TARGET),

V_IN= V_OUT(TARGET)+ 400mV

110

V

Output Current Limit

I_LIM

1.8

2.3

2.8

A

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RTQ2521A

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Minimum load, V_IN= 6.5V,

--

2.8

4

I

_OUT= 5mA

Maximum load, V_IN= 1.4V,

_OUT= 1.5A

Shutdown, PGOOD = Open,

_IN= 6.5V, V_EN= 0.5V

mA

Ground Pin Current

EN Pin Current

I_GND

--

3.7

--

5.5

25

I

A

V

--

I_EN

V_IN= 6.5V, V_EN= 0V and 6.5V

EN Input Voltage “H”

0.1

1.1

0

0.1

6.5

0.5

V_{EN_H}

V_{EN_L}

EN Pin Threshold

Voltage

V

EN Input Voltage “L”

PGOOD Pin

Threshold

For the direction PGOOD signal

falling with decreasing V_OUT

0.82 x 0.883 x 0.93 x

V_{IT_PGOOD}

V

V_OUT

PGOOD Pin

Hysteresis

0.025 x

V_OUT

V_{PGOOD_HYS}For PGOOD signal rising

--

PGOOD Pin Low-

Level Output Voltage

V_OUT< V_{IT_PGOOD}

I_PGOOD= 1mA (current into device)

,

V_{PGOOD_L}

--

0.4

V

PGOOD Pin Leakage

Current

V_OUT> V_{IT_PGOOD}

_PGOOD= 6.5V

,

I_{PGOOD_LK}

I_NR/SS

I_FB

--

4

--

6.2

--

1

9

A

nA

V

NR/SS Pin Charging

Current

V_NR/SS= GND, V_IN= 6.5V

V_IN= 6.5V

FB Pin Leakage

Current

100

100

V

_IN= 4.3V,

f = 10kHz

--

60

38

7

--

V_OUT= 3.3V,

Power Supply

Rejection Ratio

PSRR

I

_OUT= 750mA,

dB

C

_NR/SS= C_FF= 10nF,

_OUT= 22F

f = 500kHz

V_IN= 1.1V,

BW = 10Hz to 100kHz

_OUT= 1.5A

V_OUT= 0.5V

I

Output Noise Voltage e_NO

C

_NR/SS= 100nF

_FF= 10nF

_OUT= 10F

V_RMS

V_OUT= 3.3V

10

--

Temperature increasing

Temperature decreasing

--

160

140

--

Thermal Shutdown

T_SD

°C

Threshold

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RTQ2521A

Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.

These are stress ratings only, and functional operation of the device at these or any other conditions beyond those

indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating

conditions may affect device reliability.

Note 2. θ_JAis measured under natural convection (still air) at T_A= 25°C with the component mounted on a high effective-

thermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard. θ_JCis measured at the

exposed pad of the package.

Note 3. Devices are ESD sensitive. Handling precaution is recommended.

Note 4. The device is not guaranteed to function outside its operating conditions.

Note 5. V_OUT(TARGET)is the expected V_OUTvalue set by the external feedback resistors. The 50Ω load is disconnected when the

test conditions specify an I_OUTvalue.

Note 6. External resistor tolerance is not taken into account.

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RTQ2521A

Typical Application Circuit

RTQ2521A

8

4

1

2

V

OUT

V

VIN

IN

VOUT

C

10µF

1V/1.5A

IN

C

10µF

C

10nF

OUT

FF

R1

12.4k

Power Good

FB

R3 100k

V

R2

OUT

PGOOD

12.4k

7

6

Enable

EN

NR/SS

C

10nF

NR/SS

GND

3, 9 (Exposed Pad)

R1

R2

12.4k



















V_OUT= V_REF 1 +

= 0.5V 1 +

= 1V





Figure 1. Configuration Circuit for V_OUTAdjusted by a ResistiveDivider

Table 1. Recommended Feedback-Resistor Values

External Restive Divider Combinations

Output Voltage (V)

R1 (k)

12.4

R2 (k)

31

0.7

1

12.4

8.86

6.2

1.2

1.5

1.8

2.5

3.3

4.5

5

4.77

3.1

2.21

1.55

1.38

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RTQ2521A

Typical Operating Characteristics

Power On from EN

Power Off from EN

V_IN= 4.3V, V_OUT= 3.3V, I_OUT= 1.5A,

V_EN

(2V/Div)

C_OUT= 10μF, C_NR/SS= C_FF=10nF

V_EN

(2V/Div)

V_OUT

(1V/Div)

V_OUT

(1V/Div)

V_PGOOD

(4V/Div)

V_PGOOD

(4V/Div)

I_OUT

(1A/Div)

I_OUT

(1A/Div)

V_IN= 4.3V, V_OUT= 3.3V, I_OUT= 1.5A,

C_OUT= 10μF, C_NR/SS= C_FF=10nF

Time (1ms/Div)

Time (50μs/Div)

Load Transient Response

PSRR vs. Frequency and I_OUT

100

80

60

40

20

0

V_OUT

(50mV/Div)

V_IN= 4.3V, V_OUT= 3.3V,

I_OUT= 0.5A to 1.5A,

C_OUT= 10μF,

I_OUT= 100mA

I_OUT= 500mA

C_NR/SS= C_FF=10nF

I

_OUT= 750mA

_OUT= 1.2A

I_OUT

(0.5A/Div)

V_IN= 3.8V, V_OUT= 3.3V,

C_OUT= 22μF,

C_NR/SS= C_FF=10nF

10

100

1K

10K

100K

1M

Time (20μs/Div)

Frequency (Hz)

PSRR vs. Frequency and V_IN

PSRR vs. Frequency and V_OUT

100

80

60

40

20

0

100

V_IN= 4.8V

V_IN= 4.3V

V_IN= 3.8V

V_IN= 3.7V

V_IN= 3.6V

80

60

V_OUT= 3.3V

V_OUT= 1.8V

V_OUT= 1.2V

V_OUT= 2.5V

V_OUT= 0.8V

40

20

V_OUT= 3.3V, C_OUT= 22μF,

I_OUT= 750mA

C_NR/SS= C_FF=10nF

V_IN= V_OUT+ 0.3V,

C_OUT= 22μF, I_OUT= 1.2A

C_NR/SS= C_FF=10nF

0

10

100

1K

10K

100K

1M

10

100

1K

10K

100K

1M

Frequency (Hz)

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RTQ2521A

Output Noise vs. Frequency and V_OUT

PSRR vs. Frequency and C_OUT

1000

100

80

60

40

20

0

V_IN= 5.3V, V_OUT= 5V

V_IN= 3.6V, V_OUT= 3.3V

V_IN= 2.1V, V_OUT= 1.8V

V_IN= 1.2V, V_OUT= 0.5V

10

C_OUT= 22μF

_OUT= 10μF

C_OUT= 47μF

C

1

0.1

0.01

0.001

0.0001

V_IN= 4.3V, V_OUT= 3.3V,

I_OUT= 750mA

C_NR/SS= C_FF=10nF

C_OUT= 10μF, I_OUT= 1.5A,

C_FF= 10nF, C_NR/SS= 100nF

10

100

1K

10K

100K

1M

10

100

1K

10K

100K

1M

Frequency (Hz)

Enable Voltage vs. Temperature

Input UVLO vs. Temperature

1.50

1.25

1.00

0.75

0.50

0.25

0.00

1.2

1.0

0.8

0.6

0.4

0.2

0.0

Logic-High

Logic-Low

Logic-High

Logic-Low

V_IN= 1.2V, V_OUT= 0.5V, I_OUT= 10mA

25 50 75 100 125

V_OUT= 0.5V, I_OUT= 10mA

50 75 100 125

-50

-25

0

-50

-25

0

25

Temperature (°C)

Dropout Voltage vs. Output Current

100

90

80

70

60

50

40

30

20

10

0

125°C

85°C

25°C

−40°C

V_IN= 1.1V

1250 1500

0

250

500

750

1000

Output Current (mA)

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RTQ2521A

Application Information

The RTQ2521Ais a high current, low-noise, high accuracy,

low-dropout linear regulator which capable of sourcing 1.5A

with only maximum 110mV dropout. The input voltage

operating range from 1.1V to 6.5V and adjustable output

voltage from 0.5V to (V_IN− V_DROP) via external resistor

setting and get required output target.

recommended due to its good capacitive stability across

temperature, whereas the use of Y5V-rated capacitors is

discouraged because of large variations in capacitance.

However, ceramic capacitance varies with operating voltage

and temperature and the design engineer must be aware

of these characteristics. It is recommended to use

capacitors of 10μF or greator (4.7μF or greater of effective

capacitance ) to ensure stability. Input capacitance is

selected to minimize transient input droop during load

current steps. For general applications, an input capacitor

of at least 10μF is highly recommended for minimal input

impedance. If the trace inductance between the RTQ2521A

input supply is high, a fast load transient any cause VIN

voltage level ringing and above the absolute maximum

voltage rating that also damage the device. Adding more

input capacitors is available to restrict the ringing and to

keep it not above the device absolute maximum ratings.

Output Voltage Setting

The output voltage of the RTQ2521Acan be set by external

resistors to achieve different output target.

Using external resistors, the output voltage is determined

by the values of R1 and R2 as Figure 2. The values of R1

and R2 can be calculated with any voltage value via use

the formula given in Equation :

R1 + R2

V_OUT= 0.5V

R2

RTQ2521

V

OUT

V

VIN

EN

VOUT

SNS

IN

C

OUT

C

IN

R1

R2

Feed-Forward Capacitor (C_FF)

C

FF

The RTQ2521A is designed to be stable without the

external feed-forward capacitor (C_FF). However, a 10nF

external feed-forward capacitor optimizes the transient,

noise, and PSRR performance. Ahigher capacitance C_FF

can be also used, but the start-up time is longer and the

power-good signal can incorrectly indicate that the output

voltage is settled.

FB

GND

Figure 2. Output Voltage Set by External Resistors

Dropout Voltage

The dropout voltage refers to the voltage difference between

the VINand VOUT pins while operating at specific output

current. The dropout voltage V_DROPalso can be expressed

as the voltage drop on the pass-FET at specific output

current (I_RATED) while the pass-FET is fully operating at

ohmic region and the pass-FET can be characterized as

an resistance R_DS(ON). Thus the dropout voltage can be

defined as (V_DROP= V_IN− V_OUT= R_DS(ON)x I_RATED). For

normal operation, the suggested LDO operating range is

(V_IN> V_OUT+ V_DROP) for good transient response and

PSRR ability. Vice versa, while operating at the ohmic

region will degrade the performance severely.

Soft-Start and Noise Reduction (C_NR/SS

)

The RTQ2521Ais designed for a programmable, monotonic

soft-start time of output rising, it can be achieved via an

external capacitor (C_NR/SS) onNR/SS pin. Using an external

C_NR/SSis recommended for general application, not only

for the in-rush current minimization but also helps reduce

the noise component from internal reference.

During the monotonic start-up procedure, the error amplifier

of the RTQ2521A tracks the voltage ramp of the external

soft-start capacitor(C_NR/SS) until the voltage approaches

the internal reference 0.5V. The soft-start ramp time can

be calculated with Equation a1 and which is depends on

the soft-start charging current (I_NR/SS), the soft-start

capacitance (C_NR/SS), and the internal reference 0.5V

(V_REF).

C_INand C_OUTSelection

The RTQ2521A is designed to support the low equivalent

series resistance (ESR) ceramic capacitors for application.

The X7R, X5R, and COG-rated ceramic capacitors is

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11

RTQ2521A

more input capacitance or improving input trace layout on

PCB are effectively to make sure input power stabilization.

V

C





REF

NR/SS

t

=

a1





SS

I

NR/SS

For noise-reduction consideration, the C_NR/SSalso

conjunction with an internal noise-reduction resistor that

forms a low-pass filter (LPF) and filters out the noise from

the internal bandgap reference before it being gained up

via the error amplifier, thus reducing the total device noise

floor.

Power-Good (PGOOD) Function

The Power-Good function is monitors the voltage level at

the feedback pin to indicate the output voltage status is

works normal or not, this function enables others devices

receive the RTQ2521A's Power-Good signal as a logic

signal that can be used for the sequence design of the

system application. The PGOOD pin is an open-drain

structure and an external pull-up resistor connecting to

an external supply is necessary. The pulled-up resistor

value between 10kΩ to 100kΩ is recommended for proper

operation. The lower limit of 10kΩ results from the

maximum pulled-down strength of the power-good

transistor, and the upper limit of 100kΩ results from the

maximum leakage current at the power-good node.

Input Inrush Current

During start-up process, the input Inrush current into VIN

pin is consists of the sum of load current and the charging

current of the output capacitor. The inrush current is difficult

to measure that the input capacitor must be removed and

which is not recommended.Generally, the soft-start inrush

current can be estimated by Equation b1, which V_OUT(t)

is the instantaneous output voltage of the power-up ramp,

dV_OUT(t) / dt is the slope of the V_OUTramp and R_LOADis

the resistive load impedance.

Figure 4 demonstrates some PGOOD scenarios versus

the VIN, ENand protection status. Duration “a” is present

the device is under the operation while V_ENis higher than

V_{EN_H}threshold, the output voltage V_OUTstart rising(the

C_OUTdV_OUT

t

 





V_OUT

t





+

 

I_OUTt =

 

b1









dt

R_LOAD





rising time has related with soft-start capacitor C_NR/SS)

,

Under-Voltage Lockout (UVLO)

after V_OUTover PGOOD hysteresis threshold, the reflected

feedback voltage V_FBexceeds V_{PGOOD_HYS}threshold, the

PGOOD pin is high impedance. The duration “b”

indicates some unpredictable operation happens (ex: OTP,

OCP or output voltage droop severely caused by very fast

load variation). Where the V_FBlower than V_{IT_PGOOD}

threshold and the V_PGOODis pulled toGNDfor the indication

that output voltage status is not ready. While duration

“c” is assume V_OUThave small droop that not lower than

PGOOD falling threshold, the PGOOD pin remain high

impedance. After V_ENgoes logic low level, V_PGOODpulled

to GND as duration “d” presented.

The under-voltage lockout (UVLO) threshold is the

minimum input operational voltage range that ensure the

device stays disabled. Figure 3 explain the UVLO circuits

being triggered between three different input voltage

events(duration a, b and c), assuming V_EN≥ V_{EN_H}for all

time duration. For duration “a”, input power starts rising

and V_INover the UVLO rising threshold, the V_OUTstarts

power on then reached the target level and under regulated.

Duration “b” is assume V_INoccurs instant power line

unstable and have droop severely, the V_INdroop level not

lower than UVLO falling threshold, the device maintain

normal work status, V_OUTstill under regulated. The

duration “c” is happens V_INdroop level lower than UVLO

falling threshold, the control loop of device is disabled

and don't have the regulation ability either, the V_OUTdroop

in the mean time. For general application, instant power

line transient with long power trace between VINpin may

have V_INlevel unstable force the device trap into duration

c and makes output voltage collapse. In this case, adding

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RTQ2521A

c

a

b

UVLO Rising Threshold

UVLO Hystersis Falling

V

IN

V

OUT

Figure 3. Under-Voltage Lockout Trigging Conditions and Output Variation

V

EN

a

c

d

b

PGOOD Hysteresis Rising

PGOOD Falling Threshold

V

OUT

V

PGOOD

Figure 4. PGOODTrigger Scenario withDifferent Operating Status

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RTQ2521A

Reverse Current Protection

calculated using the following formula :

If the maximum V_OUTexceeds V_IN+ 0.3V, that may induce

reverse current from VOUT to VIN that flows through the

body diode of pass element instead of the normal

conducting channel. In this case, the pass element maybe

damaged. For example, the output is biased above input

supply voltage level or input supply has instant collapse

at light load operation that makes V_IN< V_OUT. As shown

in Figure 5, an external Schottky diode could be added to

prevent the pass element be damaged from the reverse

current.

P_D(MAX)= (T_J(MAX)− T_A) / θ_JA

where T_J(MAX)is the maximum junction temperature, T_Ais

the ambient temperature, and θ_JAis the junction-to-ambient

thermal resistance.

For continuous operation, the maximum operating junction

temperature indicated under Recommended Operating

Conditions is 125°C. The junction-to-ambient thermal

resistance, θ_JA, is highly package dependent. For a WDFN-

8EL 3x3 package, the thermal resistance, θ_JA, is 30.5°C/

W on a standard JEDEC 51-7 high effective-thermal-

conductivity four-layer test board. The maximum power

dissipation at T_A= 25°C can be calculated as below :

VIN

P_D(MAX)= (125°C − 25°C) / (30.5°C/W) = 3.27W for a

WDFN-8EL 3x3 package.

VOUT

C

OUT

C

IN

RTQ2521

The maximum power dissipation depends on the operating

ambient temperature for the fixed T_J(MAX)and the thermal

resistance, θ_JA. The derating curves in Figure 7 allows

the designer to see the effect of rising ambient temperature

on the maximum power dissipation.

GND

Figure 5. Application Circuit for Reverse Current

Protection

Thermal Considerations

V

OUT

Short to GND

Thermal protection limits power dissipation in the

RTQ2521A.When power dissipation on pass element

(P_DIS= (V_IN− V_OUT) x I_OUT) is too much that raise the

operation junction temperature exceeds 160°C, the OTP

circuit starts the thermal shutdown function and turns the

pass element off. The pass element turns on again after

the junction temperature cools down by 20°C. The

RTQ2521A output voltage will be closed to zero when output

short circuit occurs as shown in Figure 6. It can reduce

the chip temperature and provides maximum safety to

end users when output short circuit occurs.

V

OUT

I_LIM’

I

OUT

IC Temperature

Figure 6. Short-Circuit Protection when Output Short-

Circuit Occurs

The junction temperature should never exceed the

absolute maximum junction temperature T_J(MAX), listed

under Absolute Maximum Ratings, to avoid permanent

damage to the device. The maximum allowable power

dissipation depends on the thermal resistance of the IC

package, the PCB layout, the rate of surrounding airflow,

and the difference between the junction and ambient

temperatures. The maximum power dissipation can be

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DSQ2521A-00 October 2019

RTQ2521A

4.0

3.6

3.2

2.8

2.4

2.0

1.6

1.2

0.8

0.4

0.0

Four-Layer PCB

0

25

50

75

100

125

Ambient Temperature (°C)

Figure 7. Derating Curve of Maximum PowerDissipation

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RTQ2521A

Outline Dimension

D2

D

L

E

E2

SEE DETAIL A

1

e

b

2

1

2

1

A

A3

DETAILA

Pin #1 ID and Tie Bar Mark Options

A1

Note : The configuration of the Pin #1 identifier is optional,

but must be located within the zone indicated.

Dimensions In Millimeters

Dimensions In Inches

Symbol

Min

Max

Min

Max

A

A1

A3

b

0.700

0.000

0.175

0.180

2.950

2.200

2.950

1.450

0.800

0.050

0.250

0.300

3.050

2.700

3.050

1.750

0.028

0.000

0.007

0.116

0.087

0.116

0.057

0.031

0.002

0.010

0.012

0.120

0.106

0.120

0.069

D

D2

E

E2

e

0.500

0.020

L

0.350

0.450

0.014

0.018

W-Type 8EL DFN 3x3 Package (0.5mm Lead Pitch)

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DSQ2521A-00 October 2019

RTQ2521A

Footprint Information

Footprint Dimension (mm)

Sx

Number of

Package

Tolerance

M

P

A

B

C

D

Sy

V/W/U/XDFN3x3-8E

8

0.50 3.80 2.10 0.85 0.30 2.40 1.65 1.80

±0.05

Richtek Technology Corporation

14F, No. 8, Tai Yuen 1^stStreet, Chupei City

Hsinchu, Taiwan, R.O.C.

Tel: (8863)5526789

Richtek products are sold by description only. Customers should obtain the latest relevant information and data sheets before placing orders and should verify

that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek

product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use;

nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent

or patent rights of Richtek or its subsidiaries.

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17


型号：	RTQ2521A
厂家：	RICHTEK TECHNOLOGY CORPORATION
描述：	暂无描述
文件：	总17页 (文件大小：514K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

RTQ2521A [RICHTEK]

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