LC822973_技术文档

Ordering number : ENA2131

CMOS LSI

LC822973

TV Image Viewer LSI

Overview

This LSI is TV image viewer. A 16Mbit SDRAM is built-in as image frame buffers, on which an external CPU is

able to draw the images, then another part of this LSI displays the SDRAM images on TV in NTSC/PAL after video

data encoding. This LSI equips H/V scaling circuit to scale up QVGA size image to VGA to display on the TV screen,

for instance.

The main features of this LSI are specified as below.

Features

• NTSC/PAL video encoder is integrated.

Various format support

ITU-R601 (13.5MHz/NTSC&PAL) SQ (12.27MHz/NTSC, 14.75MHz/PAL)

NTSC-J, M/PAL-B, D, G, H, I/PAL-M, N

Various image adjustment

Y signal: brightness and contrast adjustment

C signal:U gain, V gain, HUE and Burst amplitude adjustment

Trap filter

Trap filters locate on the Y signal pass to reduce cross color interference. The trap strength is adjustable by

register setup.

Built-in color bar

This is for system test and level adjustment.

10 bit DAC with 75Ω driver

A high accuracy video DAC of 10bit is built-in. Its DAC output is able to be connected to TV input or any

image devices, thanks for its 75Ω driver built-in.

• It mounts 16Mbit SDRAM to store multiple VGA size images. Since it has the arbitration function built-in, the

access timing from CPU for drawing can be used without any care of real-time access condition for TV display.

VGA 30fps performance can be achieved with appropriate setting of system clock, the burst size of SDRAM,

scaling ratio etc.

Continued to the next page.

* I²C Bus is a trademark of Philips Corporation.

Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to

"standard application", intended for the use as general electronics equipment. The products mentioned herein

shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life,

aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system,

safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives

in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any

guarantee thereof. If you should intend to use our products for new introduction or other application different

from current conditions on the usage of automotive device, communication device, office equipment, industrial

equipment etc. , please consult with us about usage condition (temperature, operation time etc.) prior to the

intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely

responsible for the use.

Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate

the performance, characteristics, and functions of the described products in the independent state, and are not

guarantees of the performance, characteristics, and functions of the described products as mounted in the

customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent

device, the customer should always evaluate and test devices mounted in the customer

's products or

equipment.

Ver.1.07

O1012HKPC 20101028-S00001 No.A2131-1/27

LC822973

Continued from the previous page.

• The OSD function is installed. OSD images consist of binary pixel data to display over the original image. The

Alfa-blend display is also available.

• Scaling from ×1 up to ×4 in two independent directions, horizontally and vertically, is available.

256 step arbitrary enlargement is given by register settings. The image rotation is available when writing as well.

• The high-speed clock for SDRAM is generated internally by built-in PLL.

• CPU-IF with 8/9/16/18/24 bit width data transfer is available.

• Built-in VIDEO-IF supports receiving video rate image input with Hsync/Vsync/Dotclcok signals.

It accepts various digital image formats of 18bit-RGB666, 16bit-RGB565, 16bit-YUV422, 8bit-YUV422,

8bit-YUV422 (BT656) and so on. In addition, it accepts both interlace and non-interlace format.

• The Autoview function executes automatic writing/reading sequence. Once all the relevant commands are set, then

this function properly updates the image banks to write and to read. This bank arbitration avoids well the tearing

image (reading outruns writing).

• The FilckerFreeFilter effectively decreases the line flicker, a substantial phenomena of the interlace method.

• High performance C-signal band-limit filter is built-in. The thorny ‘dot crawl’ is thus decreased.

• CGMS-A/WSS data multiple functions are built-in.

• The I/O voltage of the CPU/Video interface is 1.6V-3.4V.

• Macrovision™ Encoding (Revision 7.1.L1 in NTSC and PAL standards for Composite video output applications)

are built-in. (LC822973-04VM-E only)*

* This device is Protected by U.S. patents 5, 583, 936; 6, 516, 132; 6, 836, 549; and 7, 050, 698; and other intellectual

property rights. The use of Macrovision's copy protection technology in the device must be authorized by

Macrovision and is intended for home and other limited pay-per-view uses only, unless otherwise authorized in

writing by Macrovision. Reverse engineering or disassembly is prohibited. This Device can only be sold or

distributed to Authorized Buyers.

DC characteristics/AC characteristics

Absolute Maximum Ratings at DV = 0V

SS

Ratings

-0.3 to 1.8

Parameter

Supply voltage

Symbol

Conditions

unit

V

DV 15 max

DD

DV IO max

DD

-0.3 to 3.96

V

Input voltage

V IO

I

-0.3 to 3.96 *1

V

Output voltage

V

IO

-0.3 to DV IO+0.3

DD

V

O

Operation surrounding

temperature

Topg

-30 to 85

°C

Storage temperature

Tstg

-55 to 125

Soldering

Hand

For 3 seconds

For 10 seconds

350

°C

temperature

soldering

Reflow

255

°C

In/Out current

I 15, I 15

20 *2

mA

I

O

I IO, I IO

I

O

*1 Input voltage of I/O basic cell in case of without P-ch protection diode.

*2 per 1 cell of I/O basic cell

Permissible Operation Range at Ta = -30 to 85°C, DV = 0V

SS

min

1.35

typ

max

1.65

Parameter

Supply voltage

Symbol

Conditions

unit

V

DV 15

1.5

3.0

1.8

3.0

1.5

DD

DV IO *3

DD

2.5

1.6

2.7

1.35

0

3.4

2.0

V

DV IO *4

DD

V

DV

3

3.4

V

DD

AV

3

3.4

V

DD

AV 15

DD

1.65

V

Input range

V

IO

DV IO

DD

V

IN

*3 at supply = 3.0V (Typical)

*4 at supply = 1.8V (Typical)

No.A2131-2/27

LC822973

I/O pin capacity at V 3 = DV IO = V 15 = V IO = DV = 0V, Ta = -30 to 85°C

DD

I

SS

Parameter

Input pin

Symbol

Conditions

min

typ

max

unit

pF

C

f = 1MHz

10

IN

Output pin

I/O pin

C

OUT

I/O

C

DC characteristics

I/O level / V = 0V, DV IO = 2.5 to 3.4V, Ta = -30 to 85°C

SS

DD

Applied

pin *5

Parameter

Symbol

IO

Conditions

min

typ

max

unit

Input level

H

L

V

CMOS

2.0

V

IH

(1) (2)

(3)

IO

0.3DV IO

DD

IL

H

L

CMOS schmit

V

IH

IO

0.3DV IO

DD

V

IL

Output level

H

L

IO

I

= -4mA

= 4mA

DV IO-0.4

DD

V

OH

OL

(2) (4)

(5)

IO

0.4

V

OL

H

L

V

IO

I

= 4mA

0.4

+10

V

OL

Input leak current

Output leak current

I

V = DV 3, DV

DD SS

(1) (2) (3)

(4) (5)

-10

μA

IL

I

High impedance

OZ

*5 The applied pins correspond to the following names.

I/O level / V = 0V, DV IO = 1.6 to 2.0V, Ta = -30 to 85°C

SS

DD

Applied

pin *6

Parameter

Symbol

IO

Conditions

min

typ

max

unit

Input level

H

L

V

CMOS

0.7DV IO

DD

V

IH

(1) (2)

(3)

IO

0.25DV IO

DD

IL

H

L

CMOS schmit

0.75DV IO

DD

V

IH

IO

0.2DV IO

DD

V

IL

Output level

H

L

IO

I

= -4mA

= 4mA

DV IO-0.4

DD

V

OH

OL

(2) (4)

(5)

IO

0.4

V

OL

H

L

V

IO

I

= 4mA

0.4

+10

V

OL

Input leak current

Output leak current

I

V = DV 3, DV

DD SS

(1) (2) (3)

(4) (5)

-10

μA

IL

OZ

I

High impedance

*6 The applied pins correspond to the following names.

(INPUT)

(1)

(2)

(3)

...

CKI, A0, CS, CONF3-CONF0, MODE2-MODE0

D15-D0, DB17, DB16

XRST, CS, RD, WR, SCL, SDA

(OUTPUT)

D15-D0

INT, MON

(2)

(4)

(5)

...

SDA (Open Drain)

No.A2131-3/27

LC822973

DAC characteristics

The characteristics of DAC (10bitDAC) for video that features this LSI are illustrated.

Zero scale output voltage

Full scale output voltage

Maximum conversion speed

Linear line error

within 0V 15mV

within 1.00V 80mV

30MHz

within 4LSB (VQFN84 [-10B] : within 4.5LSB)

Differential linear line error

Voltage reference level

within 1LSB

1.20 20mV

(Ta = +25°C)

Current consumption

*at the time of DV 3 = DV IO = 3V and DV 15 = 1.5V and AV 3 = 3V

DD DD DD DD

and AV 15 = 1.5V and MCLK50MHz

DD

* at the time of still picture (640×480) + OSD1 All screens + OSD2 All screens

Parameter

min

typ

max

unit

mA

μA

AV 15 (PLL operation current)

DD

0.5

10

35

2

1

15

DV 15 (core operation current)

DD

AV 3 (DAC operation current)*

DD

35

DV IO (IO operation current)

DD

5

DV 3 (SDRAM operation current)

DD

8

13

Standby current (clock input on)

300

100

18

Standby current (input clock off)**

μA

Standby current (input clock off + SDRAM/SRAM off)**

6

μA

* ‘typ’ here implies only that DACOUT always outputs its maximum current.

** Under the condition of tying input pin levels to H or L.

Standby current is at the condition of room temperature (+25°C)

No.A2131-4/27

LC822973

Package Dimensions

unit : mm (typ)

3442

TOP VIEW

5.0

SIDE VIEW

BOTTOM VIEW

0.5

J

H

G

F E

D C B A

0.28

SIDE VIEW

SANYO : ISB63(4.0X5.0)

Package Dimensions

unit : mm (typ)

3443

TOP VIEW

SIDE VIEW

BOTTOM VIEW

10.2

10.0

2

0.6

.2

0

(5.00)

1

2

(1.0)

0.4

0.18

SIDE VIEW

SANYO : VQFN84(10X10)

No.A2131-5/27

LC822973

Structure

Outline Specification

Item

NTSC/PAL video encoder

DAC

Outline

Multi rate and multi format video encoder that supports NTSC/PAL and ITU-601/SQ (square pixel).

10bit-1chD/A converter that integrates 7Ω driver.

Can be connected to TV directly without OP-amp or buffer.

Support 8/9/16/18/24bit bus (D, WR, RD, CS, A0) of I80 type.

CPU I/F

Video I/F

It corresponds to 5 format of RGB565, RGB666, YUV422 (8bit), YUV422 (8bit_BT656mode), and YUV422

(16bit). The writing operation is executed based on Sync signals.

Memory controller

Controls built-in (MCP) 16MbitSDRAM. Owns arbitration function and CPU access (drawing) is possible

as needed.

Matrix (CPU I/F)

Matrix (Video I/F)

PLL

Performs RGB → YUV conversion at the time of CPU → memory writing.

Performs RGB → YUV conversion at the time of video port → memory writing.

Generates high-speed clock for SDRAM.

OSD

A reading binary image from SDRAM is displayed in TV. Because the Alfa blend function is installed, it is

possible to select four stages by blend register.

Scaling function

×4 scaling processing at maximum is executed for reading image from SDRAM.

Can be set to H and V direction independently.

Autoview function

The issue of the command of each screen is unnecessary. Writing/reading control in the image area (two

bank or3 bank) set beforehand is executed automatically.

V-blanking period.

I/O

Can insert CGMS-A/WSS code into V-blanking period.

CMOS interface

Operation temperature

Package

-30°C to 85°C

ISB63 4mm × 5mm

VQFN84 10mm × 10mm

Power voltage (IO)

DV IO (1.6V - 3.4V)

DD

for ex. : 1.8V (1.6V - 2.0V), 3.0V (2.5V - 3.4V)

Power voltage

(digital core)

1.5V (1.35V - 1.65V)

Power voltage (PLL)

1.5V (1.35V - 1.65V)

3.0V (2.7V - 3.4V)

Power voltage

(for stacked SDRAM)

Power voltage

3.0V (2.7V - 3.4V)

(DAC analog part)

No.A2131-6/27

LC822973

Structure Block

DAC with 75Ω driver

SEL

Back Ground Display window gen.

Phase Comp

SEL

(3)DRAM CONTROL BLOCK

SDRAM controller

SEL

VIDEO I/F

CONF

No.A2131-7/27

LC822973

This LSI consists of 9 function blocks in the structure block above.

(1) CPU interface (CPUIF BLOCK)

The parameter setup such as mode setup/image area setup/video encoder characteristic of this LSI is possible via

bus from CPU. The image data writing to SDRAM achieves image port writing command that is in the same

command class as regular register and the same command class and keep writing continuously. This is a double

bank buffer structure and is able to write drawing data for 1 line without WAIT control.

(2) Host access (HOST ACCESS BLOCK)

The image writing is fulfilled from CPU interface for SDRAM.

This obtains line buffer in double bank buffer and the writing is carried out to SDRAM as accessing from CPU. It

also mounts 90, 180, 270 degrees rotation writing and writing function with matrix conversion processing besides

regular writing.

(3) SDRAM control (DRAM CONTROL BLOCK)

This LSI is MCP (multi chip) structure and has 16Mbit SDRAM built-in. This is the memory controller that controls

writing from CPU, reading for real-time display to video encoder and refresh processing for this memory.

(4) Reading control for display (DISPLAY ACCESS BLOCK)

This is the SDRAM reading processing part that controls transferring real-time image data to NTSC/PAL video

encoder.

This consists of scaling part that performs enlargement processing for image data that was read from SDRAM and

the buffer controlling part that provides video signal continuously to video encoder. The background processing

circuit that inserts fixed level is mounted in the buffer control part besides display window (image from SDRAM).

(5) Video encoder (VIDEO ENCODER BLOCK)

This supports both NTSC/PAL methods. All timing signals that are necessary for video signal are generated in this

block. This operates as a sync master and generates transfer request of real-time image data for DISPLAY ACCESS

BLOCK.

(6) Video interface (VIDEOIF BLOCK)

It is an interface part for the video rate writing. It writes based on a video sync signal and the dot clock. In case of

RGB format (RGB565, RGB666 etc.), the image is input to the host access part by processing the matrix at valid

period. The BT656 decoding is done if necessary at the YUV format. it supports both non-interlace and interlace

format. When the video interface is used, the data bus (D15 - D0) is treated as a dedicated image bus. The command

issue and the register access are executed with the I²C bus. It has the I²C bus control part in CPU interface part.

(7) Automatic image viewing (AUTOVIEW CONTROL BLOCK)

Automatic writing/reading sequence is executed by alternating the pre-defined image banks. Thus clean images

without the scan passing (tearing image) are displayed. Consecutive image data transfer follows after one time

command and parameter setting.

(8) VBI control (VBI CONTROL BLOCK)

The CGMS-A/WSS data is inserted. It has AUX function for the copy protect control etc.

(9) Others

To combine drawing from CPU and real-time request (continuous video signal is provided to NTSC/PAL video

encoder), SDRAM needs to be operated with high-speed clock. The high-speed master clock (MCLK) is created and

supported by using PLL for input clock (CKI).

No.A2131-8/27

LC822973

General Operation

[Operation 1.]

The rotation processing is performed at the time of SDRAM writing. As a result, a vertically long image of small size

such as QQVGA, QVGA, etc. is rotated 90 degrees and it is possible to display on TV (VGA size image).

NTSC

encoder

CPU I/F

SDRAM

QQVGA-QVGA

VGA

[Operation 2.]

The enlargement processing can be realized by filter processing that utilized line memory for reading data from

SDRAM. The small size image such as QQVGA and QVGA can be displayed on TV screen fully (VGA size). An

enlargement ratio can be set optionally (2×(n+1)/256, n: 128 to 255). If the displayed image after enlargement is smaller

than VGA size, other than target image can be set to background level (brightness/color setup possible).

This operation can be combined with the above rotation function.

Enlarge-

NTSC

CPU I/F

ment

SDRAM

encoder

circuit

QQVGA-QVGA

VGA

[Operation 3.]

The enlargement processing can be bypassed if writing image size from CPU fits VGA image size exactly. Degradation

of broad area level due to filter processing can be prevented.

NTSC

encoder

CPU I/F

SDRAM

VGA

[Moving image processing]

This LSI is the system that supports moving image that made writing from CPU and competitive operation of TV

display (real-time reading from SDRAM) possible by using high-speed clock operation.

The moving image performance (supportable frame rate) improves by raising SDRAM clock frequency through PLL

setup. However, the current consumption increases significantly.

No.A2131-9/27

LC822973

Corresponding video format

The video format that NTSC/PAL video encoder corresponds is described in the following tables.

((NTSC))

Mode

Dot clock

ITU-601

13.500MHz

858

SQ

12.2727MHz

780

Dot/line

Horizontal valid period

Vertical cycle

720

640

525 lines/frames

59.94Hz (field)

Vertical frequency

Vertical blanking period

Burst mask period

21 lines (line1-line21, line263-line284)

9 lines (line1-line9, line264-line272)

((PAL))

Mode

Dot clock

ITU-601

SQ

14.750MHz

944

13.500MHz

864

Dot/ line

Horizontal valid period

Vertical cycle

720

768

625 lines/frames

50Hz (field)

Vertical frequency

Vertical blanking period

Burst mask period

25 lines (line623-line22, line311-line335)

9 lines (line623-line6, line310-line318)

*The video encoder is the component signal processing for Y and C of 8 bit each as an internal processing. The dot

clock in the table above corresponds to the sampling clock at the time of 16bit processing of Y+C. To simplify post

filter, the video encoder processing performs ×2 oversampling. Therefore, the operation clock in video encoder part is

double of dot clock (27MHz, 24.54MHz, 29.5MHz, etc.).

No.A2131-10/27

LC822973

Pin Description

at

Pin name

Pol.

Dir

Description of function

reset

CKI

-

L

-

I

Master clock

-

1

XRST

DB17

DB16

Master reset, Low active

(bit17) extended bit. use at 18bit mode.

(bit16) extended bit. use at 18bit mode

-

Data bus, needs pull-up resistance externally

(unnecessary if either device always drives bus).

This bus is sharing for the VIDEOIF.

D[15:0]/

-

I/O

-

16

VIFVD[15:0]

A0/ (IDSEL)

RD/ (VIFVS)

WR/ (VIFHS)

CS/ (VIFFI)

INT

-

I

Address/ (IDSEL at VIDEOIF).

Read pulse/ (Vsync in at VIDEOIF).

Write pulse/ (Hsync in at VIDEOIF).

Chip select/ (Field index in at VIDEOIF).

Interrupt

-

1

L

H

I

-

I

-

O

"0"

MON

Monitor

Set "H" in case of VIDEOIF mode.

The command issue is via I²C bus.

USEVIF

H

I

-

1

SDA

-

I/O

I

SDA for I²C bus.

SCL for I²C bus.

DAC output

-

1

3

1

SCL

-

DACOUT

Ana

-

O

I

analog

DAC

IOB

DAC_IOB pin

DAC_COMP pin

DAC_VREF pin

DAC_IREF pin

VCNT pin

COMP

VREF

IREF

VCNT

analog

PLL

MODE[2:0]

CONF3

I

For test *

-

I

To decide input format

CONF2

To decide input format

-

I

-

1

/ (VIFDOT)

CONF1

/ (Dotclock in at VIDEOIF)

To decide input format

/ (VIFVACT)

CONF0

/ (V-valid period flag in at VIDEOIF)

To decide input format

/ (VIFHACT)

/ (H-valid period flag in at VIDEOIF)

DV 15

DD

Pow

-

DV

AV

for digital core (1.5V part)

-

4 (6)

4 (7)

3 (4)

1

DD

DV IO

DD

for digital I/O part

DV

3

for stacked SDRAM (it's controlled by internal switch cell)

for DAC analog (analog 3V)

DD

AV

3

DD

AV 15

DD

for PLL analog (analog 1.5V)

1

DV

SS

GND for digital part

GND for analog part

Total

6 (13)

2

AV

SS

63 (76)

* MODE pins are for testing.

They should be fixed to "L" normally.

No.A2131-11/27

LC822973

Pin assignment (ISB63/VQFN84/[SQFP100] )

Ball

[ISB]

-

Reference

[SQFP]

1

Pin name

I/O

Application

[VQFN]

-

NC

DV

-

2

3

4

5

6

7

H5

G6

H7

F4

F6

1

2

3

4

5

P

B

I

Digital GND

SS

SDA

SCL

I²C data / maintain open at CPUIF mode

I²C clock / connect to GND at CPUIF mode.

DV 15

DD

P

I

V

(digital core)

DD

CONF3

For format setting at CPUIF (bit3). connect to GND at

VIDEOIF mode.

G7

F5

F7

6

7

8

CONF2/ (VIFDOT)

CONF1/ (VIFVACT)

CONF0/ (VIFHACT)

I

For format setting at CPUIF (bit2).

/ Dotclock in at VIDEOIF mode.

For format setting at CPUIF (bit1).

/ V-valid flag in at VIDEOIF mode.

For format setting at CPUIF (bit0).

/ H-valid flag in at VIDEOIF mode.

9

10

E2

H5

E7

E6

E4

D7

E5

H5

C7

9

11

12

13

14

15

16

17

18

19

DV

3

P

I

V

(for stacked SDRAM)

DD

10

11

12

13

14

15

16

17

Digital GND

SS

CKI

System clock input

DV IO

DD

P

I

V

(Digital IO)

DD

XRST

INT

System reset ("L"==reset)

INT signal ("L"==interrupt generation)

Monitor pin.

O

P

I

MON

DV

SS

Digital GND

A0/ (IDSEL)

Address/ID address select at VIDEOIF mode.

(0 : 8'b0100_000_r, 1 : 8'b0100_001_r).

/CS signal/field index at VIDEOIF mode.

D6

B7

H5

-

18

19

20

-

20

21

22

23

|

CS/ (VIFFI)

I

DV 15

DD

P

-

V

(digital core)

DD

DV

SS

Digital GND

NC

-

|

-

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

NC

-

C6

A7

E6

B6

A6

C5

B5

A5

D5

D4

A4

B4

C4

A3

E3

B3

A2

C3

D3

B2

A1

C2

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

DB17

DB16

I

bit17 for 18bit data transfer format.

bit16 for 17bit data transfer format.

I

DV IO

DD

P

B

I

V

(Digital IO)

DD

D15/ (VIFVD15)

D14/ (VIFVD14)

D13/ (VIFVD13)

D12/ (VIFVD12)

D11/ (VIFVD11)

D10/ (VIFVD10)

D9/ (VIFVD9)

D8/ (VIFVD8)

D7/ (VIFVD7)

WR/ (VIFHS)

CPU data bus/Video data bus. (MSB)

|

/WR pulse/Hsync at VIDEOIF mode.

/RD pulse/Vsync at VIDEOIF mode.

RD/ (VIFVS)

I

DV 15

DD

P

B

V

(digital core)

DD

Digital GND

V (Digital IO)

DD

DV

SS

DV IO

DD

D6/ (VIFVD6)

D5/ (VIFVD5)

D4/ (VIFVD4)

D3/ (VIFVD3)

D2/ (VIFVD2)

CPU data bus/Video data bus.

|

CPU data bus/Video data bus.

* The product version are ISB63 and VQFN84. SQFP100 is a package for our evaluation (reliability test).

Continued to the next page.

No.A2131-12/27

LC822973

Continued from the previous page.

Ball

[ISB]

-

Reference

[SQFP]

50

Pin name

I/O

Application

[VQFN]

-

NC

|

-

|

-

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

-

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

|

NC

DV

-

D2

B1

C1

E3

F1

D1

E1

D1

F1

F2

G1

G2

H1

G1

F2

-

P

B

P

-

Digital GND

SS

D1/ (VIFVD1)

D0/ (VIFVD0)

CPU data bus/Video data bus.

CPU data bus/Video data bus. (LSB)

DV 15

DD

V

(digital core)

(Digital IO)

DD

DV IO

DD

DV

SS

Digital GND

V (for stacked SDRAM)

DD

DV

3

DD

SS

Digital GND

DV IO

DD

V

(Digital IO)

DD

Digital GND

V (for stacked SDRAM)

DV

SS

DV

3

DD

SS

DD

Digital GND

DV 15

DD

V

(digital core)

DD

DV

NC

|

3

(for stacked SDRAM)

DD

Digital GND

SS

-

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

-

76

77

78

79

80

NC

AV

-

J1

3

P

Ana

P

I

AV

(DAC analog : 3V part)

DD

AV

(DAC analog : 3V part)

DD

H2

G3

J2

H3

F3

J3

F1

J4

H4

G4

J5

F4

H5

J6

G5

H6

J7

-

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

1

GND (analog for DAC)

DAC_VREF pin

DAC_COMP pin

DAC_IREF pin

SS

VREF

COMP

IREF

IOB

DAC_IOB pin

DACOUT

DAC_ video output

DV IO

DD

V

(Digital IO)

DD

MODE2

MODE1

MODE0

USEVIF

mode setting (bit2), should be fixed "L"

mode setting (bit1), should be fixed "L"

mode setting (bit0), should be fixed "L"

To use VIDEOIF mode ("H":select VIDEOIF)

I

DV 15

DD

P

Ana

P

-

V

(digital core)

DD

Digital GND

AV (PLL analog : 1.5V part)

DV

SS

AV 15

DD

AV

2

GND(PLL analog)

VCNT pin for PLL

SS

VCNT

DV IO

DD

V

(Digital IO)

DD

NC

-

* The product version are ISB63 and VQFN84. SQFP100 is a package for our evaluation (reliability test).

No.A2131-13/27

LC822973

Pin Layout (ISB63)

A1 marking

A

B

C

D

D3

D1

D0

DV

RD

D8

D7

D11

D12

D13

D10

D14

D15

DB17

CS

DB16

DDIO

D4

D2

DV

DV 15

DD

SS

D6

D5

WR

D9

A0

INT

DV

SS

E

F

G

H

J

DV

3

DV

3

DD

DV 15

DD

XRST

MON

DV IO

DD

CKI

DD

DV IO

DD

DV

IOB

VREF

IREF

DV 15

DD

CONF1

CONF3

SDA

CONF0

CONF2

SCL

SS

DV

3

DD

MODE0

MODE1

MODE2

4

AV

2

SS

DV 15

DD

AV

1

DV

VCNT

SS

AV

3

COMP

DACOUT

USEVIF

AV 15

DD

DV IO

DD

1

2

3

5

6

7

Top View

No.A2131-14/27

LC822973

Peripheral Circuit Example

An example of LPF

3.3μH

L

DB17

DB16

use at 18bit mode.

"0"-command

330pF

LPF

330pF

"AV "

SS

"AV

SS

"

D15-0

A0

DACOUT

IOB

CVBS

100μF--220μF

Recommendation:

CS

WR

RD

INT

220μF

monitor pin

open

DAC Analog

1μF AV

DD

LC822973

MON

COMP

VREF

SDA

SCL

0.1μF

560Ω

AV

SS

MODE2-0

CONF3-0

IREF

setting

OSC

100--150Ω

CKI

PLL Analog

VCNT

System

Reset

0.1μF--0.22μF

XRST

via CPUIF

An example of LPF

3.3μH

L

DB17

DB16

use at 18bit mode.

330pF

"AV "

SS

"AV

SS

"

VIFVD

VIFFI

D15-0

CS

LPF

DACOUT

IOB

CVBS

VIFHS

VIFVS

WR

RD

100μF--220μF

Recommendation:

CONF3

CONF2

CONF1

CONF0

220μF

VIFDOT

VIFVACT

VIFHACT

DAC Analog

1μF AV

DD

COMP

VREF

LC822973

0.1μF

560Ω

IDSEL(choose ID)

A0

I²C

needed

pullup

SDA

AV

SS

SDA

SCL

IREF

INT

monitor pin

100--150Ω

MON

PLL Analog

VCNT

MODE2-0

setting

0.1μF--0.22μF

CKI

OSC

System

Reset

XRST

via VIDEOIF

* The MODE2:0 pins are for test use, so please tie them "L".

* Please do not leave input pins OPEN.

* Above figure shows in case of 27MHz (24.54MHz) clock input.

When the dot clock is generated with PLL (.e.g.: CKI==26MHz), it is necessary to change in PLL loop filter's

constant. Please refer to " 7.12. Consideration of 26.0MHz clock input" paragraph for details.

No.A2131-15/27

LC822973

Writing image format (via CPU I/F)

The hardware adopts 24/18/16/9/8bit RGB format and YUV422 format of 24/18/16/9/8 as a CPU writing via CPU-I/F.

Input format is determined by CONF[3:0] pins.

The RGB → YUV matrix processing operates automatically when RGB input is formatted.

CONF[3:0]

0

1

2

3

4

5

6

7

8

Data

RGB565

YUV422

16bit

RGB666

RGB565

Transfer

Format

16bit

18bit

(×1)

1

18bit

16bit

(×1)

(×2)

trans num

1

-

1

-

2

1

-

2

-

1

-

1

-

2

-

2

-

1

-

2

-

1

-

2

-

1

2

-

DB17

DB16

D[15]

D[14]

D[13]

D[12]

D[11]

D[10]

D[9]

17

-

R5

-

16

15

14

13

12

11

10

9

-

R4

-

R5

R4

R3

R2

R1

G5

G4

G3

G2

G1

G0

B5

B4

B3

B2

B1

Ya7

Ya6

Ya5

Ya4

Ya3

Ya2

Ya1

Ya0

U7

Yb7

Yb6

Yb5

Yb4

Yb3

Yb2

Yb1

Yb0

V7

R3

R2

R1

R0

G5

G4

G3

G2

G1

G0

B5

B4

B3

B2

B1

B0

R5

R4

R3

R2

R1

R0

G5

G4

G3

G2

G1

G0

B5

B4

B3

B2

B1

B0

-

R5

R3

R2

R1

R0

G5

G4

G3

G2

G1

G0

B5

B4

B3

B2

B1

B0

R5

R4

R3

R2

R1

R0

G5

G4

G3

-

G2

G1

G0

B5

B4

B3

B2

B1

B0

-

R5

R4

R3

R2

R1

G5

G4

G3

-

G2

G1

G0

B5

B4

B3

B2

B1

-

R4

-

D[8]

8

-

R5

R4

R3

R2

R1

R0

G5

G4

G3

G2

G1

G0

B5

B4

B3

B2

B1

B0

-

D[7]

7

-

R5

R4

R3

R2

R1

G5

G4

G3

G2

G1

G0

B5

B4

B3

B2

B1

D[6]

6

U6

V6

-

D[5]

5

U5

V5

-

D[4]

4

U4

V4

-

D[3]

3

U3

V3

-

D[2]

2

U2

V2

-

D[1]

1

U1

V1

-

D[0]

0

U0

V0

-

For CONF==2:RGB666_18bit mode, R5 and R4 correspond DB17 and DB16 pins, respectively.

Otherwise, please connect DB17, 16 pins to GND.

CONF[3:0]

Data

9

10

11

12

13

14

15

RGB888

RGB666

RGB888

Transfer Format

24bit

18bit

24bit

(×2)

(×3)

trans num

1

-

2

-

1

-

2

1

2

-

3

-

1

2

-

3

-

1

2

-

3

1

-

2

-

3

1

-

2

-

3

-

DB17

DB16

D[15]

D[14]

D[13]

D[12]

D[11]

D[10]

D[9]

17

16

15

14

13

12

11

10

9

-

R5

R4

R3

R2

R1

R0

-

R7

R6

R5

R4

R3

R2

R1

R0

G7

G6

G5

G4

G3

G2

G1

G0

B7

B6

B5

B4

B3

B2

B1

B0

-

R7

R6

R5

R4

R3

R2

R1

R0

-

G7

G6

G5

G4

G3

G2

G1

G0

B7

B6

B5

B4

B3

B2

B1

B0

G5

B5

B4

B3

B2

B1

B0

-

Ra7

Ra6

Ra5

Ra4

Ra3

Ra2

Ra1

Ra0

Ga7

Ga6

Ga5

Ga4

Ga3

Ga2

Ga1

Ga0

Ba7

Ba6

Ba5

Ba4

Ba3

Ba2

Ba1

Ba0

Rb7

Rb6

Rb5

Rb4

Rb3

Rb2

Rb1

Rb0

Gb7

Gb6

Gb5

Gb4

Gb3

Gb2

Gb1

Gb0

Bb7

Bb6

Bb5

Bb4

Bb3

Bb2

Bb1

Bb0

Ra7

Ra6

Ra5

Ra4

Ra3

Ra2

Ra1

Ra0

Rb7

Rb6

Rb5

Rb4

Rb3

R2

Ga7

Ga6

Ga5

Ga4

Ga3

Ga2

Ga1

Ga0

Gb7

Gb6

Gb5

Gb4

Gb3

Gb2

Gb1

Gb0

Ba7

Ba6

Ba5

Ba4

Ba3

Ba2

Ba1

Ba0

Bb7

Bb6

Bb5

Bb4

Bb3

Bb2

Bb1

Bb0

-

G4

-

G3

-

G2

-

G1

-

G0

-

D[8]

8

-

D[7]

7

-

R7

G7

G6

G5

G4

G3

G2

G1

G0

B7

B6

B5

B4

B3

B2

B1

B0

D[6]

6

-

R6

R5

R4

R3

R2

R1

R0

D[5]

5

-

R5

R4

R3

R2

R1

R0

G5

G4

G3

G2

G1

G0

B5

B4

B3

B2

B1

B0

D[4]

4

-

D[3]

3

-

D[2]

2

-

D[1]

1

-

Rb1

Rb0

D[0]

0

-

* 16bit or 8bit command area is to be sent within heavy-lined area. CONF==5, 6, 7, 8, 11, 12, and 15 correspond 8bit

command data, and the 16bit parameter register needs double transfer.

* Hatched area shows unused pins. "L" level is always output, so please keep them open.

* For CONF==14:24bit (×3) format, a dummy write of 0×0 data is required every time after sending all the frame data.

* For CONF==1:16bit-YUV422 format, RGB to YUV matrix conversion can be enabled by register setting, SYSCTL1

(bit5) MTXON, which is useful for the mixed format system of RGB565 and YUV422.

No.A2131-16/27

LC822973

Writing image format (via VIDEO I/F)

Writing from video IF corresponds to various entry formats such as YUV422 (8bit), YUV422 (8bitBT656decode),

YUV422 (16bit), RGB565 (16bit), and RGB666 (18bit).

When video IF is used, the USEVIF pin is set to "H". The VIFFMT register is set and a necessary input format is

decided at the same time. In this LSI, internal processing is YUV system.

The RGB → YUV matrix processing operates automatically when RGB is input.

USEVIF

VIFFMT[3:0]

Data Format

BT656decode

Transfer

1

0

1

2

3

4

YUV422

No

5

6

YUV422

RGB565

RGB666

No

16bit

(×2)

Yes

16bit

(×2)

16bit

(×1)

1

16bit

(×1)

1

18bit

(×1)

1

Format

(×2)

Trans num

DB17

1

2

-

1

-

2

-

1

-

2

1

-

2

-

17

16

15

14

13

12

11

10

9

-

R5

R4

R3

R2

R1

R0

G5

G4

G3

G2

G1

G0

B5

B4

B3

B2

B1

B0

DB16

-

D15/VIFVD15

D14/VIFVD14

D13/VIFVD13

D12/VIFVD12

D11/VIFVD11

D10/VIFVD10

D9/VIFVD9

D8/VIFVD8

D7/VIFVD7

D6/VIFVD6

D5/VIFVD5

D4/VIFVD4

D3/VIFVD3

D2/VIFVD2

D1/VIFVD1

D0/VIFVD0

-

Y7

R5

R4

R3

R2

R1

G5

G4

G3

G2

G1

G0

B5

B4

B3

B2

B1

-

Y6

-

Y5

-

Y4

-

Y3

-

Y2

-

Y1

8

-

Y0

7

U7/V7

U6/V6

U5/V5

U4/V4

U3/V3

U2/V2

U1/V1

U0/V0

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

U7/V7

U6/V6

U5/V5

U4/V4

U3/V3

U2/V2

U1/V1

U0/V0

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

R5

R4

R3

R2

R1

G5

G4

G3

G2

G1

G0

B5

B4

B3

B2

B1

G2

G1

G0

B5

B4

B3

B2

B1

R5

R4

R3

R2

R1

G5

G4

G3

U7/V7

U6/V6

U5/V5

U4/V4

U3/V3

U2/V2

U1/V1

U0/V0

6

5

4

3

2

1

0

USEVIF

VIFFMT[3:0]

Data Format

BT656decode

Transfer

1

7

8

9

10

RGB666

RGB888

No

18bit

(×2)

18bit

24bit

Format

(×2)

(×3)

2

Trans num

DB17

1

2

-

1

2

1

2

3

-

1

-

3

-

17

16

15

14

13

12

11

10

9

-

DB16

-

D15/VIFVD15

D14/VIFVD14

D13/VIFVD13

D12/VIFVD12

D11/VIFVD11

D10/VIFVD10

D9/VIFVD9

D8/VIFVD8

D7/VIFVD7

D6/VIFVD6

D5/VIFVD5

D4/VIFVD4

D3/VIFVD3

D2/VIFVD2

D1/VIFVD1

D0/VIFVD0

R5

R4

R3

R2

R1

R0

G5

G4

G3

G2

G1

G0

B5

B4

B3

B2

B1

B0

-

R5

R3

R2

R1

R0

G5

G4

G3

G2

G1

G0

B5

B4

B3

B2

B1

B0

-

R4

-

8

-

7

-

R7

R6

R5

R4

R3

R2

R1

R0

G7

G6

G5

G4

G3

G2

G1

G0

B7

B6

B5

B4

B3

B2

B1

B0

6

-

5

-

R5

R4

R3

R2

R1

R0

G5

G4

G3

G2

G1

G0

B5

B4

B3

B2

B1

B0

4

-

3

-

2

-

1

-

0

-

* The width of the bus at video IF is decided by the register setting. (USEVIF=="H").

All the image ports are set to the input at video IF. Please connect an unused bit with GND (It shows "-" in the table).

No.A2131-17/27

LC822973

Command

Command Type/Register Map

There are two types of command. One is to be able to operate by a command itself and the other needs a parameter.

In case of writing a command, A0 should be set to 0 and A0 should be set to 1 in case of writing or reading a parameter.

If other command is executed before setting a parameter, the command that is in the middle of setting is cancelled.

Other than 9bit interface

How to set command

〈Command that doesn’t need a parameter〉

A[0]

0

D[15:0]

command

command setting

command is valid

〈Command that needs a parameter〉

A[0]

0

D[15:0]

command

command setting

parameter setting

1

parameter

command is valid

8bit/9bit interface

How to set command

〈Command that doesn’t need a parameter〉

A[0]

D[7:0]

0

command

command setting

parameter setting

1

parameter

command is valid

〈Command that needs a parameter〉

A[0]

0

D[7:0]

command

command setting

parameter setting

A[0]

1

D[15:8]

parameter

A[0]

1

D[7:0]

parameter

command is valid

* 9bit transfer CONF="5", 8bit transfer CONF="7"/CONF="11" : data bus[15:8] should be used.

* 9bit transfer CONF="6", 8bit transfer CONF="8"/CONF="12"/CONF="15" : data bus[7:0] should be used.

No.A2131-18/27

LC822973

I²C access

When video I/F is used (USEVIF==1), the register access from the host uses the I²C bus.

One sending data size of the I²C bus is 8bit.

Additionally, I²C is not applicable the concept of the address (A0==0: the command and A0==1: parameter) used with

parallel CPUIF.

Therefore, a special access way is necessary as follows respectively.

Stand-alone command : not need parameter--IMGWRITE,IMGREADGO etc.)

write "00" into the target address

target address+"00"

(normal write : need 1word parameter)

write sequentially "upper byte" → "lower byte" into target address.

address is "upper : normal address×2" , "lower : normal address×2+1" in case of I²C.

target address(upper)+"writing data for upper byte"

target address(lower)+"writing data for lower byte"

*Please keep the order "upper byte → lower byte".

When the host accessing is finished, internal transfer with word align will start.

(normal read : need 1word parameter)

read sequentially "upper byte" → "lower byte" from target address.

address is "upper : normal address×2" , "lower : normal address×2+1" in case of I²C.

target address(upper)+"reading data for upper byte"

target address(lower)+"reading data for lower byte"

The read order from upper byte or lower byte doesn't especially have regulations.

Only one byte accessing is also possible.

(image writing command : AUTOVIEWON,IMGWRITE,OSDWRITE etc.)

write via special image port (IMGPORT : 0×FD).

After issuing the image writing command, the data writing is necessary

in accurate the order. (upper → lower → upper → lower...)

On the other hand, the data writing operation from the host is unnecessary

because the automatic writing is done with a pin (image data/dot clock) at video IF.

target address+"00" ← Issue AUTOVIEWON command etc.

IMGPORT address+"data writing for upper byte : at 1st pixel"

IMGPORT address+"data writing for lower byte : at 1st pixel"

IMGPORT address+"data writing for upper byte : at 2nd pixel"

|||||

IMGPORT address+"data writing for upper byte : at Nth pixel"

IMGPORT address+"data writing for lower byte : at Nth pixel"

(image reading command : IMGREAD)

read via special image port (IMGPORT : 0×FD).

The access order is same as parallel CPU IF : IMGREADGO → IMGREAD → image reading.

IMGREADGO+"00" ← Issue IMGREADGO command.

IMGREAD+"00" ← Issue IMGREAD command.

IMGPORT address+"reading target pixel's upper byte"

IMGPORT address+"reading target pixel's lower byte"

Please keep the order "upper byte → lower byte".

Because the I²C bus is low-speed, status read after IMGREADGO command is unnecessary.

(status read :)

Status and a usual register are distinguished referring to the A0 address at parallel IF.

On the other hand, it corresponds in a special address in I²C.

(STAT upper : STATUP : 0×FE, STAT lower : STATDN : 0×FF).

STATUP address+"reading upper byte of STATUS register"

STATDN address+"reading upper byte of STATUS register"

The read order from upper byte or lower byte doesn't especially have regulations.

Only one byte accessing is also possible.

No.A2131-19/27

LC822973

List of Command (A0==0)

The following tables are memory maps for 16bitCPU bus with 16bit width parameters.

I²C takes Big ENDIAN system.

upper byte : I²C_address = Add × 2

lower byte : I²C_address = Add × 2 + 1

No

1

Add

Command name

CLKCONT

Function

Clock control

length

1word

Description

0×01

VCLK_MODE, PLLON, DACON, DRAM sleep, Mode setting at

VIDEOIF

2

3

4

5

6

0×02

0×03

0×04

0×05

0×06

DIV_M

DIV_N

DIV_P

reserved

INT

PLL control

-

1word

-

1/M (12bit)

1/N (12bit)

1/P (8bit), S0--S3

-

Interrupt

1word

INT factor

*) this can be issued during memory writing

INT factor clear

7

8

0×07

0×08

INTEN

Interrupt

1word

*) this can be issued during memory writing

Scaler and Matrix ON/OFF, scan direction, display OFF, filter

setup, enhancer setup, etc.

SYSCTL1

System setup

9

0×09

0×0a

0×0b

0×0c

0×0d

0×0e

0×0f

SYSCTL2

System setup

MEMCTL setup

CPU drawing

Image reading

Drawing end

1word

-

Transfer mode setup, V sync setup, etc.

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

SYSCTL3

Polarity, system control, etc. (others, spare)

SDRAM burst length, latency, mode, etc.

SDRAM refresh interval

MEMSET1

MEMSET2

MEMSET3

IMGWRITE

IMGREADGO

IMGREAD

IMGABORT

SCALE

SDRAM initial sequence setup

CPU → SDRAM Writing

-

SDRAM → CPU Reading start

SDRAM → CPU Reading (acquiring data)

CPU drawing forced termination

Scaling image ratio setup

0×10

0×11

0×12

0×13

0×14

0×15

0×16

0×17

0×18

0×19

0×1a

0×1b

0×1c

0×1d

0×1e

0×1f

1word

-

Scale up

1word

-

reserved

-

reserved

-

WFBHLEN

WFBVLEN

WFBHSTART

WFBVSTART

RFBHOFST

RFBVOFST

DSPHOFST

DSPVOFST

DSPHLEN

DSPVLEN

BGCOLOR1

BGCOLOR2

ENCMODE

ENCGAIN1

ENCGAIN2

ENCBST1

ENCBST2

ENCBBPLT

ENCRHVAL

Coordinate setup

Background color

VENC setup

1word

SDRAM address length for CPU drawing (H)

SDRAM address length for CPU drawing (V)

horizontal start point for SDRAM writing

vertical start point for SDRAM writing

Real-time reading SDRAM address offset (H)

Real-time reading SDRAM address offset (V)

Real-time reading display position offset (H)

Real-time reading display position offset (V)

Real-time reading display position length (H)

Real-time reading display position length (V)

Background color Y signal (use only low 8bit)

Background color UV signal (U: upper, V: lower)

Operation mode, filter switch, interlace setup

Level setup, bright, contrast

0×20

0×21

0×22

0×23

0×24

0×25

0×26

0×27

VENC setup

Level setup, color gain

VENC setup

Burst gain setup

VENC setup

Burst phase setup

VENC setup

Blueback pallet setup

Video timing

Horizontal valid period signal to the memory controller

adjustment

40

41

42

43

44

0×28

0×29

0×2a

0×2b

0×2c

ENCHBLK

ENCVBLK

VERSION

Video timing

Other

1word

Horizontal Blanking period adjustment

Vertical Blanking period adjustment

Version register

TESTMODE

OSDCONT_1

For test

-

OSD1 setup

SDRAM burst length,OSD1 ON/OFF, etc.

Continued to the next page.

No.A2131-20/27

LC822973

Continued from the previous page.

No

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

|

Add

0×2d

0×2e

0×2f

Command name

OSDWFBHSTART

OSDWFBVSTART

OSDWFBHLEN

OSDWFBVLEN

OSDRFBHOFST_1

OSDRFBVOFST_1

OSDHOFST_1

OSDVOFST_1

OSDHLEN_1

Function

OSD1, 2 setup

OSD1 setup

length

1word

-

Description

SDRAM address offset for OSD drawing (H)

SDRAM address offset for OSD drawing (V)

SDRAM address length for OSD drawing (H)

SDRAM address length for OSD drawing (V)

SDRAM reading address (H) offset for OSD1

SDRAM reading address (V) offset for OSD1

display position offset (H) for OSD1

display position offset (V) for OSD1

display position length (H) for OSD1

display position length (V) for OSD1

burst length (SDRAM), OSD2 ON/OFF, etc.

SDRAM reading address offset (H) for OSD2

SDRAM reading address offset (V) for OSD2

display position offset (H) for OSD2

display position offset (V) for OSD2

display position length (H) for OSD2

display position length (V) for OSD2

OSD Y adjustment (Up: OSD1/Down: OSD2)

OSD U adjustment (Up: OSD1/Down: OSD2)

OSD V adjustment (Up: OSD1/Down: OSD2)

CPUOSD → SDRAM DRAW

0×30

0×31

0×32

0×33

0×34

0×35

0×36

0×37

0×38

0×39

0×3a

0×3b

0×3c

0×3d

0×3e

0×3f

OSD1 setup

OSDVLEN_1

OSD1 setup

OSDCONT_2

OSD2 setup

OSDRFBHOFST_2

OSDRFBVOFST_2

OSDHOFST_2

OSDVOFST_2

OSDHLEN_2

OSD2 setup

OSDVLEN_1

OSD2 setup

OSDCOLOR_Y

OSDCOLOR_U

OSDCOLOR_V

OSDWRITE

OSD1,2 setup

OSD drawing

VIDEOIF setup

A-VIEW setup

A-VIEW start

A-VIEW stop

A-VIEW setup

CGMSA setup

WSS setup

0×40

0×41

0×42

0×43

0×44

0×45

0×46

0×47

0×48

0×49

0×4a

0×4b

0×4c

0×4d

0×4e

0×4f

OSDABORT

-

CPUOSD → DRAW ABORT

VIFSYS

1word

-

Data ordering, sync polarity, internal valid flag on/off etc.

Internal valid flag (start position of H-flag)

Internal valid flag (end position of H-flag)

Internal valid flag (start position of V-flag)

Internal valid flag (end position of V-flag)

Num of bank at AUTOVIEW mode

Strat AUTOVIEWing

VIFHACTSTA

VIFHACTEND

VIFVACTSTA

VIFVACTEND

AVIEWSYS

AUTOVIEWON

AUTOVIEWOFF

AVWFBHSTART_0

AVWFBVSTART_0

AVWFBHSTART_1

AVWFBVSTART_1

AVWFBHSTART_2

AVWFBVSTART_2

CGMSA_CODE

CGMSA_TRM

WSS_CODE

-

Stop AUTOVIEWing

1word

Start position of bank#0 (H)

Start position of bank#0 (V)

Start position of bank#1 (H)

Start position of bank#1 (V)

Start position of bank#2 (H)

0×50

0×51

0×52

0×53

0×54

0×55

|

Start position of bank#2 (V)

CGMSA code setting

CGMSA position setting

WSS code setting

WSS_TRM

WSS setup

WSS position setting

reserved

|

112

0×70

reserved

for I²C

113

0×7E

0×7F

0×FC (I²C) : no use

Image port

0×FD (I²C) : IMGPORT

0×FE (I²C) : status (upper)

0×FF (I²C) : status (lower)

114

Status

No.A2131-21/27

LC822973

AC characteristics (CPU bus timing)

Parallel I/F (I80 like)

twas twah

twcs twch

A

CPU WRITE

CS

twlw

twhw

/WR

/RD

tcycw

high

twds twdh

Data

tras trah

trcs trch

A

CPU READ

CS

/WR

/RD

high

trlw

trhw

tcycr

trdh

tacc

Data

Item

System cycle time (write) [×1 transfer]

System cycle time (read) [×1 transfer]

System cycle time (write) [×2, ×3 transfer]

System cycle time (read) [×2, ×3 transfer]

Address setup time (write)

Address hold time (write)

Address setup time (read)

Address hold time (read)

CS setup time (write)

Symbol

Condition

min

3T*

typ

max

unit

cyc

ns

tcycw

tcycr

tcycw

tcycr

twas

twah

tras

write

read

write

read

A

3T*

2T*

15

5

A

ns

A

25

5

ns

trah

A

ns

twcs

twch

trcs

/CS

/WR

/RD

15

5

ns

CS hold time (write)

ns

CS setup time (read)

25

5

ns

CS hold time (read)

trch

ns

/WR low side pulse width

/WR high side pulse width

/RD low side pulse width

/RD high side pulse width

Data setup time

twlw

twhw

trlw

20

15

25

15

5

ns

trhw

twds

twdh

tacc*

Trdh

ns

Data [15:0]

ns

Data hold time

ns

Read access time

20

10

ns

Data hold time

ns

* T ⇒ MCLK (master clock) 1 cycle .ex. MCLK: 50MHz ⇒ 1T is 20ns.

*tacc ⇒ from (/RD) or (/CS)↓

No.A2131-22/27

LC822973

I²C transfer sequence and AC characteristics

I²C slave circuit is equipped to the LSI for the Video-I/F mode, which enables to read and to write

command registers via SDA and SCL pins.

IDSEL pin sets one of two pre-defined device ID's,

IDSEL: 0 then device ID=0×40 (0100_000_r)

IDSEL: 1 then device ID=0×42 (0100_001_r)

The transfer sequence of I²C is explained below.

No.A2131-23/27

LC822973

tR

tHIGH

tBUF

tF

tSU:STO

tHD:STA

SDA

SCL

tF

tR

tSU:STA

S

P

S

tLOW

START

STOP

Condition

I/O timing of I²C bus (at the time of SCL 400kHz cycle mode)

Symbol

Item

Bus open period

Hold time (Start)

SCL_Lo period

SCL_Hi period

Data rising

min

max

Unit

μs

tBUF

1.3

0.6

1.3

tHD: STA

tLOW

tHIGH

tR

300

tF

Data falling

tSU: STA

tSU: STO

Setup time (Start)

Setup time (Stop)

0.6

tHD:DAT

SDA

SCL

tHIGH

tSU:DAT

I/O timing of I²C bus (at the time of high speed operation)

Symbol

tSU: DAT

Item

Setup time (Data)

Hold time (Data)

SCL_Hi period

min

max

Unit

ns

100

0

tHD: DAT

tHIGH

ns

150

ns

No.A2131-24/27

LC822973

AC characteristics (VIDEO I/F timing)

DB17,DB16

VIFVD15-0

VIFHS

VIFVS

VIFFI

VIFHACT

VIFVACT

vifts tifth

dotwl

dotwh

dotcyc

VIFDOT

(dotclock)

SymbolItem

Data/Flag

Symbol

vifts

Condition

DB17/16

min

typ

max

unit

ns

Setup time

VIFVD, VIFHS,

VIFVS, VIFFI

VIFHACT

10

VIFVACT

Data/Flag

Hold time

vifth

DB17/16

VIFVD, VIFHS,

VIFVS, VIFFI

VIFHACT

5

ns

VIFVACT

Clock low side pulse width

Clock high side pulse width

Clock cycle time

dotwl

VIFDOT

15

30

ns

dotwh

dotcyc

VIFDOT

No.A2131-25/27

LC822973

AC characteristics (Reset condition)

Fixing XRST pin to Lo level initializes the internal FF. The filter circuit that used delay device is embedded inside so

that an error operation won’t be performed even if a noise is on XRST pin. The condition of Lo period is as follows.

XRST

20ns(min)

Lo period restricyion of XRST pin

Power turn-ON/turn OFF-conditions

This LSI needs digital power (DV 15 [core], DV 3 [DRAM], DV IO), analog power for DAC (AV 3) and

DD DD DD DD

analog power for PLL (AV 15). Power turn ON/turn OFF conditions is shown in the following sequence diagram.

DD

It is desirable for DV 15 and DV IO/DV 3 to maintain

DD DD DD

DV 15 > = DV IO/DV 3/AV 3/AV 15 relation as below or at the same time.

DD DD DD DD DD

However, the condition is acceptable when the period, which is the reversed relation, is within 1ms.

Simultaneous of power turn ON / turn OFF of DV IO/DV 3/AV 3/AV 15 is all preferable. However, there is

DD DD DD DD

no problem even if the time difference is mutually generated.

However, please avoid keeping only a certain power supply in the state of power turn OFF.

ON

DV 15

DD

OFF

same time or

DV 15 ON early

same time or

DV 15 OFF later

DD

ON

OFF

DV IO

DD

OFF

DV

AV

3

DD

ON

3

OFF

DD

AV 15

DD

Simultaneous of power turn ON/turn OFF of DV IO/DV 3/

DD DD

AV 3/AV 15 is all preferable. However, there is no

DD

problem even if the time difference is mutually generated.

Power turn-ON/turn-OFF sequence

No.A2131-26/27

LC822973

SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using

products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition

ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.

products described or contained herein.

Regarding monolithic semiconductors, if you should intend to use this IC continuously under high temperature,

high current, high voltage, or drastic temperature change, even if it is used within the range of absolute

maximum ratings or operating conditions, there is a possibility of decrease reliability. Please contact us for a

confirmation.

SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all

semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or

malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise

to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt

safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not

limited to protective circuits and error prevention circuits for safe design, redundant design, and structural

design.

In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are

controlled under any of applicable local export control laws and regulations, such products may require the

export license from the authorities concerned in accordance with the above law.

No part of this publication may be reproduced or transmitted in any form or by any means, electronic or

mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise,

without the prior written consent of SANYO Semiconductor Co.,Ltd.

Any and all information described or contained herein are subject to change without notice due to

product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the

SANYO Semiconductor Co.,Ltd. product that you intend to use.

Upon using the technical information or products described herein, neither warranty nor license shall be granted

with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third

party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's

intellectual property rights which has resulted from the use of the technical information and products mentioned

above.

This catalog provides information as of October, 2012. Specifications and information herein are subject

to change without notice.

PS No.A2131-27/27


型号：	LC822973
厂家：	SANYO SEMICON DEVICE
描述：	CMOS LSI TV Image Viewer LSI CMOS LSI电视图像浏览器LSI 电视
文件：	总27页 (文件大小：214K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LC822973 [SANYO]

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