SED1632DOA [SEIKO]
LIQUID CRYSTAL DISPLAY DRIVER, UUC98, ALUMINUM PAD, DIE-98;
| 型号： | SED1632DOA |
| 厂家： | 
SEIKO EPSON CORPORATION |
| 描述： | LIQUID CRYSTAL DISPLAY DRIVER, UUC98, ALUMINUM PAD, DIE-98 驱动 接口集成电路 |
| 文件： | 总6页 (文件大小：33K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SED1632
CMOS DOT MATRIX HIGH DUTY LCD DRIVER
CMOS 86-bit Common Driver
High Voltage Resistant Output
Max 1/300 in Display Duty
CMOS High Voltage Resistant Process
•
•
•
•
■ DESCRIPTION
The SED1632 is an 86 output dot matrix LCD common (row) driver for driving a high-capacity LCD panel at
duty cycles higher than 1/64 (up to 1/300). The LSI has a wide range of LCD driving voltages. Due to the
architecture of the SED1632, the LCD driving power is isolated from VDD. This provides the ability to adjust
the offset bias independently of VDD. These unique features allow the SED1632 to interface with a variety of
LCD panels.
The SED1632 is used in conjunction with the SED1600 (80 segment driver), the SED1601 (80 segment
driver) and the SED1620 (128 segment driver) to drive a large-capacity dot matrix LCD panel.
■ FEATURES
Low-power CMOS technology
Selectable output shift direction
•
•
•
•
•
•
•
•
•
•
86-bit common (row) driver
Wide range of LCD voltage .... –12 to –28V
Supply voltage ........................ 5.0V ± 10%
Package......................... DIE: Al pad (DOA)
Duty cycle ............................... 1/64 to 1/300
Display blanking available
Shift clock frequency .............. 2MHz max
Ability to adjust offset bias of the LCD source from
VDD
■ SYSTEM BLOCK DIAGRAM
D0 ~ D3
XSCL
LP, FR
LCD
CONTR
YSCL
YD
SED1600
80
SED1600
80
SED1632
SED1632
86
128 SEG × 128 COM
DUTY: 1/128
86
741
SED1632
■ BLOCK DIAGRAM
VDD
VSS
V1
V4
LCD Driver
86-bit
V0
V5
Voltage
Control
FR
Level Shifter
86-bit
DIO1
DIO2
Shift Register
86-bit
YSCL
SHL
INH
■ PIN DESCRIPTION
Pin Name
Function
LCD driving common (row) outputs.
COM0 to COM85
Each output changes at the falling edge of YSCL.
Controls all common outputs to nonselect level (V4 when FR = L, V1 when
FR = H) (low active). Contents of shift register are cleared.
INH
YSCL
Shift clock of serial data (falling edge trigger).
Serial transfer data I/O, which is controlled by SHL input. Output changes
at falling edge of YSCL.
DI01,DI02
Shift direction selection and DIO pin control.
DIO
SHL
COM Data Shift Direction
SHL
1
2
Output
Input
L
85
85
0
0
Input
Output
H
FR
AC signal of LCD driving outputs.
Logic circuit power.
VDD: 0V (GND)
VDD, VSS
VSS: –5.0 V
LCD driving power.
V5: –12 to –28V
V0, V1, V4, V5
VDD ≥ V0 ≥ V1 > V4 ≥ V5
742
SED1632
■ ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
•
(VDD = 0 V)
Parameter
Supply voltage (1)
Symbol
VSS
Ratings
–7.0 to +0.3
–30.0 to +0.3
V5 –0.3 to +0.3
VSS –0.3 to +0.3
VSS –0.3 to +0.3
20
Unit
V
Supply voltage (2)
V5
V
Supply voltage (2)
V0, V1, V4
VI
V
Input voltage (1)
V
Output voltage (1)
VO
V
Output current (1)
IO
mA
mA
°C
°C
—
mW
Output current (2)
IOSEG
Topr
20
Operating temperature
Storage temperature
Soldering temperature, time
Allowable power dissipation
–20 to +75
–65 to +150
260°C, 10s (at lead)
300
Tstg
Tsol
PD
Notes: 1. V0, V1 and V4 must always satisfy the condition VDD ≥ V0 ≥ V1 ≥ V4 ≥ V5.
2. If the power supply for the logic circuit is floated while the liquid crystal driving power supply is applied,
the LSI can be irreparably damaged. Be especially careful when the system power is being turned on
or off.
743
SED1632
DC Electrical Characteristics
•
(Unless otherwise specified, VDD = V0 = 0 V, VSS = –5.0 V ±10%, Ta = –20 to 75°C)
Parameter
Symbol
VSS
Condition
Pin
Min
Typ
Max
–4.5
Unit
V
Operating voltage (1)
VSS
–5.5
–5.0
Recommended operating voltage
Minimum operating voltage
–12.0
–8.0
V5
V5
–28.0
—
V
Operating voltage (2)
Operating voltage (4)
Operating voltage (5)
“H” input voltage
V0
V1
Recommended value
Recommended value
Recommended value
V0
V1
V4
–2.5
2/9·V5
V5
—
—
—
—
—
—
—
—
—
0
VDD
V
V
V4
7/9·V5
—
V
DIO1, DIO2,
YSCL, FR,
SHL, INH
VIH
VIL
VOH
VOL
ILI
0.2VSS
—
V
“L” input voltage
0.8VSS
—
V
“H” output voltage
“L” level output voltage
IOH = –0.3 mA
IOL = 0.3 mA
–0.4
—
V
DIO1, DIO2
VSS+0.4
2.0
V
YSCL, SHL,
INH,FR
VSS ≤ VI ≤ 0 V
VSS ≤ VI ≤ 0 V
V5 = –12.0 to –28.0 V
—
µA
µA
Input leakage current
Stand–by current
ILI/O
DIO1, DIO2
—
5.0
IDDS
VDD
—
—
25
µA
IH
DD
IL
SS
V
= V , V = V
V5=–20.0V V1,
—
—
—
—
0.40
0.50
0.60
0.70
0.80
1.00
1.20
1.40
|∆VON | V5=–14.0V V4 COM0 to
= 0.5 V V5=–20.0V V0, COM85
V5=–14.0V V5
Output resistance
RSEG
kΩ
VSS = –5.0 V, VIH = VDD,
VIL = VSS, fYSCL = 12 kHz,
Frame period = 60 Hz;
Input data: “H” every
1/200 duty No-load
Current dissipation (1)
ISSO1
VSS
—
—
7
7
15.0
15.0
µA
µA
VSS = –5.0 V, V1 = –2.0 V
V4 = –18.0 V, V5 = –20.0 V
All other conditions are
same as ISSO1
Current dissipation (2)
Input capacitance
ISSO2
V5
YSCL, SHL,
INH,FR
I
C
—
—
—
—
8.0
pF
pF
a
T = 25°C
DIO1, DIO2
CI/O
15.0
AC Characteristics
Input Timing
•
°
(VSS = –5.0 V ±10%, Ta = –20 to 75°C)
Parameter
Symbol
tCCL
tWCLH
tWCLL
tDS
Conditions
Min
500
70
Typ
—
—
—
—
—
—
—
—
Max
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
YSCL period
YSCL “H” pulse width
YSCL “L” pulse width
Data setup time
—
330
100
10
—
—
Data hold time
tDH
—
Allowable FR delay time
Input signal rise time
Input signal fall time
tDFR
tr
–500
—
500
50
50
tf
—
744
SED1632
Output Timing
°
(VSS = –5.0 V ±10%, Ta = –20 to 75°C)
Parameter
(YSCL-fall to DIO) Delay time
Symbol
Conditions
CL = 15 pF
Min
30
Typ
—
Max
300
Unit
ns
tpdDOCL
(YSCL-fall to COM output) Delay time tpdCCL
V5 = –12.0 to –28.0 V
CL = 100 pF
—
—
—
—
3.0
3.0
µs
µs
(INH to COM output) Delay time
(FR to COM output) Delay time
tpdCINH
tpdCFR
Timing Chart
Input Timing
•
°
VIH = 0.2VSS
VIL = 0.8VSS
FR
tWCLH
tDFR
tWCLL
tf
tr
YSCL
tCCL
tDS
tDH
DIO1
DIO2
Output Timing
°
FR
VIH = 0.2VSS
VIL = 0.8VSS
YSCL
tpdDOCL
VOH = 0.2VSS
VOL = 0.8VSS
DIO1
DIO2
tpdCCL
INH
tpdCFR
tpdCINH
Vn – 0.5
Vn + 0.5
COM
outputs
745
SED1632
■ EXAMPLE OF APPLICATION
(for 200 × 640 DOT MATRIX LCD)
LP
YSCL
SHL
DIO1
1
YD
DIO2 FR
VSS
SED1632
VSS
VDD
V0
V1
V2
V3
V4
V5
200 x 640 DOT MATRIX
LCD PANEL
YSCL
2
+
SHL
DIO1
DIO2 FR
R
SED1632
R
YSCL
3
SHL
11R
DIO1
DIO2 FR
SEG
0
R
R
79
79
0
79
0
SED1632
VDD
EIO2
EIO1
EIO2
EIO1
SHL
EIO2
8
EIO1
SHL
1
2
6
6
SHL
22Ω
22Ω
VSSH
*
WF
XSCL
XD0 to XD3
4
Note: * Be sure to connect a current limiter resistor. Also, connect decoupling capacitors (0.01 µF) near pins
VSS and V5 of each LSI for noise protection.
■ PAD LAYOUT
Pad
X
Y
Pad
X
Y
Pad
X
Y
No. Name (µm) (µm) No. Name (µm) (µm) No. Name (µm)
(µm)
1
2
3
4
5
6
7
8
9
COM2 –2852 –1844 35 COM36 2852 –944 69 COM69 –593 1844
COM3 –2612 –1844 36 COM37 2852 –764 70 COM70 –762 1844
COM4 –2382 –1844 37 COM38 2852 –594 71 COM71 –932 1844
COM5 –2162 –1844 38 COM39 2852 –425 72 COM72 –1112 1844
COM6 –1942 –1844 39 COM40 2852 –255 73 COM73 –1292 1844
COM7 –1742 –1844 40 COM41 2852 –86 74 COM74 –1472 1844
81
51
Y
COM8 –1542 –1844 41 COM42 2852
86
75 COM75 –1652 1844
COM9 –1342 –1844 42 COM43 2852 255 76 COM76 –1832 1844
COM10 –1142 –1844 43 COM44 2852 425 77 COM77 –2012 1844
X
(0,0)
10 COM11 –962 –1844 44 COM45 2852 594 78 COM78 –2212 1844
11 COM12 –782 –1844 45 COM46 2852 764 79 COM79 –2412 1844
12 COM13 –602 –1844 46 COM47 2852 944 80 COM80 –2632 1844
13 COM14 –422 –1844 47 COM48 2852 1124 81 COM81 –2852 1844
14 COM15 –252 –1844 48 COM49 2852 1304 82 COM82 –2852 1666
15 COM16 –82 –1844 49 COM50 2852 1484 83 COM83 –2852 1489
100
30
16 COM17 82 –1844 50
NC
2852 1664 84 COM84 –2852 1313
1
17 COM18 252 –1844 51 COM51 2852 1844 85 COM85 –2852 1137
18 COM19 422 –1844 52 COM52 2612 1844 86 DIO2 –2852 961
19 COM20 602 –1844 53 COM53 2382 1844 87
20 COM21 782 –1844 54 COM54 2162 1844 88
INH –2852 794
FR –2852 628
21 COM22 962 –1844 55 COM55 1942 1844 89 YSCL –2852 462
22 COM23 1142 –1844 56 COM56 1742 1844 90 SHL –2852 295
23 COM24 1342 –1844 57 COM57 1542 1844 91
24 COM25 1542 –1844 58 COM58 1342 1844 92
25 COM26 1742 –1844 59 COM59 1142 1844 93
26 COM27 1942 –1844 60 COM60 962 1844 94
27 COM28 2162 –1844 61 COM61 782 1844 95
28 COM29 2382 –1844 62 COM62 602 1844 96
VDD –2852 129
VSS –2852 –38
VO
V1
V4
V5
–2852 –425
–2852 –594
–2852 –764
–2852 –944
29 COM30 2612 –1844 63 COM63 422 1844 97 DIO1 –2852 –1124
30 COM31 2852 –1844 64 COM64 252 1844 98 COM0 –2852 –1304
Chip size
6.03mm × 4.01mm
0.400mm ±0.025mm
100mm × 100mm
31 COM32 2852 –1664 65 COM65 84
1844 99 COM1 –2852 –1484
32 COM33 2852 –1484 66 COM66 –84 1844 100 NC
33 COM34 2852 –1304 67 COM67 –254 1844
34 COM35 2852 –1124 68 COM68 –423 1844
–2852 –1664
Chip thickness
Pad surface area
746
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