SED1633D1A_技术文档

SED1633

LOW-POWER 100-BIT LCD COMMON DRIVER

■ DESCRIPTION

The SED1633 is a 100-output dot matrix LCD common (row) driver for driving high-capacity LCD panels at

duty cycles higher than 1/64 (up to 1/300). The LSI has a wide range of LCD driving voltages, and has its

maximum drive voltage, VO, isolated from VDD for flexibility of bias voltage generation.

The SED1633 is used in conjunction with the SED1648 (80-output segment driver) or the SED1600 (80-bit

segment driver) to drive a large-capacity dot matrix LCD panel).

■ FEATURES

Low-power CMOS technology

Non-biased display off function

•

100-bit (50 × 2 structure) common (row) driver

Duty cycle ..................................... 1/64 to 1/300

Pin selection of the output shift direction

LCD voltage ......................................–8 to –28V

Supply voltage ..................................2.7 to 5.5V

Low output impedance 500Ω typ (V1, V4 level)

700Ω typ (VO, V5 level)

Package......................................... Al pad (D1A)

Au bump (D1B)

Duty cycle ................................... 1/100 to 1/300

Ability to adjust offset bias of the LCD relative to

VDD

■ SYSTEM BLOCK DIAGRAM

D0 ~ D3

XSCL

LP, FR

LCD

CONTR

YSCL

YD

SED1648

80

SED1648

80

SED1633

100

160 x 200 dots

DUTY: 1/200

100

747

SED1633

■ BLOCK DIAGRAM

V_DD

V_SS

V1

V4

LCD Driver

100 bit

Voltage

Control

Circuit

V0

V5

FR

Level Shifter

100 bit

DI1

YSCL

D0

Shift Register

50 x 2 bits

SEL

DI3

748

SED1633

■ BLOCK DESCRIPTION

Shift Register

•

This is a bidirectional shift register for common data transmission.

Shift Direction

•

SED1633

SED1634

COM 0 → COM 99

COM 99 → COM 0

Reference

Level Shifter

•

This is a level interface circuit for shifting the signal voltage from the logic system level to the LCD driver

system level.

LCD Drivers and Voltage Controller Circuit

Outputs the LCD driver voltage.

The relationships between the content of the shift register, the alternating signal FR, and the common output

voltage are as shown in the table below:

Contents of

Shift Register

FR

COM Output Voltage

H

L

V5

V0

V1

V4

H

Select level

Non-select level

H

L

■ PIN DESCRIPTION

No. of

Pins

Pin Name

I/O

O

Function

LCD driver common (row) output

COM0-

COM99

100

Changes on the falling edge of the YSCL signal.

DI1, DI3

I

Serial data input for the 100 bit shift register. DI3 is the intermediate shift

input. (When DI3 is unused, tie it to VDD or VSS.)

2

YSCL

FR

I

Serial data shift clock input. Scanning data is shifted at the falling edge.

LCD driver output AC signal input

1

2

4

I

VDD, VSS

Power

Power source for logic. VDD: 0V (GND). VSS: –5.0V

V0, V1,

V4, V5

Power source for LCD driver. V5: –12 to –28 V

VDD ≥ V0 ≥ V1 > V4 ≥ V5

SEL

DO

I

Shift Register Operating Configuration Selection:

1

SEL

H

Shift Register Configuration

DI3

Input

H/L

50 × 2

L

100 × 1

O

Shift register data output.

1

The output changes with the falling edge of the YSCL signal.

Total: 112

749

SED1633

■ ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

•

Parameter

Power voltage (1)

Power voltage (2)

Power voltage (3)

Input voltage

Symbol

VSS

Condition

–7.0 to +0.3

–30.0 to +0.3

V5 – 0.3 to + 0.3

VSS – 0.3 to + 0.3

20

Unit

V

V5

V

V0, V1, V4

VI

V

Output voltage

VO

V

Output current (1)

Output current (2)

Operating temperature

Storage temperature

IO

mA

°C

IOCOM

Topr

Tstg

20

–40 to +85

–65 to +150

Notes: *1. The voltages are all relative to VDD = 0V.

*2. Ensure that the relationship between V0, V1, and V4 is always as follows: V^DD≥ V0 ≥ V1 ≥ V4 ≥ V5.

*3. The LSI may be permanently damaged if the logic system power is floating or V^SSis less than or equal to –2.6V when

power is applied to the LC drive circuit system. Special caution must be paid to the power sequences when turning

the power on and off.

750

SED1633

Unless otherwise specified, VDD = V0 = 0V,

VSS = –5.0V ± 10%, Ta = –40 to 85°C

DC Electrical Characteristics

•

Parameter

Symbol

V^SS

Conditions

Applicable Pins

Min

–5.5

Typ

–5.0

—

Max

–2.7

Unit

V

Power voltage (1)

VSS

V5

Recommended operating

voltage

V5

–28.0

–12.0

V

Possible operating

voltage

V5

V0

Function

V5

V0

—

–8.0

0

V

Power voltage (2)

Recommended value

–2.5

—

V

Power voltage (3)

Power voltage (4)

V1

V4

V1

V4

2/9 × V5

V5

V^DD

7/9 × V5

High-level input voltage

Low-level input voltage

High-level output voltage

V^IH

V^IL

VSS = –2.7 to –5.5V

IOH = –0.3mA

DI1, YSCL,

SEL, DI3, FR

0.2 × VSS

—

0.8 × V^SS

—

V

V^OH

DO

–0.4

I^OH= –0.2mA

(V^SS= –2.7 to –4.5V)

Low-level output voltage

Input leakage current

V^OL

IOL = 0.3mA

—

VSS + 0.4

2.0

V

I^OL= 0.2mA

(VSS = –2.7 to –4.5V)

I^LI

VSS ≤ VIN ≤ 0V

YSCL, SEL,

DI3, FR

µA

I/O leakage current

Static current

I^LO

VSS ≤ VIN ≤ 0V

DI1, DO

VDD

—

5.0

25

µA

I^DDS

V5 = –12.0 to –28.0V

VIH = VDD, VIL = VSS

When

output-

ting the

V1, V4

Output resistance

RCOM

∆|VON| V5 = –20.0V

= 0.5V V5 = –14.0V

*(V5 = –8.0V)

—

0.40

0.50

(0.60)

0.80

1.00

(1.20)

KΩ

µA

COM0

~

COM99

levels

When

*Refer-

output-

ence

V5 = –20.0V

V5 = –14.0V

*(V5 = –8.0V)

0.60

0.70

(0.90)

1.20

1.40

(1.80)

ting the

value

V0, V5

levels

Average operating

current consumption (1)

I^SS1

VSS = –5.0V, VIH = VDD,

VIL = VSS, fYSCL = 12KHz,

Frame frequency =

60KHz, Input data: 1/200,

“H” is without load on

each duty cycle

VSS

7

15

V^SS= –3.0V; other

parameters are identical

—

5

7

10

15

Average operating

current consumption (2)

I^SS2

VSS = –5.0V, V1 = –2.0V,

V4 = –18.0V,

V5

V5 = –20.0V; other

parameters are the

same as for ISS1

Input terminal capacitance

I/O terminal capacitance

CI

Ta = 25°C

YSCL, SEL,

DI3, FR

—

8

pF

C^I/O

DI1, DO

15

751

SED1633

AC Characteristics

Input Timing Characteristics

•

°

V_IH= 0.2V_SS

V_IL= 0.8V_SS

FR

t_WCLH

t_DFR

t_WCLL

t_f

t_r

YSCL

t_CCL

t_DS

t_DH

DI1

DI3

VSS = –5.0 ± 10%, Ta = –40 to 85°C

Parameter

Symbol

tr

Conditions

Min

—

Max

50

—

Unit

ns

Input signal rise time

Input signal fall time

YSCL frequency

tf

—

t^CCL

t^WCLH

t^WCLL

t^DS

500

70

YSCL high-level pulse width

YSCL low-level pulse width

Data setup time

—

330

100

10

—

Data hold time

t^DH

—

Allowable FR delay

t^DFR

–500

500

VSS = –2.7 to –4.5V, Ta = –40 to 85°C

Parameter

Input signal rise time

Input signal fall time

YSCL frequency

Symbol

tr

Conditions

Min

—

Max

50

—

Unit

ns

tf

—

t^CCL

t^WCLH

t^WCLL

t^DS

1000

160

330

200

10

YSCL high-level pulse width

YSCL low-level pulse width

Data setup time

—

Data hold time

t^DH

—

Allowable FR delay

t^DFR

–500

500

752

SED1633

Output Timing Characteristics

°

FR

V_IH= 0.2V_SS

V_IL= 0.8V_SS

YSCL

DO

t

pdDOCL

V_OH= 0.2V_SS

V_OL= 0.8V_SS

t

pdCCL

t

pdCFR

COM

outputs

Vn – 0.5

Vn + 0.5

VSS = –5.0V ± 10%, Ta = –40 to 85°C

Parameter

Symbol

t^pdDOCL

t^pdCCL

Conditions

CL = 15pF

Min

30

—

Max

300

3.0

Unit

ns

(YSCL fall → D0) delay time

(YSCL fall → COM output) delay time

(FR → COM output) delay time

V5 = –12.0 to –28.0V

CL = 100pF

µs

t^pdCFR

—

3.0

µs

VSS = –2.7 to –4.5V, Ta = –40 to 85°C

Parameter

Symbol

t^pdDOCL

t^pdCCL

Conditions

CL = 15pF

Min

60

—

Max

600

3.0

Unit

ns

(YSCL fall → D0) delay time

(YSCL fall → COM output) delay time

(FR → COM output) delay time

V5 = –12.0 to –28.0V

CL = 100pF

µs

t^pdCFR

—

3.0

µs

753

SED1633

Timing Diagram

•

1 frame

SEL = “L”

(200 lines)

For a 1/200 duty cycle

DI1

YSCL

FR

Q0

IC

Internal

shift

Q1

register

Q2

100 lines

DO

V0

V1

COM0

V4

V5

V0

V1

COM1

V4

V5

V0

V1

COM2

V4

V5

■ LCD DRIVING POWER

Method of Forming Each Voltage Level

•

The simplest way to obtain the voltage levels for driving the LCs is to use resistive voltage dividers, as shown

in the example connection figure. Because a high quality display requires precise and stable voltage levels,

the values of the dividing resistances must be set at the low end of the tolerance range of the power capacity.

When there is the need to operate with low power, the values of the voltage dividing resisters must be set

high, and the LCs must be driven by an op amp voltage follower. In consideration of the use of op amps, V0

(the highest voltage setting for driving LCs) and VDD are separated and given separate terminals.

However, when the voltage level of V0 is below VDD and the voltage difference between the two is large, the

performance of the LC output driver is reduced. Therefore ensure that the voltage gap between V0 and VDD

is in the range of 0V to 2.5V.

Connect V0 and VDD when an op amp is not used.

Cautions During Power Up and Power Down

•

Because of the high voltage of the LC driving system of this LSI, if the power to the logic system is floating

when a high voltage is applied to the LC driving system, then too much current will flow, causing damage to

the LSI.

Follow the sequences below during power up and power down:

Power up: Logic system on → LC drive system on (or simultaneous)

Power down: LC drive system off → Logic system off (or simultaneous)

In order to prevent excessive current, insert a guard resistance of at least 22 Ω in series with V5.

754

SED1633

■ EXAMPLE OF CONNECTION

Connections for a 640 × 300 dot matrix LCD

•

DI1

FR

YSCL

DI3

SEL

LP

YDU

YDL

D0

DI1

FR

V_SS

V_DD

V0

V1

V2

V3

V4

V5

640 × 300 DOT

YSCL

DI3

SEL

+

D0

(1/150 Duty)

R

DI1

FR

YSCL

DI3

SEL

R

11R

D0

SEG

0

SEG

0

SEG

0

R

79

EIO2

79

V_DD

EIO2

EIO1

SHL

EIO1

SHL

EIO2

8

EIO1

SHL

1

2

6

22Ω

V_SSH

*1

WF

XSCL

XD0 to XD3

4

Note: *1. A guard resistance must be used to prevent excessive current. Moreover, a bypass capacitor (0.01µF) should be used

near the VSS and V5 pins of each LSI to prevent noise.

755

SED1633

■ PAD LAYOUT

30

20

10

1

110

100

40

50

Y

X

(0,0)

D1633D1B

60

70

148.8µm pitch

80

90

SED1663D^1ASpecifications (The Al Pad Model)

Chip size ................. 6.03 mm × 4.01 mm

Chip thickness ........ 0.400 mm

SED1663D1B Specifications (The Au Bump Model)

Chip size ................. 6.03 mm × 4.01 mm

Chip thickness ........ 0.525 mm

Pad opening ........... 101 mm (X) × 110 mm (Y)

(where the Y direction is the

Bump size ............... 117 µm × 105 µm

+10 µm

directionofthechipcenterline)

Bump height: .......... 20 µm

(reference values) –5 µm

756

SED1633

■ PAD COORDINATES

Applicable to the SED1633D1A and SED1633D1B.

Unit: µm

Pad

No.

Pad

Name

X

Y

Pad

No.

Pad

Name

X

Y

Pad

No.

Pad

Name

X

Y

Coord.

1

COM5

COM6

2604

2455

2306

2158

2009

1860

1711

1562

1414

1265

1116

967

1834

1596

1428

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

COM43

COM44

COM45

COM46

COM47

COM48

COM49

COM50

COM51

COM52

COM53

COM54

COM55

COM56

COM57

COM58

COM59

COM60

COM61

COM62

COM63

COM64

COM65

COM66

COM67

COM68

COM69

COM70

COM71

COM72

COM73

COM74

COM75

COM76

COM77

COM78

COM79

–2842

–2604

–2455

–2306

–2158

–2009

–1860

–1711

–1562

–1414

–1265

–1116

–967

1260

1092

76

77

COM80

COM81

COM82

COM83

COM84

COM85

COM86

COM87

COM88

COM89

COM90

COM91

COM92

COM93

COM94

COM95

COM96

COM97

COM98

COM99

D0

223

372

–1834

–1596

–1428

–1260

–1092

–924

–756

–588

–420

–252

–84

2

924

78

521

3

COM7

4

COM8

756

79

670

5

COM9

588

80

818

420

81

967

6

COM10

COM11

COM12

COM13

COM14

COM15

COM16

COM17

COM18

COM19

COM20

COM21

COM22

COM23

COM24

COM25

COM26

COM27

COM28

COM29

COM30

COM31

COM32

COM33

COM34

COM35

COM36

COM37

COM38

COM39

COM40

COM41

COM42

252

82

1116

1265

1414

1562

1711

1860

2009

2158

2306

2455

2604

2842

7

8

84

83

9

–84

84

–252

85

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

–420

86

–588

87

818

–756

88

–924

89

670

–1092

–1260

–1428

–1596

–1834

90

521

372

91

223

92

93

74

94

–74

–223

–372

–521

–670

–818

–967

–1116

–1265

–1414

–1562

–1711

–1860

–2009

–2158

–2306

–2455

–2604

–2842

95

96

97

DI3

98

FR

99

YSCL

SEL

100

101

102

103

104

105

106

107

108

109

110

111

112

V^DD

V^SS

V0

84

V1

252

V4

420

–818

V5

588

–670

DI1

756

–521

COM0

COM1

COM2

COM3

COM4

924

–372

1092

1260

1428

1596

–223

–74

74

757

SED1633

THIS PAGE INTENTIONALLY BLANK

758


型号：	SED1633D1A
厂家：	SEIKO EPSON CORPORATION
描述：	Liquid Crystal Driver, 100-Segment, CMOS 驱动接口集成电路
文件：	总12页 (文件大小：45K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SED1633D1A [SEIKO]

相关型号：

SED1634D1A

SED1635D1A

SED1635D1B

SED1640D0B

SED1640T

SED1640T0A

SED1640TXX

SED1648D0A

SED1648DOA

SED1651D0A

SED1651DOA

SED1670