SGM12024A [SGMICRO]
0.4GHz to 5.0GHz, DP4T Switch with MIPI RFFE Interface;
| 型号： | SGM12024A |
| 厂家： | 
Shengbang Microelectronics Co, Ltd |
| 描述： | 0.4GHz to 5.0GHz, DP4T Switch with MIPI RFFE Interface |
| 文件： | 总14页 (文件大小：751K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SGM12024A
0.4GHz to 5.0GHz, DP4T Switch
with MIPI RFFE Interface
GENERAL DESCRIPTION
FEATURES
The SGM12024A is a dual-pole/four-throw (DP4T)
addressable switch, which supports a wide operating
frequency from 0.4GHz to 5.0GHz. The device provides
low insertion loss and high isolation performance.
These specifications make the device appropriate for
2G/3G/4G/5G applications, which need high power
processing and high linearity.
● Operating Frequency Range: 0.4GHz to 5.0GHz
● Low Insertion Loss
● Input 0.1dB Compression Point: 38dBm
● High Isolation
● MIPI RFFE V2.1 Interface Compatible
● No External DC Blocking Capacitors Required
● Available in a Green UTQFN-2×2-16AL Package
The device has the ability to integrate serial control
system compatible with RFFE standard. Internal driver
and decoder for switch control signals are offered by
the controller, which makes it flexible in RF path routing
and bands selection.
BLOCK DIAGRAM
VIO
SDA
SCL
USID
MIPI RFFE Interface
No external DC blocking capacitors required on the RF
paths as long as no external DC voltage is applied,
which can save PCB area and cost.
RFIN1
RFOUT1
RFOUT2
RFIN2
RFIN3
RFIN4
The SGM12024A is available in a Green UTQFN-2×
2-16AL package.
APPLICATIONS
Antenna Swapping
Figure 1. SGM12024A Block Diagram
5G SRS Applications
SG Micro Corp
DECEMBER 2022 – REV.A
www.sg-micro.com
0.4GHz to 5.0GHz, DP4T Switch
with MIPI RFFE Interface
SGM12024A
PACKAGE/ORDERING INFORMATION
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESCRIPTION
ORDERING
NUMBER
PACKAGE
MARKING
PACKING
OPTION
MODEL
017
XXXX
SGM12024A
UTQFN-2×2-16AL
SGM12024AYURT16G/TR
Tape and Reel, 3000
-40℃ to +85℃
MARKING INFORMATION
NOTE: XXXX = Date Code, Trace Code and Vendor Code.
Serial Number
Y Y Y
X X X X
Vendor Code
Trace Code
Date Code - Year
Green (RoHS & HSF): SG Micro Corp defines "Green" to mean Pb-Free (RoHS compatible) and free of halogen substances. If
you have additional comments or questions, please contact your SGMICRO representative directly.
OVERSTRESS CAUTION
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed in Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods
may affect reliability. Functional operation of the device at any
conditions beyond those indicated in the Recommended
Operating Conditions section is not implied.
Supply Voltage, VIO ...................................................... 2.5V
SDA, SCL and USID Control Voltage............................ 2.5V
RF Input Power, PIN ............ 38dBm (f0 = 0.4GHz to 5.0GHz)
Junction Temperature ..............................................+150℃
Storage Temperature Range ......................-55℃ to +150℃
Lead Temperature (Soldering, 10s)...........................+260℃
ESD Susceptibility
ESD SENSITIVITY CAUTION
HBM......................................................................... 1500V
CDM......................................................................... 2000V
This integrated circuit can be damaged if ESD protections are
not considered carefully. SGMICRO recommends that all
integrated circuits be handled with appropriate precautions.
Failureto observe proper handling and installation procedures
can cause damage. ESD damage can range from subtle
performancedegradation tocomplete device failure. Precision
integrated circuits may be more susceptible to damage
because even small parametric changes could cause the
device not to meet the published specifications.
RECOMMENDED OPERATING CONDITIONS
Operating Temperature Range.....................-40℃ to +85℃
Operating Frequency Range ................... 0.4GHz to 5.0GHz
Supply Voltage, VIO .......................................1.65V to 1.95V
SDA, SCL RFFE Bus High Voltage............. (0.8 × VIO) to VIO
SDA, SCL RFFE Bus Low Voltage...............0V to (0.2 × VIO)
RFFE USID Voltage, VUSID .....................................0V to VIO
DISCLAIMER
SG Micro Corp reserves the right to make any change in
circuit design, or specifications without prior notice.
SG Micro Corp
www.sg-micro.com
DECEMBER 2022
2
0.4GHz to 5.0GHz, DP4T Switch
with MIPI RFFE Interface
SGM12024A
PIN CONFIGURATION
(TOP VIEW)
RFIN2 GND RFIN3
1
2
3
4
5
16
15
14
13
12
11
10
9
RFIN4
GND
RFIN1
GND
RFOUT1
GND
GND
RFOUT2
GND
6
7
8
NC
USID
VIO
SCL
SDA
UTQFN-2×2-16AL
PIN DESCRIPTION
PIN
NAME
RFIN1
FUNCTION
1
RFIN Port 1.
2, 4, 10, 12, 15
GND
RFOUT1
USID
VIO
Ground.
3
RFOUT Port 1.
RFFE USID Select Pin.
Supply Voltage.
RFFE Clock Signal.
RFFE Data Signal.
No Connection.
RFOUT Port 2.
RFIN Port 4.
5
6
7
SCL
8
SDA
9
NC
11
RFOUT2
RFIN4
RFIN3
RFIN2
GND
13
14
16
RFIN Port 3.
RFIN Port 2.
Exposed Pad
Ground.
SG Micro Corp
www.sg-micro.com
DECEMBER 2022
3
0.4GHz to 5.0GHz, DP4T Switch
with MIPI RFFE Interface
SGM12024A
FUNCTION CHARACTERISTICS
Table 1. Register Mapping for RF Operating Modes
Register0
Output Switching Control Register
Patch
D7
x
D6
x
D5
x
D4
x
D3
x
D2
x
D1
x
D0
0
DPDT Direct DP4T Direct (Default)
DP4T Cross
x
x
x
x
x
x
x
1
REGISTER TRUTH TABLE
Table 2. Register Truth Table (Register0[0] = 0)
Register1 (DP4T Switching Control Register)
State
Mode
D7
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
D6
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
D5
0
0
0
0
0
0
1
0
0
0
1
1
0
0
1
1
1
1
1
1
1
D4
0
0
1
1
1
0
0
1
1
0
0
0
1
0
0
0
0
1
1
1
1
D3
0
0
0
0
1
0
0
0
1
0
0
0
1
1
1
1
1
0
0
0
1
D2
0
0
0
1
0
0
0
1
0
1
1
1
1
0
0
0
1
0
0
1
0
D1
0
0
1
0
0
1
1
1
1
0
0
1
0
0
0
1
0
0
1
0
0
D0
1
2
Isolation mode
Isolation mode
0
1
1
1
1
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
RFIN1 to RFOUT1; RFOUT2 Isolation
RFIN1 to RFOUT1; RFIN2 to RFOUT2
RFIN1 to RFOUT1; RFIN3 to RFOUT2
RFIN1 to RFOUT1; RFIN4 to RFOUT2
RFIN2 to RFOUT1; RFOUT2 Isolation
RFIN2 to RFOUT1; RFIN1 to RFOUT2
RFIN2 to RFOUT1; RFIN3 to RFOUT2
RFIN2 to RFOUT1; RFIN4 to RFOUT2
RFIN3 to RFOUT1; RFOUT2 Isolation
RFIN3 to RFOUT1; RFIN1 to RFOUT2
RFIN3 to RFOUT1; RFIN2 to RFOUT2
RFIN3 to RFOUT1; RFIN4 to RFOUT2
RFIN4 to RFOUT1; RFOUT2 Isolation
RFIN4 to RFOUT1; RFIN1 to RFOUT2
RFIN4 to RFOUT1; RFIN2 to RFOUT2
RFIN4 to RFOUT1; RFIN3 to RFOUT2
RFIN1 to RFOUT2; RFOUT1 Isolation
RFIN2 to RFOUT2; RFOUT1 Isolation
RFIN3 to RFOUT2; RFOUT1 Isolation
RFIN4 to RFOUT2; RFOUT1 Isolation
Single through mode
Dual through mode
Dual through mode
Dual through mode
Single through mode
Dual through mode
Dual through mode
Dual through mode
Single through mode
Dual through mode
Dual through mode
Dual through mode
Single through mode
Dual through mode
Dual through mode
Dual through mode
Single through mode
Single through mode
Single through mode
Single through mode
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
SG Micro Corp
www.sg-micro.com
DECEMBER 2022
4
0.4GHz to 5.0GHz, DP4T Switch
with MIPI RFFE Interface
SGM12024A
REGISTER TRUTH TABLE (continued)
Table 3. Register Truth Table (Register0[0] = 1)
Register1 (DP4T Switching Control Register)
State
Mode
D7
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
D6
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
D5
0
0
0
0
0
0
1
0
0
0
1
1
0
0
1
1
1
1
1
1
1
D4
0
0
1
1
1
0
0
1
1
0
0
0
1
0
0
0
0
1
1
1
1
D3
0
0
0
0
1
0
0
0
1
0
0
0
1
1
1
1
1
0
0
0
1
D2
0
0
0
1
0
0
0
1
0
1
1
1
1
0
0
0
1
0
0
1
0
D1
0
0
1
0
0
1
1
1
1
0
0
1
0
0
0
1
0
0
1
0
0
D0
0
1
1
1
1
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
0
1
2
Isolation mode
Isolation mode
RFIN1 to RFOUT2; RFOUT1 Isolation
RFIN1 to RFOUT2; RFIN2 to RFOUT1
RFIN1 to RFOUT2; RFIN3 to RFOUT1
RFIN1 to RFOUT2; RFIN4 to RFOUT1
RFIN2 to RFOUT2; RFOUT1 Isolation
RFIN2 to RFOUT2; RFIN1 to RFOUT1
RFIN2 to RFOUT2; RFIN3 to RFOUT1
RFIN2 to RFOUT2; RFIN4 to RFOUT1
RFIN3 to RFOUT2; RFOUT1 Isolation
RFIN3 to RFOUT2; RFIN1 to RFOUT1
RFIN3 to RFOUT2; RFIN2 to RFOUT1
RFIN3 to RFOUT2; RFIN4 to RFOUT1
RFIN4 to RFOUT2; RFOUT1 Isolation
RFIN4 to RFOUT2; RFIN1 to RFOUT1
RFIN4 to RFOUT2; RFIN2 to RFOUT1
RFIN4 to RFOUT2; RFIN3 to RFOUT1
RFIN1 to RFOUT1; RFOUT2 Isolation
RFIN2 to RFOUT1; RFOUT2 Isolation
RFIN3 to RFOUT1; RFOUT2 Isolation
RFIN4 to RFOUT1; RFOUT2 Isolation
Single through mode
Dual through mode
Dual through mode
Dual through mode
Single through mode
Dual through mode
Dual through mode
Dual through mode
Single through mode
Dual through mode
Dual through mode
Dual through mode
Single through mode
Dual through mode
Dual through mode
Dual through mode
Single through mode
Single through mode
Single through mode
Single through mode
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
NOTE: x = Either 0 or 1.
SG Micro Corp
www.sg-micro.com
DECEMBER 2022
5
0.4GHz to 5.0GHz, DP4T Switch
with MIPI RFFE Interface
SGM12024A
ELECTRICAL CHARACTERISTICS
(TA = +25℃, VIO = 1.65V to 1.95V, typical values are at VIO = 1.8V, VIH = 1.8V, VIL = 0V, PIN = 0dBm, VSWR = 1:1, unless
otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC Characteristics
Supply Voltage
Supply Current
Turn-On Time
VIO
IVIO
tON
1.65
1.8
1.95
203
10
V
150
μA
μs
50% VDD to 90% RF
RF Path Switching Time
(One on Path to Another)
tSW
Switching CMD 50% SCL to 90%/10% RF
2
3
μs
Wake Up Time
tWK
Switching CMD 50% SCL to 90%/10% RF
VIO off to it starts to re-power up
10
μs
μs
VIO Reset Time
RF Characteristics
tRST
10
f0 = 0.4GHz to 1.0GHz
f0 = 1.0GHz to 2.0GHz
f0 = 2.0GHz to 2.7GHz
f0 = 3.0GHz to 3.8GHz
f0 = 4.0GHz to 5.0GHz
f0 = 0.4GHz to 1.0GHz
f0 = 1.0GHz to 2.0GHz
f0 = 2.0GHz to 2.7GHz
f0 = 3.0GHz to 3.8GHz
f0 = 4.0GHz to 5.0GHz
f0 = 0.4GHz to 1.0GHz
f0 = 1.0GHz to 2.0GHz
f0 = 2.0GHz to 2.7GHz
f0 = 3.0GHz to 3.8GHz
f0 = 4.0GHz to 5.0GHz
f0 = 0.4GHz to 1.0GHz
f0 = 1.0GHz to 2.0GHz
f0 = 2.0GHz to 2.7GHz
f0 = 3.0GHz to 3.8GHz
f0 = 4.0GHz to 5.0GHz
f0 = 0.4GHz to 2.7GHz, CW
f0 = 3.0GHz to 5.0GHz, CW
0.50
0.56
0.64
0.84
0.94
49
0.85
0.95
1.20
1.45
1.65
Insertion Loss
(RFINx to RFOUTx)
IL
dB
dB
dB
31
25
22
20
16
31
25
22
20
16
44
Isolation
ISO
ISO
41
(Dual through Mode, No-Adjacent Ports)
37
31
37
33
Isolation
31
(Dual through Mode, Adjacent Ports)
26
24
26
22
Input Return Loss
(RFINx to RFOUTx)
RL
21
dB
18
10
38
Input 0.1dB Compression Point
(RFINx to RFOUTx)
P0.1dB
dBm
36
2nd Harmonic
3rd Harmonic
2nd Harmonic
3rd Harmonic
2nd Harmonic
3rd Harmonic
2nd Harmonic
3rd Harmonic
IIP2
2f0
3f0
-51
-41
-63
-59
-72
-65
-54
-63
110
70
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
dBm
f0 = 900MHz at 35dBm
f0 = 900MHz at 33dBm
f0 = 1800MHz at 25dBm
f0 = 1800MHz at 33dBm
2f0
3f0
2f0
3f0
2f0
3f0
IIP2
IIP3
f0 = 1950MHz at 20dBm, f1 = 4090MHz at -15dBm
f0 = 1950MHz at 20dBm, f1 = 1760MHz at -15dBm
IIP3
SG Micro Corp
www.sg-micro.com
DECEMBER 2022
6
0.4GHz to 5.0GHz, DP4T Switch
with MIPI RFFE Interface
SGM12024A
MIPI RFFE READ AND WRITE TIMING
SCL
SDA
SA3
SA2
SA1
SA0
0
1
0
A4
A3
A2
A1
A0
P
SSC
Example Register Write Command Frame
SCL
Signal Driven by Master
Signal Not Driven; Pull-Down Only
For Reference Only
SDA
P
D7
D6
D5
D4
D3
D2
D1
D0
P
0
Example Data Frame
Bus
Park
Figure 2. Register Write Command Timing Diagram
SCL
SDA
SA3
SA2
SA1
SA0
0
1
1
A4
A3
A2
A1
A0
P
SSC
Example Register Read Command Frame
Signal Driven by Master
SCL
SDA
Signal Not Driven; Pull-Down Only
Signal Driven by Slave
P
0
D7
D6
D5
D4
D3
D2
D1
D0
P
0
For Reference Only
Example Data Frame
Bus
Bus
Park
Park
Figure 3. Register Read Command Timing Diagram
COMMAND SEQUENCE BIT DEFINITIONS
Command Frame Bits
Bus
Extended Operation
Bus
Bus
Park
Cycle
Type SSC
Parity Bits Park
Cycle
Data Frame
Bits
Parity
Bits
Data Frame Parity
C[11:8] C[7] C[6:5]
C[4]
C[3:0]
Park
Bits
Bits
Cycle
Reg
Y
SA[3:0]
SA[3:0]
SA[3:0]
0
0
1
10
11
A[4]
A[4]
D[4]
A[3:0]
A[3:0]
D[3:0]
Y
Y
Y
-
D[7:0]
D[7:0]
-
Y
Y
-
Y
Y
-
-
-
-
-
-
-
-
-
-
Write
Reg
Read
Y
Y
Y
Reg0
Write
Y
D[6:5]
Legends:
SSC = Sequence Start Command
SA = Slave Address
A = Register Address
D = Data Bit
SG Micro Corp
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DECEMBER 2022
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0.4GHz to 5.0GHz, DP4T Switch
with MIPI RFFE Interface
SGM12024A
REGISTER MAPS
Register_0
Register Address: 0x00; R/W
Table 4. Register_0 Register Details
Bits
Bit Name
Description
Description
Description
Default
Type B/G
No
Trig
D[7:0]
MODE_CTRL0
See Table 2 and Table 3 section.
00000000 R/W
0, 1, 2
Register_1
Register Address: 0x01; R/W
Table 5. Register_1 Register Details
Bits
Bit Name
Default
Type B/G
No
Trig
D[7:0]
MODE_CTRL1
See Table 2 and Table 3 section.
00000000 R/W
0, 1, 2
RFFE_STATUS
Register Address: 0x1A; R/W
Table 6. RFFE_STATUS Register Details
Bits
Bit Name
Default
Type B/G
Trig
0: Normal
1: Software reset
During software reset, this register and all configurable registers are
set to their default values except for reserved registers.
D[7]
SOFTWARE_RESET
0
R/W
No
No
COMMAND_FRAME_
PARITY_ERR
D[6]
Command frame parity error.
0
0
0
R/W
R/W
R/W
No
No
No
No
No
No
D[5] COMMAND_LENGTH_ERR Command length error.
ADDRESS_FRAME_
D[4]
Address frame parity error.
PARITY_ERR
DATA_FRAME_
PARITY_ERR
D[3]
Data frame parity error.
0
R/W
No
No
D[2]
D[1]
RD_IVD_ADD
WR_IVD_ADD
Read command to an invalid address.
Write command to an invalid address.
0
0
R/W
R/W
No
No
No
No
Read command with a BROADCAST_ID or GSID.
When this register is read, it will reset.
D[0]
BID_GID_ERR
0
R/W
No
No
GROUP_SID
Register Address: 0x1B; R and R/W
Table 7. GROUP_SID Register Details
Bits
Bit Name
Reserved
GSID
Description
Default
0000
Type B/G
Trig
No
D[7:4]
D[3:0]
Reserved.
R
No
No
Group slave ID.
0000
R/W
No
SG Micro Corp
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DECEMBER 2022
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0.4GHz to 5.0GHz, DP4T Switch
with MIPI RFFE Interface
SGM12024A
REGISTER MAPS (continued)
PM_TRIG
Register Address: 0x1C; R/W and W
Table 8. PM_TRIG Register Details
Bits
Bit Name
Description
Default
Type B/G
Trig
0: Normal
1: Low power
0: Active - Normal
D[7]
PWR_MODE_1
0
R/W
R/W
Yes
Yes
No
D[6]
D[5]
PWR_MODE_0
0
0
No
No
1: Startup - All registers are reset to the default
If any one of the three TRIGGER_MASK_x
0: TRIGGER_2 enabled
1: TRIGGER_2 disabled
TRIGGER_MASK_2
R/W
R/W
R/W
No
No
No
is set to logic '1', the corresponding trigger
is disabled, in that case data written to a
register associated with the trigger goes
0: TRIGGER_1 enabled directly to the destination register.
1: TRIGGER_1 disabled Otherwise, if the TRIGGER_MASK_x is
set to logic '0', incoming data is written to
D[4]
D[3]
TRIGGER_MASK_1
TRIGGER_MASK_0
0
0
No
No
the shadow register, and the destination
register is unchanged until its corresponding
trigger is asserted.
0: TRIGGER_0 enabled
1: TRIGGER_0 disabled
0: Keep its associated destination registers unchanged
D[2]
D[1]
D[0]
TRIGGER_2
TRIGGER_1
TRIGGER_0
1: Load its associated destination registers with the data in the parallel
shadow register, provided TRIGGER_MASK_2 is set to logic '0'
0: Keep its associated destination registers unchanged
1: Load its associated destination registers with the data in the parallel
shadow register, provided TRIGGER_MASK_1 is set to logic '0'
0: Keep its associated destination registers unchanged
0
0
0
W
W
W
Yes
Yes
Yes
No
No
No
1: Load its associated destination registers with the data in the parallel
shadow register, provided TRIGGER_MASK_0 is set to logic '0'
PRODUCT_ID
Register Address: 0x1D; R
Table 9. PRODUCT_ID Register Details
Bits
Bit Name
Description
Default
Type B/G
No
Trig
D[7:0]
PRODUCT_ID
Product number.
00000101
R
No
MANUFACTURER_ID
Register Address: 0x1E; R
Table 10. MANUFACTURER_ID Register Details
Bits
Bit Name
Description
Lower eight bits of Manufacturer ID.
Default
Type B/G
No
Trig
D[7:0] MANUFACTURER_ID[7:0] Read-only. Note that during USID programming, the write command
sequence is executed on the register, but the value does not change.
01001010
R
No
MAN_USID
Register Address: 0x1F; R and R/W
Table 11. MAN_USID Register Details
Bits
Bit Name
Description
Upper four bits of Manufacturer ID.
Default
Type B/G
Trig
D[7:4] MANUFACTURER_ID[11:8] Read-only. Note that during USID programming, the write command
sequence is executed on the register, but the value does not change.
0000
R
No
No
No
USID pin connected to GND.
1010
1011
D[3:0]
USID
R/W
No
USID pin connected to VIO.
SG Micro Corp
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DECEMBER 2022
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0.4GHz to 5.0GHz, DP4T Switch
with MIPI RFFE Interface
SGM12024A
POWER ON AND OFF SEQUENCE
Once the VIO voltage drops to 0V, the VIO waits at
least 10μs before repowering (see Figure 4).
Do not apply RF power during switching. To ensure this,
the RF power needs to be removed before the register
write operation that changes the switching mode is
completed (see Figure 6).
In order to ensure the correct data transmission,
SDA/SCL must be sent after VIO has been applied at
least 120ns. There must be at least 15μs to apply RF
power after VIO has been applied. Wait a minimum of
typically 10μs after RFFE bus is idle to apply an RF
signal (see Figure 5).
When the low power mode is used, a delay time of 10μs
is required to exit the low power mode (see Figure 7).
> 15μs
VIO
...
...
SCL
> 10μs
> 120ns
VIO
SDA
> 10μs
RF Power
VIO Off
VIO Power Up
VIO On
Start
Stop
RF On
Figure 4. Digital Supply Detail
Figure 5. Digital Signal/RF Power-On Detail
VIO
SCL
> 5μs
...
...
SCL
SDA
...
> 120ns
...
SDA
RF Power
> 10μs
> 15μs
RF Power
Start
Stop
RF On
Initiate Low
Power Mode Power Mode
Exit Low
RF On
VIO On
Figure 6. Switch Event Timing
Figure 7. Low Power Mode Exit Timing
SG Micro Corp
www.sg-micro.com
DECEMBER 2022
10
0.4GHz to 5.0GHz, DP4T Switch
with MIPI RFFE Interface
SGM12024A
TYPICAL APPLICATION CIRCUIT
USID
Supply Voltage
VIO
RFFE USID Select Pin
RFFE Clock Signal
C1
100nF
RFFE Data Signal
SDA
SCL
C2
DNI
C3
DNI
SGM12024A
L1*
0.7nH
RFIN Port 1
RFIN Port 2
RFIN Port 3
RFIN Port 4
RFIN1
RFIN2
RFIN3
RFIN4
RFOUT1
RFOUT Port 1
RFOUT Port 2
C4*
0.5pF
RFOUT2
GND
NOTE: * Matching for optimized RF performance, it may be changed according to different applications.
Figure 8. SGM12024A Typical Application Circuit
EVALUATION BOARD LAYOUT
Figure 9. SGM12024A Evaluation Board Layout
SG Micro Corp
www.sg-micro.com
DECEMBER 2022
11
PACKAGE INFORMATION
PACKAGE OUTLINE DIMENSIONS
UTQFN-2×2-16AL
D
e
N16
N1
PIN 1#
E
E1
D1
L
k
L1
L1
L
BOTTOM VIEW
TOP VIEW
0.425
A
1.00
1.00
1.50 1.90
A1
A2
0.20
0.20
SIDE VIEW
RECOMMENDED LAND PATTERN (Unit: mm)
Dimensions In Millimeters
Symbol
MIN
0.500
0.000
MOD
0.550
-
MAX
0.600
0.050
A
A1
A2
D
0.127 REF
2.000
1.000
2.000
1.000
0.425 BSC
-
1.900
0.900
1.900
0.900
2.100
1.100
2.100
1.100
D1
E
E1
e
k
0.150
0.150
0.000
-
L
0.200
0.050
0.250
0.100
L1
NOTE: This drawing is subject to change without notice.
SG Micro Corp
TX00238.000
www.sg-micro.com
PACKAGE INFORMATION
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
P2
P0
W
Q2
Q4
Q2
Q4
Q2
Q4
Q1
Q3
Q1
Q3
Q1
Q3
B0
Reel Diameter
P1
A0
K0
Reel Width (W1)
DIRECTION OF FEED
NOTE: The picture is only for reference. Please make the object as the standard.
KEY PARAMETER LIST OF TAPE AND REEL
Reel Width
Reel
Diameter
A0
B0
K0
P0
P1
P2
W
Pin1
Package Type
W1
(mm)
(mm) (mm) (mm) (mm) (mm) (mm) (mm) Quadrant
UTQFN-2×2-16AL
7″
9.5
2.25
2.25
0.75
4.0
4.0
2.0
8.0
Q1
SG Micro Corp
TX10000.000
www.sg-micro.com
PACKAGE INFORMATION
CARTON BOX DIMENSIONS
NOTE: The picture is only for reference. Please make the object as the standard.
KEY PARAMETER LIST OF CARTON BOX
Length
(mm)
Width
(mm)
Height
(mm)
Reel Type
Pizza/Carton
7″ (Option)
7″
368
442
227
410
224
224
8
18
SG Micro Corp
www.sg-micro.com
TX20000.000
相关型号：
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