SI5322-C-GM [SILICON]
Support Circuit, 1-Func, 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD, QFN-36;
| 型号： | SI5322-C-GM |
| 厂家： | 
SILICON |
| 描述： | Support Circuit, 1-Func, 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD, QFN-36 时钟 |
| 文件： | 总16页 (文件大小：213K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si5322
PRELIMINARY DATA SHEET
PIN-PROGRAMMABLE PRECISION CLOCK MULTIPLIER
Description
Features
The Si5322 is a low jitter, precision clock multiplier for
high-speed communication systems, including SONET
OC-48/OC-192, Ethernet, and Fibre Channel. The
Si5322 accepts dual clock inputs ranging from 19.44 to
707 MHz and generates two equal frequency-
multiplied clock outputs ranging from 19.44 to
1050 MHz. The input clock frequency and clock
multiplication ratio are selectable from a table of
popular SONET, Ethernet, and Fibre Channel rates.
The Si5322 is based on Silicon Laboratories' 3rd-
Selectable output frequencies ranging from 19.44 to
1050 MHz
Low jitter clock outputs with jitter generation as low
as 0.6 ps
(50 kHz–80 MHz)
RMS
Integrated loop filter with selectable loop bandwidth
(30 kHz to 1.3 MHz)
Dual clock inputs with manual or automatically
controlled hitless switching
Dual clock outputs with selectable signal format:
®
LVPECL, LVDS, CML, CMOS
generation DSPLL technology, which provides any-
Support for ITU G.709 FEC ratios (255/238,
rate frequency synthesis in a highly integrated PLL
solution that eliminates the need for external VCXO
and loop filter components. The DSPLL loop bandwidth
is digitally programmable, providing jitter performance
optimization at the application level. Operating from a
single 1.8, 2.5, or 3.3 V supply, the Si5322 is ideal for
providing clock multiplication in high performance
timing applications.
255/237, 255/236)
LOS alarm output
Pin-controlled output phase adjust
Pin-programmable settings
On-chip voltage regulator for 1.8, 2.5, or 3.3 V
±10% operation
Small size: 6 x 6 mm 36-lead QFN
Pb-free, RoHS compliant
Applications
SONET/SDH OC-48/OC-192 line cards
GbE/10GbE, 1/2/4/8/10GFC line cards
ITU G.709 line cards
Optical modules
Test and measurement
CKOUT1
CKIN1
®
Signal Format
CKOUT2
DSPLL
CKIN2
Disable/BYPASS
Control
Signal Detect
Loss of Signal
VDD (1.8, 2.5, or 3.3 V)
GND
Frequency Select
Bandwidth Select
Manual/Auto Switch
Clock Select
Preliminary Rev. 0.47 7/07
Copyright © 2007 by Silicon Laboratories
Si5322
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si5322
Table 1. Performance Specifications
(VDD = 1.8, 2.5, or 3.3 V ±10%, TA = –40 to 85 ºC)
Parameter
Temperature Range
Supply Voltage
Symbol
Test Condition
Min
–40
Typ
25
Max
85
Unit
ºC
V
T
A
V
2.97
2.25
1.62
3.3
2.5
1.8
3.63
2.75
1.98
DD
V
V
Supply Current
I
f
= 622.08 MHz
DD
OUT
Both CKOUTs enabled
LVPECL format output
—
—
—
251
217
204
279
243
234
mA
mA
mA
CKOUT2 disabled
f
= 19.44 MHz
OUT
Both CKOUTs enabled
CMOS format output
CKOUT2 disabled
—
—
194
220
mA
mA
Tristate/Sleep Mode
TBD
TBD
Input Clock Frequency
(CKIN1, CKIN2)
CK
Input frequency and clock multi-
plication ratio pin-selectable
from table of values using
FRQSEL and FRQTBL settings.
Consult Silicon Laboratories
configuration software
DSPLLsim or Any-Rate Preci-
sion Clock Family Reference
Manual at www.silabs.com/clock
for table selections.
F
19.44
—
707.35
MHz
Output Clock Fre-
quency (CKOUT1,
CKOUT2)
CK
OF
19.44
—
1049.76
MHz
Input Clocks (CKIN1, CKIN2)
Differential Voltage
Swing
CKN
DPP
0.25
—
1.9
V
PP
Common Mode
Voltage
CKN
1.8 V ±10%
2.5 V ±10%
3.3 V ±10%
20–80%
0.9
1.0
1.1
—
—
—
—
—
—
—
1.4
1.7
1.95
11
V
V
VCM
V
Rise/Fall Time
Duty Cycle
CKN
ns
%
ns
TRF
CKN
40
60
DC
Whichever is less
50
—
Output Clocks (CKOUT1, CKOUT2)
Common Mode
V
LVPECL
100 Ω load
line-to-line
V
– 1.42
—
—
V – 1.25
DD
V
V
OCM
DD
Differential Output
Swing
V
1.1
1.9
OD
Single Ended Output
Swing
V
0.5
—
0.93
V
SE
Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision
Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing.
2
Preliminary Rev. 0.47
Si5322
Table 1. Performance Specifications (Continued)
(VDD = 1.8, 2.5, or 3.3 V ±10%, TA = –40 to 85 ºC)
Parameter
Rise/Fall Time
Duty Cycle
Symbol
CKO
Test Condition
Min
—
Typ
230
—
Max
Unit
ps
20–80%
350
55
TRF
CKO
45
%
DC
PLL Performance
Jitter Generation
J
fo = 622.08 MHz,
LVPECL output format
50 kHz – 80 MHz
GEN
—
0.6
TBD
ps rms
12 kHz – 20 MHz
—
—
0.6
TBD
0.1
ps rms
dB
Jitter Transfer
Phase Noise
J
0.05
PK
CKO
f
= 622.08 MHz
PN
OUT
—
TBD
TBD
dBc/Hz
100 Hz offset
1 kHz offset
—
—
—
—
—
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc
10 kHz offset
100 kHz offset
1 MHz offset
Subharmonic Noise
Spurious Noise
SP
SP
Phase Noise @ 100 kHz Offset
SUBH
Max spur @ n x F3
(n > 1, n x F3 < 100 MHz)
SPUR
—
TBD
TBD
dBc
Package
Thermal Resistance
Junction to Ambient
θ
JA
Still Air
—
38
—
ºC/W
Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision
Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing.
Table 2. Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
V
DC Supply Voltage
V
–0.5 to 3.6
DD
DIG
JCT
STG
LVCMOS Input Voltage
V
–0.3 to (V + 0.3)
V
DD
Operating Junction Temperature
Storage Temperature Range
ESD HBM Tolerance (100 pF, 1.5 kΩ)
ESD MM Tolerance
T
–55 to 150
–55 to 150
2
ºC
ºC
kV
V
T
200
Latch-Up Tolerance
JESD78 Compliant
Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods of time may affect device reliability.
Preliminary Rev. 0.47
3
Si5322
C4
C3
1 µF
System
Power
Supply
0.1 µF
Ferrite
Bead
C2
C1
0.1 µF
0.1 µF
VDD = 3.3 V
130 Ω
82 Ω
130 Ω
82 Ω
0.1 µF
100 Ω
0.1 µF
CKOUT1+
CKOUT1–
CKIN1+
+
–
CKIN1–
Clock
Outputs
0.1 µF
100 Ω
0.1 µF
CKOUT2+
CKOUT2–
+
–
Input
Clock
VDD = 3.3 V
Sources1
130 Ω
82 Ω
130 Ω
82 Ω
CKIN2+
CKIN2–
C1B
C2B
CKIN_1 Loss of Signal
CKIN_2 Loss of Signal
Si5322
Manual/Automatic Clock
Selection (L)
AUTOSEL2
CS_CA3
Input Clock Select/
Active Clock Indicator
FRQTBL2
Frequency Table Select
FRQSEL[3:0]2
BWSEL[1:0]2
Frequency Select
Bandwidth Select
SFOUT[1:0]2
DBL2_BY2
RST
Signal Format Select
Clock Output 2 Disable/
Bypass Mode Control
Reset
Notes: 1. Assumes differential LVEPECL termination (3.3 V) on clock inputs.
2. Denotes tri-level input pins with states designated as L (ground), M (VDD/2), and H (VDD).
3. Assumes manual input clock selection.
Figure 1. Si5322 Typical Application Circuit
4
Preliminary Rev. 0.47
Si5322
In the case when the input clocks enter alarm
conditions, the PLL will freeze the DCO output
1. Functional Description
The Si5322 is a low jitter, precision clock multiplier for frequency near its last value to maintain operation with
high-speed communication systems, including SONET an internal state close to the last valid operating state.
OC-48/OC-192, Ethernet, and Fibre Channel. The
The Si5322 has two differential clock outputs. The
Si5322 accepts dual clock inputs ranging from 19.44 to
electrical format of the clock outputs is programmable to
707 MHz and generates two frequency-multiplied clock
support LVPECL, LVDS, CML, or CMOS loads. If not
outputs ranging from 19.44 to 1050 MHz. The two input
required, the second clock output can be powered down
clocks are at the same frequency and the two output
to minimize power consumption. The phase difference
clocks are at the same frequency. The input clock
between the selected input clock and the output clocks
frequency and clock multiplication ratio are selectable
is adjustable in 200 ps increments for system skew
from a table of popular SONET, Ethernet, and Fibre
control. For system-level debugging, a bypass mode is
Channel rates. In addition to providing clock
available which drives the output clock directly from the
multiplication in SONET and datacom applications, the
input clock, bypassing the internal DSPLL. The device is
Si5322
supports
SONET-to-datacom
frequency
powered by a single 1.8, 2.5, or 3.3 V supply.
translations. Silicon Laboratories offers a PC-based
software utility, DSPLLsim, that can be used to look up
valid Si5322 frequency translations. This utility can be
1.1. Further Documentation
Consult the Silicon Laboratories Any-Rate Precision
Clock Family Reference Manual (FRM) for more
detailed information about the Si5322. The FRM can be
downloaded from www.silabs.com/timing.
downloaded
from
www.silabs.com/timing.
This
information is also available in the Any-Rate Precision
Clock Family Reference Manual, also available from
www.silabs.com/timing.
Silicon Laboratories has developed
a PC-based
The Si5322 is recommended for applications in which
the input clock is relatively low jitter and only clock
software utility called DSPLLsim to simplify device
configuration, including frequency planning and loop
bandwidth selection. This utility can be downloaded
from www.silabs.com/timing.
multiplication is required. The Si5322 is based on
®
Silicon
Laboratories'
3rd-generation
DSPLL
technology, which provides any-rate frequency
synthesis in a highly integrated PLL solution that
eliminates the need for external VCXO and loop filter
components. The Si5322 PLL loop bandwidth is
selectable via the BWSEL[1:0] pins and supports a
range from 30 kHz to 1.5 MHz. The DSPLLsim software
utility can be used to calculate valid loop bandwidth
settings for a given input clock frequency/clock
multiplication ratio. The Si5322 monitors all input clocks
for loss of signal and provides a LOS alarm when it
detects a missing clock.
Preliminary Rev. 0.47
5
Si5322
2. Pin Descriptions: Si5322
36 35 34 33 32 31 30 29 28
RST
FRQTBL
C1B
1
2
3
4
5
6
7
8
9
27 FRQSEL3
26
FRQSEL2
25 FRQSEL1
C2B
24
23
FRQSEL0
BWSEL1
GND
Pad
VDD
GND
22 BWSEL0
NC
21
20
19
CS_CA
NC
GND
NC
AUTOSEL
10 11 12 13 14 15 16 17 18
Pin assignments are preliminary and subject to change.
Table 3. Si5322 Pin Descriptions
Pin #
Pin Name
I/O
Signal Level
Description
External Reset.
Active low input that performs external hardware reset of
device. Resets all internal logic to a known state. Clock out-
puts are tristated during reset. After rising edge of RST sig-
nal, the Si5322 will perform an internal self-calibration.
This pin has a weak pull-up.
1
RST
I
LVCMOS
3-Level
Frequency Table Select.
Selects SONET/SDH, datacom, or SONET/SDH to datacom
frequency table.
L = SONET/SDH.
2
FRQTBL
I
M = Datacom.
H = SONET/SDH to Datacom.
This pin has a weak pull-down.
CKIN1 Loss of Signal.
Active high loss-of-signal indicator for CKIN1. Once trig-
gered, the alarm will remain active until CKIN1 is validated.
0 = CKIN1 present.
3
4
C1B
C2B
O
O
LVCMOS
LVCMOS
1 = LOS on CKIN1.
CKIN2 Loss of Signal.
Active high loss-of-signal indicator for CKIN2. Once trig-
gered, the alarm will remain active until CKIN2 is validated.
0 = CKIN2 present.
1 = LOS on CKIN2.
6
Preliminary Rev. 0.47
Si5322
Table 3. Si5322 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
Supply.
The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass
capacitors should be associated with the following V pins:
DD
5, 10, 11,
15, 32
V
V
Supply
5
0.1 µF
0.1 µF
0.1 µF
DD
DD
10
32
A 1.0 µF should be placed as close to device as is practical.
Ground.
6, 8, 31
GND
GND
Supply
3-Level
Must be connected to system ground. Minimize the ground
path impedance for optimal performance of this device.
Manual/Automatic Clock Selection.
Three level input that selects the method of input clock
selection to be used.
L = Manual.
9
AUTOSEL
I
M = Automatic non-revertive.
H = Automatic revertive.
Clock Input 2.
Differential input clock. This input can also be driven with a
single-ended signal. Input frequency selected from a table
of values. The same frequency must be applied to CKIN1
and CKIN2.
12
13
CKIN2+
CKIN2–
I
I
I
Multi
3-Level
Multi
Output 2 Disable/Bypass Mode Control.
Controls enable of CKOUT2 divider/output buffer path and
PLL bypass mode.
L = CKOUT2 enabled.
M = CKOUT2 disabled.
H = Bypass mode with CKOUT2 enabled.
14
DBL2_BY
Clock Input 1.
Differential input clock. This input can also be driven with a
single-ended signal. Input frequency selected from a table
of values. The same frequency must be applied to CKIN1
and CKIN2.
16
17
CKIN1+
CKIN1–
Preliminary Rev. 0.47
7
Si5322
Table 3. Si5322 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
Input Clock Select/Active Clock Indicator.
If manual clock selection mode is chosen (AUTOSEL = L),
this pin functions as the manual input clock selector. This
input is internally deglitched to prevent inadvertent clock
switching during changes in the CS input state.
0 = Select CKIN1.
1 = Select CKIN2.
21
CS_CA
I/O
LVCMOS
If automatic clock selection mode is chosen (AUTOSEL = M
or H), this pin indicates which of the two input clocks is cur-
rently the active clock. If alarms exist on both CKIN1 and
CKIN2, indicating that the digital hold state has been
entered, CA will indicate the last active clock that was used
before entering the hold state.
0 = CKIN1 active input clock.
1 = CKIN2 active input clock.
Bandwidth Select.
Three level inputs that select the DSPLL closed loop band-
width. Detailed operations and timing characteristics for
these pins may be found in the Any-Rate Precision Clock
Family Reference Manual.
23
22
BWSEL1
BWSEL0
I
I
3-Level
3-Level
Multiplier Select.
27
26
25
24
FRQSEL3
FRQSEL2
FRQSEL1
FRQSEL0
Three level inputs that select the input clock and clock multi-
plication ratio, depending on the FRQTBL setting. Consult
the Any-Rate Precision Clock Family Reference Manual or
DSPLLsim configuration software for settings, both avail-
able for download at www.silabs.com/timing.
Signal Format Select.
Three level inputs that select the output signal format (com-
mon mode voltage and differential swing) for both CKOUT1
and CKOUT2. Valid settings include LVPECL, LVDS, and
CML. Also includes selections for CMOS mode, tristate
mode, and tristate/sleep mode.
SFOUT[1:0]
Signal Format
Reserved
HH
HM
HL
33
30
SFOUT0
SFOUT1
Reserved
CML
I
3-Level
MH
MM
ML
LH
LVPECL
Reserved
LVDS
CMOS
LM
LL
Tristate/Sleep
Reserved
8
Preliminary Rev. 0.47
Si5322
Table 3. Si5322 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
Clock Output 2.
Differential output clock with a frequency selected from a
table of values. Output signal format is selected by SFOUT
pins. Output is differential for LVPECL, LVDS, and CML
compatible modes. For CMOS format, both output pins drive
identical single-ended clock outputs.
34
35
CKOUT2–
CKOUT2+
O
Multi
Clock Output 1.
Differential output clock with a frequency selected from a
table of values. Output signal format is selected by SFOUT
pins. Output is differential for LVPECL, LVDS, and CML
compatible modes. For CMOS format, both output pins drive
identical single-ended clock outputs.
29
28
CKOUT1–
CKOUT1+
O
Multi
No Connect.
7, 18, 19,
20, 36
NC
—
—
These pins must be left unconnected for normal operation.
Ground Pad.
GND PAD
GND
GND
Supply
The ground pad must provide a low thermal and electrical
impedance to a ground plane.
Preliminary Rev. 0.47
9
Si5322
3. Ordering Guide
Ordering Part Number
Si5322-B-GM
Package
Temperature Range
36-Lead 6 x 6 mm QFN
–40 to 85 °C
10
Preliminary Rev. 0.47
Si5322
4. Package Outline: 36-Lead QFN
Figure 2 illustrates the package details for the Si5322. Table 4 lists the values for the dimensions shown in the
illustration.
Figure 2. 36-Pin Quad Flat No-lead (QFN)
Table 4. Package Dimensions
Symbol
Millimeters
Symbol
Millimeters
Min
0.80
0.00
0.18
Nom
0.85
Max
0.90
0.05
0.30
Min
0.50
—
Nom
0.60
—
Max
0.75
12º
A
A1
b
L
0.01
θ
0.23
aaa
bbb
ccc
ddd
eee
—
—
0.10
0.10
0.05
0.10
0.05
D
6.00 BSC
4.10
—
—
D2
e
3.95
4.25
—
—
0.50 BSC
6.00 BSC
4.10
—
—
E
—
—
E2
3.95
4.25
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220, variation VJJD.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body
Components.
Preliminary Rev. 0.47
11
Si5322
5. Recommended PCB Layout
Figure 3. PCB Land Pattern Diagram
12
Preliminary Rev. 0.47
Si5322
Table 5. PCB Land Pattern Dimensions
Dimension
MIN
MAX
e
E
0.50 BSC.
5.42 REF.
5.42 REF.
D
E2
D2
GE
GD
X
4.00
4.00
4.53
4.53
—
4.20
4.20
—
—
0.28
Y
0.89 REF.
ZE
ZD
—
—
6.31
6.31
Notes (General):
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Notes (Solder Mask Design):
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Notes (Stencil Design):
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4. A 4 x 4 array of 0.80 mm square openings on 1.05 mm pitch should be used for the
center ground pad.
Notes (Card Assembly):
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification
for Small Body Components.
Preliminary Rev. 0.47
13
Si5322
DOCUMENT CHANGE LIST
Revision 0.44 to Revision 0.45
Condensed format.
Revision 0.45 to Revision 0.46
Removed references to latency control, INC, and
DEC in figures and text.
Changed LVTTL to LVCMOS in Table 2, “Absolute
Maximum Ratings,” on page 3.
Added Figure 1, “Typical Phase Noise Plot,” on page
4.
Updated “2. Pin Descriptions: Si5322”.
Added “5. Recommended PCB Layout”.
Revision 0.46 to Revision 0.47
Removed Figure 1. “Typical Phase Noise Plot.”
Changed pins 11 and 15 from NC to VDD in “2. Pin
Descriptions: Si5322”.
14
Preliminary Rev. 0.47
Si5322
NOTES:
Preliminary Rev. 0.47
15
Si5322
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: Clockinfo@silabs.com
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-
quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-
sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-
plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
16
Preliminary Rev. 0.47
相关型号：
©2020 ICPDF网 联系我们和版权申明