CXD2434ATQ [SONY]
Timing Generator for Progressive Scan CCD Image Sensor; 时序发生器逐行扫描CCD图像传感器
| 型号： | CXD2434ATQ |
| 厂家： | 
SONY CORPORATION |
| 描述： | Timing Generator for Progressive Scan CCD Image Sensor |
| 文件： | 总26页 (文件大小：522K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXD2434ATQ
Timing Generator for Progressive Scan CCD Image Sensor
Description
48 pin TQFP (Plastic)
The CXD2434ATQ is an IC developed to generate
the timing pulses required by the Progressive Scan
CCD image sensors as well as signal processing
circuits. The CXD2434ATQ adds EFS operation
when using the high-speed electronic shutter and
other changes to the CXD2434TQ specifications.
Features
• External trigger function
• Electronic shutter function
• Supports non-interlaced operation
• 30 frames/s
Absolute Maximum Ratings (Ta=25 °C)
• Supply voltage
• Input voltage
VDD
VSS –0.5 to +7.0
V
VI VSS –0.5 to VDD +0.5 V
VO VSS –0.5 to VDD +0.5 V
• Output voltage
• Operating temperature
• Built-in driver for the horizontal (H) clock
• Base oscillation 1560 fH (24.5454 MHz)
Topr
–20 to +75
°C
°C
• Storage temperature
Applications
Tstg
–55 to +150
Progressive Scan CCD cameras
Recommended Operating Conditions
Structure
• Supply voltage
• Operating temperature
Topr
VDD
4.75 to 5.25
V
Silicon gate CMOS IC
–20 to +75
°C
Applicable CCD Image Sensors
ICX084AK, ICX084AL
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
—1—
E97841-TE
CXD2434ATQ
Block Diagram
36 35 34 33 32 31
47 46
42 29 26 25
10
13
14
21
22
23
18
17
16
19
39
38
40
3
4
5
7
8
9
RG
H1
PS
STRB
DCLK
DATA
SMD1
SMD2
TG
REGISTER
H2
XSHP
XSHD
XRS
XV1
XV2
XV3
XSG
CLD
CL
PULSE GENERATOR
DECODE
COUNTER
GATE
11
28
48
41
XSUB
TEST1
TEST2
1/2
CKO
RESET
43 44 45
12 15 20 24 27 30 37
1
2
6
Pin Configuration (Top View)
36 35 34 33 32 31 30 29 28 27 26 25
VSS 37
CL 38
24 VSS
23 XRS
22 XSHD
21 XSHP
20 VDD
19 XSG
18 XV1
17 XV2
16 XV3
15 VSS
14 H2
CLD 39
CKO 40
RESET 41
STDBY 42
TRIG 43
ESG 44
EFS 45
HD 46
CXD2434ATQ
VD 47
TEST2 48
13 H1
10 11 12
1
2
3
4
5
6
7
8
9
—2—
CXD2434ATQ
Pin Description
Pin No. Symbol
I/O
Description
1
2
OSCO
OSCI
O
I
Inverter output for oscillation.
Inverter input for oscillation.
Switching for electronic shutter speed input method. (With pull-up resistor)
Low: Serial input, High: Parallel input
Shutter speed setting. (With pull-up resistor)
Shutter speed setting. (With pull-up resistor)
GND
3
PS
I
4
STRB
DCLK
VSS
I
5
I
6
—
I
7
DATA
SMD1
SMD2
RG
Shutter speed setting. (With pull-up resistor)
Shutter mode setting. (With pull-up resistor)
Shutter mode setting. (With pull-up resistor)
Reset gate pulse output.
8
I
9
I
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
O
O
—
O
O
—
O
O
O
O
—
O
O
O
—
XSUB
VDD
CCD discharge pulse output.
Power supply.
H1
Clock output for horizontal CCD drive.
Clock output for horizontal CCD drive.
GND
H2
VSS
XV3
Clock output for vertical CCD drive.
Clock output for vertical CCD drive.
Clock output for vertical CCD drive.
Sensor charge readout pulse output.
Power supply.
XV2
XV1
XSG
VDD
XSHP
XSHD
XRS
VSS
Sample-and-hold pulse output.
Sample-and-hold pulse output.
Sample-and-hold pulse output.
GND
Switching for external trigger discharge operation. (With pull-up resistor)
Low: No high-speed discharge, High: High-speed discharge
Switching for readout timing. (With pull-up resistor)
Low: ESG input valid, High: ESG input invalid
GND
25
26
FSE
I
I
SMDE
27
28
VSS
—
I
TEST1
Test. (With pull-down resistor)
WEN mode setting. (With pull-down resistor)
Low: Effective line, High: XSG synchronization
Power supply.
29
WM
I
30
31
32
33
34
35
36
37
38
39
VDD
XCPDM
XCPOB
PBLK
ID
—
O
O
O
O
O
O
—
O
O
Clamp pulse output.
Clamp pulse output.
Blanking cleaning pulse output.
Line identification output.
WEN
BUSY
VSS
Write enable output.
Trigger mode flag output.
GND
CL
780 fH clock output.
CLD
AD conversion pulse output.
—3—
CXD2434ATQ
Pin No. Symbol
I/O
Description
40
41
CKO
O
I
1560 fH clock output.
RESET
RESET. (With pull-up resistor) Low : Reset, High : Normal
Standby. (With pull-up resistor)
42
STDBY
I
Low: Internal clock supply stopped, High: Normal
External trigger input. (With pull-up resistor)
External readout input. (With pull-up resistor)
Vertical CCD discharge input. (With pull-up resistor)
Horizontal sync signal input.
43
44
45
46
47
48
TRIG
ESG
EFS
HD
I
I
I
I
I
I
VD
Vertical sync signal input.
TEST2
Test. (With pull-up resistor)
Electrical Characteristics
1. DC Characteristics
VDD=4.75 V to 5.25 V Topr= –20 to +75 °C
Item
Supply voltage
Symbol
VDD
Conditions
Min.
4.75
Typ.
5.0
Max.
5.25
Unit
V
Input voltage 1
VIH1
VIL1
0.7 VDD
V
(Input pins other than those listed below)
Input voltage 2
0.3 VDD
0.3 VDD
0.4
V
VIH2
VIL2
0.7 VDD
VDD–0.4
VDD–0.4
VDD–0.4
VDD–0.4
VDD/2
V
(Pin 2)
V
Output voltage 1
VOH1
VOL1
VOH2
VOL2
VOH3
VOL3
VOH4
VOL4
VOH5
VOL5
RFB
IOH=–2.5 mA
IOL=4.5 mA
V
(Output pins other than those listed below)
Output voltage 2
V
IOH=–5.0 mA
IOL=9.0 mA
V
(Pins 21, 22, 23, 38, 39 and 40)
Output voltage 3
0.4
V
IOH=–7.5 mA
IOL=13.5 mA
IOH=–14.0 mA
IOL=24.0 mA
V
(Pin 10)
0.4
V
Output voltage 4
V
(Pins 13 and 14)
0.4
V
Output voltage 5
V
(Pin 1)
VDD/2
V
Feedback resistor
Pull-up resistor
VIN=VSS or VDD
VIL=0 V
1 M
50 k
50 k
40
Ω
Ω
Ω
mA
RPU
100 k
100 k
Pull-down resistor
Current consumption
RPD
VIH=VDD
IDD
VDD=5 V
—4—
CXD2434ATQ
2. AC Characteristics
1) Waveform characteristics of H1, H2 and RG
0.9VDD
H1
0.1VDD
tRH1
tWH1
tFH1
0.9VDD
H2
0.1VDD
tFH2
tWH2
tRH2
0.9VDD
RG
0.1VDD
tRRG
tWRG
tFRG
VDD=5.0 V, Topr=25 °C, load capacitance of H1 and H2=100 pF, load capacitance of RG=10 pF
Symbol
Definition
Min.
Typ.
6
Max.
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRH1
tFH1
H1 rise time
H1 fall time
5
15
tWH1
tRH2
tFH2
H1 high level time
H2 rise time
25
35
6
15
15
H2 fall time
5
tWH2
tRRG
tFRG
tWRG
H2 low level time
RG rise time
25
35
2
5
5
RG fall time
2
RG high level time
10
15
20
—5—
CXD2434ATQ
2) Phase characteristics of H1, H2, RG, XSHP, XSHD, XRS, CL, CLD and CKO
tH1
0.5VDD
0.5VDD
0.5VDD
H1
H2
0.5VDD
0.5VDD
tPD3
tPD1
tPD2
0.5VDD
0.5VDD
RG
tPD4
tPD5
tW1
0.5VDD
0.5VDD
XSHP
XSHD
tW2
tPD6
0.5VDD
0.5VDD
tPD7
0.5VDD
0.5VDD
0.5VDD
XRS
CLD
CL
tPD8
tW3
tPD9
0.5VDD
tPD10
tW4
0.5VDD
0.5VDD
tW5
tW5
0.5VDD
0.5VDD
CLO
0.5VDD
0.5VDD
tPD11
tPD11
VDD=5.0 V, Topr=25 °C, load capacitance of CL and CKO=30 pF, load capacitance of CLD, XSHP, XSHD, XRS and RG=10 pF
Symbol
tH1
Definition
Min.
Typ.
82
0
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
H1 cycle
tPD1
tPD2
tPD3
tPD4
tPD5
tPD6
tPD7
tPD8
tPD9
tPD10
tPD11
tW1
H2 rising delay, activated by the falling edge of H1
H2 falling delay, activated by the rising edge of H1
H1 rising delay, activated by the rising edge of RG
XSHP falling delay, activated by the falling edge of RG
H1 falling delay, activated by the rising edge of XSHP
H1 rising delay, activated by the rising edge of XSHD
CLD falling delay, activated by the falling edge of XSHD
CLD falling delay, activated by the rising edge of XRS
XRS falling delay, activated by the falling edge of CLD
CL falling delay, activated by the rising edge of H1
H1 rising (falling) delay, activated by the rising edge of CKO
XSHP pulse width
–5
–5
–5
–2
–7
–5
–5
17
0
5
5
0
0
5
4
10
7
2
2
7
2
7
22
8
27
15
5
–5
–5
13
15
17
38
17
0
2
7
18
20
22
41
20
23
25
27
45
24
tW2
XSHD pulse width
tW3
CLD pulse width
tW4
CL pulse width
tW5
CKO pulse width
—6—
CXD2434ATQ
3) Phase conditions of HD, VD, TRIG, EFS and ESG
0.5VDD
CL
tSETUP
tHOLD
HD, VD, TRIG
EFS, ESG
0.5VDD
0.5VDD
VDD=5.0 V, Topr=25 °C, load capacitance of CL=30 pF
Symbol
tSETUP
tHOLD
Definition
Min.
Typ.
Max.
Unit
ns
HD, VD, TRIG, EFS and ESG setup time, activated by CL
HD, VD, TRIG, EFS and ESG hold time, activated by CL
20
5
ns
4) Phase characteristics of XV1, XV2, XV3, XSG, PBLK, XCPDM, XCPOB, BUSY, WEN and ID
0.5VDD
0.5VDD
CL
tPDCL1
XV1, XV2, XV3
BUSY, WEN, ID
0.5VDD
tPDCL2
0.5VDD
tPDCL3
XSG, PBLK,
XCPDM, XCPOB
0.5VDD
VDD=5.0 V, Topr=25 °C, load capacitance of CL=30 pF,
load capacitance of XV1, XV2, XV3, XSG, PBLK, XCPDM, XCPOB, BUSY, WEN and ID=10 pF
Symbol
Definition
Min.
30
Typ.
Max.
65
Unit
ns
tPDCL1 XV1, XV2 and XV3 delay, activated by the falling edge of CL
tPDCL2 BUSY, WEN and ID delay, activated by the rising edge of CL
40
60
ns
XSG, PBLK, XCPDM and XCPOB delay, activated by the
tPDCL3
40
55
ns
rising edge of CL
—7—
CXD2434ATQ
Description of Functions
1. Progressive Scan CCD drive pulse generation
• Combining this IC with a crystal oscillator generates a fundamental frequency of 24.5454 MHz.
• CCD drive pulse generation is synchronized with the HD and VD inputs.
Set fCL to 780 fHD and fHD to 525 fVD.
• The various operations are performed by the TRIG, EFS and ESG inputs. (See the following items.)
<Detection timing for VD, TRIG, EFS and ESG>
CL
1
35
HD
H1
T1
Detection timing for VD,
TRIG, EFS and ESG
After HD input is detected, the status of VD, TRIG, ESG and EFS is detected during T1.
Do not change the status of VD, TRIG, ESG and EFS during T1.
When input is from a non-synchronized system, the low level period for each pulse should be set to 63.5 µs
or longer to prevent misoperation.
2. Reset
The internal register values are undetermined immediately after power-on, so perform one of the following
reset operations.
1. Reset by the RESET pin
Reset is performed by setting the RESET pin low for a period of 80 ns or more. Reset can also be
performed by setting the RESET pin low during power-on and then switching the RESET pin from low to
high when VDD rises to 4.75 V or higher. Note that when reset is performed by the RESET pin, the
electronic shutter settings made by serial input are also reset.
2. Reset by turning off the electronic shutter
Reset is performed by setting the shutter mode to electronic shutter off and inputting VD. Note that in
this case the TRIG, ESG and EFS pins should all be set high.
—8—
CXD2434ATQ
3. Electronic shutter
<Shutter modes>
The electronic shutter has the following four shutter modes.
• Electronic shutter off :
Exposure time is 1/30 s.
• High-speed electronic shutter : Exposure time is shorter than 1/30 s.
• Low-speed electronic shutter: Exposure time is longer than 1/30 s.
• Flickerless :
Exposure time is 1/50 s. This is a special feature of the high-speed
electronic shutter, and reduces flicker from fluorescent lights, etc. in areas
with 50 Hz power supply
<Shutter mode and speed setting methods>
PS=Low : Serial input; set by the STRB, DCLK and DATA pins. The SMD1 and SMD2 pins are not used.
PS=High : Parallel input; set by the STRB, DCLK, DATA, SMD1 and SMD2 pins.
3-1. [Serial input]
Serial input is set by the STRB, DCLK and DATA pins. The electronic shutter mode and the meanings of the
numbers indicated by D0 to 9 vary according to the SMD1 and SMD2 setting of the internal register.
STRB
DCLK
DATA
SMD2 SMD1 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SMD1 SMD2
Mode
D0 to 9
—
H
L
H
H
L
Electronic shutter off (1/30 s accumulation)
High-speed electronic shutter
Number of exposed lines (Note 1)
Number of exposed frames (Note 2)
H
Low-speed electronic shutter
Note 1) Relationship between the number of exposed lines and the exposure time
The relationship between the number of exposed lines and the exposure time is as follows.
(Exposure time)=(Number of exposed lines) × (One horizontal scan period) + (Accumulation time for
the readout lines)
In this formula, one horizontal scan period equals the HD falling interval, and the accumulation time for
the readout lines is the time from the rising edge of XSUB to the rising edge of XSG (456 bits). Also,
(Number of exposed lines) should be set to greater than 1 but less than 524.
Note 2) The number of exposed frames should be set to greater than 1 but less than 1023. However, when
the number of exposed frames is 1 and SMDE is set to high, external trigger mode does not function.
Timing Chart (Serial input)
STRB
tWD
tSDS
tHDD
tWS
DCLK
DATA
tSDD
—9—
CXD2434ATQ
AC characteristics for serial input
Symbol
Definition
Min.
Max.
—
tSDD
tHDD
tSDS
tWS
DATA setup time, activated by the rising edge of DCLK
DATA hold time, activated by the rising edge of DCLK
DCLK setup time, activated by the falling edge of STRB
STRB pulse width
10 ns
10 ns
10 ns
82 ns
82 ns
—
—
—
tWD
DCLK pulse width
—
3-2. [Parallel input]
PS
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
SMD1
H
L
SMD2
H
L
STRB
X
DCLK
X
DATA
X
Exposure time
1/30 s
Mode
Electronic shutter off
Flickerless
X
X
X
1/50 s
L
H
H
H
H
H
H
H
H
L
H
L
H
H
L
H
H
H
H
L
1/60 s
L
1/125 s
1/250 s
1/500 s
1/1000 s
1/2000 s
1/4000 s
1/10000 s
2 FRM
L
H
L
L
L
High-speed shutter
L
H
L
H
H
L
L
L
L
H
L
L
L
L
L
H
H
H
H
H
H
H
H
H
L
H
H
L
H
H
H
H
L
L
3 FRM
L
H
L
4 FRM
L
L
5 FRM
Low-speed shutter
L
H
L
H
H
L
6 FRM
L
L
7 FRM
L
H
L
L
8 FRM
L
L
L
9 FRM
—10—
CXD2434ATQ
4. External trigger mode
External trigger mode starts exposure in sync with the external trigger input. No special pins are required to
set this mode.
The IC prepares to shift to external trigger mode with the falling edge of the TRIG pin (Note). The timing to
shift to external trigger mode varies according to the mode setting. (See the table.) The BUSY pin
maintains high status during external trigger mode. Whether or not to discharge the vertical CCD charge is
set by FSE.
Note) See the detection timing for VD, TRIG, EFS and ESG.
Mode settings during external trigger (Note 1)
PS
L
SMD1 SMD2
Description of operation
The IC is shifted to external trigger mode by HD, exposure is finished after the set
time, and XSG is output. (Note 2) (Note 3)
L
L
X
H
H
The IC is shifted to external trigger mode by HD, exposure is finished 1/50 s later,
and XSG is output.
H
L
L
X
X
H
H
L
Do not set for external trigger.
H
Trigger input is not accepted.
Note 1) The SMD1 and SMD2 setting method varies according to the PS status. See “3. Electronic shutter”.
PS=Low : Set by serial input.
PS=High : Set by the SMD1 and SMD2 pins.
Note 2) The exposure time setting method is the same as the exposure time setting for the electronic shutter.
Note 3) When FSE=high, set the number of exposed lines from 1 to 522.
<FSE and discharge operation>
During external trigger mode, the previously exposed signal charge sometimes remains in the vertical CCD
when exposure finishes. In this case, the image shot with external trigger mode is output overlapped with
the previously shot image. Setting FSE to high performs discharge operation for signal charges remaining
in the vertical CCD after trigger input. Discharge operation is not performed when FSE is low. This setting
is only valid when SMD1 is low.
<Finishing the exposure period with ESG>
During external trigger mode, exposure can be finished in sync with the falling edge of ESG (Note). If
SMDE is set to low, the XSG pulse is output regardless of the electronic shutter setting, when the falling
edge of ESG is detected. ESG should be fixed to high status at all times other than during external trigger
mode. Do not change SMDE while BUSY is high.
Note) See the detection timing for VD, TRIG, EFS and ESG.
<Signal after external trigger mode>
After high-speed external trigger mode is finished, the exposure time differs from that performed by the
electronic shutter setting. This is because the start and finish of external trigger mode are not synchronized
to VD input.
—11—
CXD2434ATQ
5. Discharge of the vertical CCD
During EFS is low, discharge of the vertical CCD is performed. During FSE is high in the external trigger
mode, the vertical control line by line is possible. That is different from discharge operation. The falling in
the effective interval of EFS is detected, discharge is not performed even if the low status is held until the
next effective period. For frames using EFS, set electronic shutter off or high-speed electronic shutter.
When EFS is used, WEN (WM=low) may not indicate the proper status.
<Discharge start>
Vertical CCD discharge is started in sync with HD input after the falling edge of EFS (Note). Approximately
3420 ns (81.4 ns × 42 clock pulses) are required to transfer one line vertically.
Note) See the detection timing for VD, TRIG, EFS and ESG.
<Discharge finish>
Since the operation uses 42 clock pulses as one unit, when the rising edge of EFS is detected in interval
[n], discharge operation stops from interval [n+1]. The period from the rising edge of EFS to the falling
edge of VD must be longer than 2HD.
Timing Chart 1
n–1
n
n+1
EFS
XV1
XV3
Timing Chart 2
n
n+1
CL
XV3
<Maximum number of dischargeable lines>
The number of lines transferred by discharge transfer and normal transfer during the following period
should not exceed 4096 lines.
Period : The period from when the XSG pin becomes low until XSG becomes low again or the TRIG pin
becomes low.
6. Internal logic stop (standby mode)
When the STDBY pin is set to low, clock supply is stopped to a part of the internal logic. However, output
from the oscillation cell (OSCI and OSCO pins) as well as the CL and CKO pins does not stop. The status
of each output pin when STDBY is low is shown below.
High :
Low :
XSUB, XSG
RG, H1, H2, XV1, XV2, XV3, XSHP, XSHD, XRS, XCPOB, XCPDM, PBLK, ID, WEN,
BUSY, CLD
Not stopped : OSCO, CL, CKO
—12—
CXD2434ATQ
7. Mode settings
7-1. VD input-related
BUSY
H
SMD1
L
SMD2
H
SMDE
X
EFS
X
VD input
Invalid
Readout operation or the number of
accumulated frames is counted.
Readout operation is performed.
Invalid
H
L
H
L
L
X
X
X
H
X
Note 1) When PS is high, SMD1 and SMD2 indicate the status of the SMD1 and SMD2 pins, respectively.
When PS is low, these are the corresponding internal register values. See “3. Electronic shutter”.
Note 2) Operation when PS=high, SMD1=low and SMD2=low conforms to that when SMD1=low and
SMD2=high.
7-2. TRIG, ESG and EFS input-related
BUSY
SMDE
X
TRIG
ESG
EFS
Discharge period
(Note 1)
Prohibited
Invalid
H
H
L
Prohibited
Exposure period
Readout operation (Note 4)
Signal output period
Prohibited
IC shifted to
Discharge operation
(Note 6) (Note 7)
Before TRIG input
external trigger
mode (Note 3)
X
L
Prohibited (Note 5)
After TRIG input
(Note 2) (Note 3)
Prohibited
Prohibited
Note 1) Only when FSE is high.
Note 2) Valid only during low-speed shutter.
Note 3) See “4. External trigger mode”.
Note 4) ESG input is valid only one time after TRIG input. Do not input ESG two times or more.
Note 5) Fix ESG to high status when BUSY is low.
Note 6) When EFS is low, readout is not activated by VD input. See “7-1. VD input-related”.
Note 7) Use in electronic shutter off state.
Note 8) In case any two pins or more among TRIG, ESG, and EFS are falled at the same time, the operation is
not guaranteed.
7-3. WEN mode switching by WM
WM
L
Description of WEN operation
Lines for which the signal from the CCD is valid output high; all other lines output low.
Output is synchronized with XSG.
H
—13—
CXD2434ATQ
—14—
CXD2434ATQ
0 1 5
8 0 5
4 1
1
—15—
CXD2434ATQ
7 0 1
5 3
1
0 8 7
—16—
CXD2434ATQ
7 0 1
5 3
1
0 8 7
—17—
CXD2434ATQ
8 0 5
4 1
1
7 2
1
—18—
CXD2434ATQ
5 3
1
0 8 7
—19—
CXD2434ATQ
—20—
CXD2434ATQ
8 0 5
4 1
1
—21—
CXD2434ATQ
8 0 5
4 1
1
7 2
1
—22—
CXD2434ATQ
4 6 2
6 5 2
3 1
6
1
7 2
1
—23—
CXD2434ATQ
7 0 1
5 3
1
0 8 7
—24—
CXD2434ATQ
—25—
CXD2434ATQ
Package Outline Unit : mm
48PIN TQFP (PLASTIC)
1.27 MAX
1.0 ± 0.1
9.0 ± 0.4
7.0 ± 0.2
25
36
0.1
37
24
A
13
48
1
12
0.2 ± 0.1
0.5
0.125 ± 0.05
0.08
M
0.1 ± 0.1
+ 7°
3° – 3°
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
EPOXY RESIN
SOLDER PLATING
42 ALLOY
SONY CODE
EIAJ CODE
TQFP-48P-L071
TQFP048-P-0707-AN
JEDEC CODE
PACKAGE WEIGHT
0.2g
—26—
相关型号：
©2020 ICPDF网 联系我们和版权申明