CXG1061TN [SONY]
Low Noise Down Conversion Mixer for PHS; 低噪声下变频混频器，用于小灵通
| 型号： | CXG1061TN |
| 厂家： | 
SONY CORPORATION |
| 描述： | Low Noise Down Conversion Mixer for PHS |
| 文件： | 总5页 (文件大小：91K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXG1061TN
Low Noise Down Conversion Mixer for PHS
Description
10 pin TSSOP (Plastic)
The CXG1061TN is a low noise down conversion
mixer MMIC for PHS. This IC is designed using the
Sony’s GaAs J-FET process.
Features
• High gain
Gc=22 dB (Typ.)
• Low distortion
Input IP3=–13 dBm (Typ.)
• Low LO input power operation
PLO=–15 dBm
• High image suppression ratio
IMR=27 dBc (Typ.)
Absolute Maximum Ratings (Ta=25 °C)
• Supply voltage
• Input power
VDD
PIN
4.5
+5
V
dBm
°C
• LO input matching circuit
• Operating temperature Topr
• Storage temperature
–35 to +85
• Single 3 V power supply operation
• 10-pin TSSOP package
Tstg –65 to +150 °C
Recommended Operating condition
Function
• Supply voltage
VDD
2.7 to 3.3
V
Frequency conversion
Applications
Japan digital cordless telephones (PHS)
Structure
GaAs J-FET MMIC
Block Diagram
Pin Configuration
RF AMP
IF AMP
6
5
4
3
2
1
RFIN
7
5
1
IFOUT
VDD (RF AMP)
IFOUT/VDD (MIX, IF AMP)
7
8
RFIN
CAP
CAP
GND
CAP
LOIN
MIX
GND
9
LOIN
10
VDD (LO AMP)
LO AMP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
—1—
E98335A8Y
CXG1061TN
Electrical Characteristics
VDD=3.0 V, fRF=1.9 GHz, fLO=1.66 GHz, PLO=–15 dBm, RF input and IF output 50 Ω matching; unless otherwise specified
(Ta=25 °C)
Item
Current consumption
Conversion gain
Noise figure
Symbol
IDD
Min.
—
Typ.
7
Max.
9
Unit
mA
dB
Measurement condition
When no signal
Gc
19.5
—
22
24.5
4.5
When a small signal
When a small signal
PRF=–40 dBm
NF
3.3
dB
offset=600 kHz
Input IP3
IIP3
–15.5
–13
—
dBm
Conversion by the IM3 suppression
ratio for two-wave input
When PRF=–40 dBm input
When PRF=–40 dBm input
Image suppression ratio
1/2 IF suppression ratio
LO to RF leak level
LO input VSWR
IMR
1/2IFR
PLK
22
35
—
—
27
40
–46
2
—
—
dBc
dBc
dBm
—
–41
3.5
VSWRLO
(Note) The values shown above are the specified values on the Sony’s recommended evaluation board.
Recommended Evaluation Board
VDD (RF AMP)
C8
C5
C7
VDD (MIX, IF AMP)
L2
L1
C4
IFOUT
VDD
IFOUT
CAP
GND
CAP
LOIN
6
7
8
5
4
3
50Ω
L3
C9
RFIN
C6
C3
RFIN
CAP
GND
VDD
50Ω
C10
L4
9
2
1
LOIN
50Ω
10
VDD (LO AMP)
C2
C1
L1
82 nH
3.9 nH
12 nH
10 nH
18 pF
C4
5 pF
L2
L3
L4
C1
C2
C3
C5
C6
1000 pF
0.1 µF
13 pF
C7
C8
1000 pF
3 pF
1000 pF
18 pF
C9
C10
1000 pF
—2—
CXG1061TN
Example of Representative Characteristics (Ta=25 °C)
POUT, IM3 vs. PIN
20
0
POUT
–20
–40
–60
–80
IM3
VDD=3.0V
fRF1=1.90GHz
fRF2=1.9006GHz
fLO=1.66GHz
PLO= –15dBm
–50
–40
–30
–20
–10
PIN-RF input power [dBm]
Gc, NF vs. PLO
IIP3, PLK vs. PLO
IIP3
25
23
21
19
17
15
7
6
5
4
3
2
–10
–12
–14
–16
–18
–20
–30
–35
–40
–45
–50
Gc
PLK
NF
VDD=3.0V
fRF=1.90GHz
fLO=1.66GHz
VDD=3.0V
fRF=1.90GHz
fLO=1.66GHz
–55
0
–25
–20
–15
–10
–5
0
–25
–20
–15
–10
–5
PLO-LO input power [dBm]
PLO-LO input power [dBm]
—3—
CXG1061TN
Recommended Evaluation Board
25mm
Front
SONY
CXG1061TN EVB
IFOUT
C8
C7
L2
C4
C5
L1
C6
C3
L4
C9
L3
RFIN
C10
LOIN
C1
C2
VDD (RF AMP) VDD (LO AMP) GND VDD (MIX, IF AMP)
Back
VDD (MIX, IF AMP) GND VDD (LO AMP) VDD (RF AMP)
Glass fabric-base 4-layer epoxy board (thickness: 0.3 mm × 2)
GND for the 2nd and 3rd layers
—4—
CXG1061TN
Package Outline Unit : mm
10PIN TSSOP(PLASTIC)
1.2MAX
2.8 ± 0.1
0.1
10
6
+ 0.15
0.1 – 0.05
5
1
0.5
0.25
0° to 10°
+ 0.08
0.22 – 0.07
0.1
M
A
(0.2)
+ 0.08
0.22 – 0.07
A
DETAIL
NOTE: Dimension “ ” does not include mold protrusion.
PACKAGE STRUCTURE
EPOXY RESIN
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
SOLDER PLATING
SONY CODE
EIAJ CODE
TSSOP-10P-L01
COPPER ALLOY
0.02g
JEDEC CODE
PACKAGE MASS
—5—
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