CXL1501M [SONY]
CMOS-CCD Signal Processor; CMOS ， CCD信号处理器
| 型号： | CXL1501M |
| 厂家： | 
SONY CORPORATION |
| 描述： | CMOS-CCD Signal Processor |
| 文件： | 总12页 (文件大小：183K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXL1501M
CMOS-CCD Signal Processor
For the availability of this product, please contact the sales office.
Description
30 pin SOP (Plastic)
The CXL1501M is a CMOS-CCD signal processor
designed for 8-mm VCR video signal processing. In
combination with the 8-mm VCR video Y/C signal
processing IC CXA1200Q, this IC configures a comb
filter for Y/C separation in recording an image and
elimination of crosstalk in playing back.
Features
• Single power supply 5V
Absolute Maximum Ratings (Ta = 25°C)
• Low power consumption 225mW (Typ.)
• Supply voltage
VDD
6
V
• Built-in peripheral circuits
• Operating temperature
• Storage temperature
Topr –10 to +60 °C
Tstg –55 to +150 °C
• Completely adjustment free
• Built-in quadruple progression PLL circuit
• For NTSC signals
• Allowable power dissipation PD
500
mW
Recommended Operating Conditions (Ta = 25°C)
Supply voltage VDD 5 ± 5%
Functions
V
• 1H comb filter output
• Dropout compensation (D.O.C) output
• Delay time matching through output (THR)
• PLL circuit (quadruple progression)
• Clock driver
Recommended Clock Conditions (Ta = 25°C)
• Input clock amplitude
VCLK 0.4 to 1.0 Vp-p
(0.5Vp-p Typ.)
• Clock frequency
fCLK
3.579545 MHz
• Autobias circuit
• Input clock waveform
sine wave
• Sync tip clamp circuit
• Sample and hold circuit
Input Signal Amplitude
VSIG
571 mVp-p
(Max.)
Structure
CMOS-CCD
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E71050-PS
CXL1501M
Y - Y D
S S V
S S V
V G G B
T H
S S V
D D V
Y D
A D J Y
V G G A
N C
A B P
V C O O U T
N C
N C
S S V
D D V
S S V
C L K
N C
D D V
C C D 3
P C O U T
V C O I N
A B N
A D J C
C C D 2
S S V
C C D 1
S S V
– 2 –
CXL1501M
Pin Description
Symbol
Pin No.
1
Description
I/O
—
I
Impedance (Ω)
VSS
GND
CCD2
ADJC
ABN
CCD3
NC
2
Signal input 2 (Reverse phase signal)
Forward phase CCD bias DC output
Reverse phase autobias DC output
Signal input 3 (Forward phase signal)
> 100k (at no clamp)
600 to 2k
3
O
O
I
4
2k to 20k
5
> 100k (at no clamp)
6
—
—
—
—
O
O
O
—
O
O
—
—
O
—
O
—
O
—
—
I
VDD
7
5V power supply (For clock driver)
GND
VSS
8
NC
9
ABP
VGGA
YD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Forward phase autobias DC output
Gate bias (A) DC output
D.O.C signal output (Reverse phase signal)
GND
2k to 20k
2k to 10k
40 to 500
VSS
VGGB
Y-YD
VSS
2k to 10k
40 to 500
Gate bias (B) DC output
Comb filter signal output
GND
VSS
GND
TH
40 to 500
600 to 2k
THR signal output (Forward phase signal)
5V power supply (For analog)
Reverse phase CCD bias DC output
VDD
ADJY
NC
VCO OUT
NC
VCO output
VSS
GND
CLK
VDD
4k to 40k
Clock input
5V power supply (For digital)
Phase comparator output
VCO input
—
O
I
PC OUT
VCO IN
VSS
2k to 5k
> 100k
GND
—
I
CCD1
> 100k (at no clamp)
Signal input 1 (Reverse phase signal)
– 3 –
CXL1501M
– 4 –
CXL1501M
– 5 –
CXL1501M
Notes)
1
Adjust the output amplitude of the inversion and the non-inversion amplifiers in the signal input block to an
equal value, as well as the phase difference to a precise 180°.
Also set the clock and input signal frequency accurately.
2
VIT, VIC and VID are defined as follows:
VIT, VIC and VID are input signal clamp levels. They clamps the Video signal sync tip level. They are the
pin voltages at no-input signal for pins 30, 2 and 5, respectively.
VIT
Input (CCD1)
30
L1501
2
5
Input (CCD2)
VIC
VID
Input (CCD3)
Testing of VIT, VIC and VID is executed with a voltmeter under the following SW conditions:
SW conditions
Test
point
Item
1
2
b
b
b
3
b
b
b
4
b
b
b
5
a
a
a
6
a
a
a
7
a
a
a
8
9
10 11
VIT
VIC
VID
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
V1
V2
V3
As VIT, VIC and VID differ with each IC, they are to be tested respectively.
This is the IC supply current value during clock and signal input.
3
4
GLT, GLC and GLD are output gains of TH, Y-YD, and YD pins when a 500mVp-p, 196.678kHz sine wave
is simultaneously fed to CCD1, CCD2, and CCD3 pins respectively.
(Example of calculation)
TH pin output voltage [mVp-p]
GLT = 20 log
[dB]
500 [mVp-p]
– 6 –
CXL1501M
5
GHT, GHC, and GHD are output gains of TH, Y-YD and YD pins when a 150mVp-p, 3.579545MHz sine
wave is simultaneously fed to CCD1, CCD2, and CCD3 pins respectively.
Bias at input (VBIAS1, VBIAS2 and VBIAS3) is tested respectively at VIT – 0.25V, VIC – 0.25V and VID + 0.25V.
(Example of calculation)
TH pin output voltage [mVp-p]
GHT = 20 log
[dB]
150 [mVp-p]
6
Indicates the dissipation at 3.579545MHz in relation to 196.678kHz. From the output voltage at TH, Y-YD
and YD pins when a 150mVp-p, 196.678kHz sine wave is simultaneously fed to CCD1, CCD2 and CCD3
pins, and from the output voltage at TH, Y-YD and YD pins when a 150mVp-p, 3.579545MHz sine wave is
simultaneously fed to same, calculation is made according to the following formula. The input block bias for
VBIAS1, VBIAS2 and VBIAS3 is tested at VIT – 0.25V, VIC – 0.25V and VID + 0.25V, respectively.
(Example of calculation)
TH pin output voltage (3.579545MHz) [mVp-p]
fT = 20 log
[dB]
TH pin output voltage (196.678kHz) [mVp-p]
7
The differential gain (DG) and the differential phase (DP), when the 5-staircase wave in the following figure
is fed, are tested with a vector scope:
143mV
357mV
500mV
143mV
1H 63.56µs
CCD3 pin input waveform (the input waveform of CCD1 and CCD2 pins is the inverted waveform of the
figure above.)
8
The internal clock component to the output signal during no-signal input and the leakage of that high
harmonic component are tested. The input block bias is tested at VITV, VICV, and VID + 0.5V.
Test value [mVp-p]
– 7 –
CXL1501M
9
The noise level of output signal at no-input signal is tested with a video noise meter in the Sub Carrier Trap
mode at BPF 100kHz to 4MHz. Vn [Vrms]
The signal component is determined either by testing the output voltage (the same test system as that of
noise level) at input of 357mVp-p, 196.678kHz, or by performing calculation from the values of GLT, GLC,
and GLD in accordance with the following formula. Vs [Vp-p]
(Example of Vs calculation)
GLT
20
VS-T = 0.357 × 10
(VS-T: TH output voltage)
(Example of S/N ratio calculation)
Vn-T (noise component) [Vrms]
SNT = 20 log
[dB]
VS-T (signal component) [Vp-p]
10 C-CD is calculated in accordance with the following formula from the Y-YD pin output voltage when a
200mVp-p, 3.579545MHz sine wave is simultaneously fed to CCD1, CCD2 and CCD3 pins and from the Y-
CD pin output voltage when a 200mVp-p, 3.587412MHz sine wave is simultaneously fed to same. The
input block bias is set to VIT – 0.3V, VIC – 0.3V and VID + 0.3V, respectively.
Y-YD pin output voltage (3.587412MHz) [mVp-p]
C-CD = 20 log
[dB]
Y-YD pin output voltage (3.579545MHz) [mVp-p]
CLOCK
fsc (3.579545MHz) sine wave
0.4Vp-p to 1.0Vp-p
(0.5Vp-p Typ.)
– 8 –
CXL1501M
Electrical Characteristics Test Circuit
9V
1.2k
CLK
fSC (3.579545MHz) 0.5Vp-p
–1
a
b
SW2
sine wave
0.1µ
1µ
SW5
2.2µ
29
4.7µ
82k
196.678kHz
500mVp-p
sine wave
a
b
b
a
1M
120
1µ
20
3.3µ 0.01µ
26 25
3.3µ 0.01µ
19 18
196.678kHz
150mVp-p
sine wave
30
28
27
24
23
22
21
17
16
a
Oscilloscope
3.579545MHz
150mVp-p
sine wave
SW8
a
SW9
c
d
e
f
b
Spectrum
analyzer
b
–1
a
b
1
×3
SW3
c
Vector
scope
3.579545MHz
200mVp-p
sine wave
LPF
c
SW6
b
1µ
1M
×3
SW1
9V
d
Noise
meter
BPF
a
1.2k
1.2k
3.587412MHz
200mVp-p
sine wave
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
2
1µ
1µ
1µ
1µ
1µ
5-staircase
wave
9V
0.01µ 3.3µ
–1
a
b
SW4
1µ
SW7
1M
51k
1
2
)
)
5V
LPF frequency response
BPF frequency response
b
a
[dB]
[dB]
51k
51k
0
–3
0
–3
V1
V2
V3
VBIAS1
VBIAS3
–50
–50
VBIAS2
0
6M
14.3M
0 200
6M
14.3M
Frequency [Hz]
Frequency [Hz]
Application Circuit
fSC
0.5Vp-p sine wave
1.2k
TH output
(Forward
phase signal)
0.1µ
1M
2.2µ
29
4.7µ
82k
1µ
120
1µ
20
CCD1 input
(Reverse
phase signal)
3.3µ 0.01µ
3.3µ 0.01µ
30
28
27
26
25
24
7
23
22
21
19
18
17
14
16
1µ
CCD2 input
(Reverse
1.2k
1
2
3
4
5
6
8
9
10
11
12
13
15
phase signal)
Y-YD output
1µ
1µ
1M
1µ
1µ
1µ
0.01µ
3.3µ
9V
1µ
1.2k
1M
9V
CCD3 input
(Forward
YD output
(Reverse
phase signal)
Transistor used
PNP : 2SA1175
phase signal)
1.8k
5V
2SC403
22
Composite video
signal input
Signal output
4fsc
1.8k
When using pin 22 (4 × fsc output)
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 9 –
CXL1501M
Low frequency gain vs. Supply voltage
High frequency gain vs. Supply voltage
–1
–2
–3
–4
–5
–3
–4
–5
–6
4.75
5.0
5.25
4.75
5.0
5.25
VDD – Supply voltage [V]
VDD – Supply voltage [V]
Frequency response vs. Supply voltage
Differential gain vs. Supply voltage
10
8
0
–1
–2
–3
6
4
2
0
4.75
5.0
5.25
4.75
5.0
5.25
VDD – Supply voltage [V]
VDD – Supply voltage [V]
High frequency gain vs. Ambient temperature
Low frequency gain vs. Ambient temperature
–1
–3
–4
–5
–6
–2
–3
–4
–5
0
20
40
60
0
20
40
60
Ta – Ambient temperature [°C]
Ta – Ambient temperature [°C]
– 10 –
CXL1501M
Frequency response vs. Ambient temperature
Differential gain vs. Ambient temperature
10
0
–1
–2
8
6
4
2
0
–3
0
20
40
60
0
20
40
60
Ta – Ambient temperature [°C]
Ta – Ambient temperature [°C]
Chroma comb depth min. gain vs.
Ambient temperature
Chroma comb depth min. gain vs.
Supply voltage
–10
–20
–30
–40
–50
–10
–20
–30
–40
–50
4.75
5.00
5.25
0
20
40
60
VDD – Supply voltage [V]
Ta – Ambient temperature [°C]
Frequency response (TH, YD Output)
Chroma comb response (Y-YD Output)
0
–2
–4
–6
–8
0
–10
–20
–30
–40
10k
100k
1M
f – Frequency [Hz]
3.57
3.58
3.59
f – Frequency [MHz]
– 11 –
CXL1501M
Package Outline
Unit: mm
30PIN SOP (PLASTIC)
+ 0.4
2.3 – 0.15
+ 0.4
18.8 – 0.1
30
16
0.15
+ 0.2
0.1 – 0.05
15
1
+ 0.1
0.15 – 0.05
1.27
0.45 ± 0.1
0.24
M
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
EPOXY RESIN
SONY CODE
EIAJ CODE
SOP-30P-L01
SOLDER PLATING
42 ALLOY
SOP030-P-0375
JEDEC CODE
PACKAGE MASS
0.7g
– 12 –
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