CXL5504P [SONY]
CMOS-CCD 1H Delay Line for NTSC; 对于NTSC CMOS ， CCD 1H延时线
| 型号： | CXL5504P |
| 厂家： | 
SONY CORPORATION |
| 描述： | CMOS-CCD 1H Delay Line for NTSC |
| 文件： | 总11页 (文件大小：137K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXL5504M/P
CMOS-CCD 1H Delay Line for NTSC
For the availability of this product, please contact the sales office.
Description
CXL5504M
8 pin SOP (Plastic)
CXL5504P
8 pin DIP (Plastic)
The CXL5504M/P are CMOS-CCD delay line ICs
that provide 1H delay time for NTSC signals including
the external low-pass filter.
Features
• Single power supply (5V)
• Low power consumption 90mW (Typ.)
• Built-in peripheral circuits
• Clamp level of I/O signal can be selected
Functions
• 905-bit CCD register
• Clock driver
• Autobias circuit
• Input clamp circuit
• Sample and hold circuit
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VDD
6
V
°C
• Operating temperature Topr
• Storage temperature Tstg
• Allowable power dissipation
PD
–10 to +60
–55 to +150 °C
Structure
CXL5504M
CXL5504P
350
480
mW
mW
CMOS-CCD
Recommended Operating Condition (Ta = 25°C)
Supply voltage 5 ± 5%
VDD
V
Recommended Clock Conditions (Ta = 25°C)
• Input clock amplitude VCLK 0.4 to 1.0
Vp-p
(0.5Vp-p typ.)
14.318182 MHz
• Input clock waveform Sine wave
• Clock frequency
fCLK
Input Signal Amplitude
VSIG 500mVp-p (Typ.), 572mVp-p (Max.)
(at internal clamp condition)
Blook Diagram and Pin Configration (Top View)
8
7
6
5
Autobias circuit
Bias circuit
Timing circuit
Clock driver
CCD
(905bit)
Bias circuit (A)
Bias circuit (B)
Output circuit
(S/H 1bit)
Clamp circuit
1
I/O control
2
3
4
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E89931C79-PS
CXL5504M/P
Pin Description
Pin No.
Symbol
I/O
I
Description
Signal input
Impedance
IN
> 10kΩ at no clamp
1
2
3
4
5
6
7
8
I/O2
OUT
VSS
CLK
I/O1
VDD
AB
I
I/O control 2
Signal output
GND
O
—
I
40 to 500Ω
> 100kΩ
Clock input
I
I/O control 1
Power supply (5V)
Autobias DC output
—
O
600 to 200kΩ
Description of Function
In the CXL5504M/P, the condition of I/O control pins (Pins 2 and 6) control the input signal clamp condition and
the mode of the output signal with relation to its input signal.
There are 2 modes for the I/O signal.
Input waveform
Output waveform
(1) PN mode
(Low level clamp/reverse phase output mode)
Clamp
level
(2) NP mode
(High level clamp/positive phase output mode)
Clamp
level
I/O Control Pin
(1) I/O1 (Pin 6)
Control of the I/O signal condition
DC open ..... Input signal is low level clamped and the output signal is inverted in relation to the input
signal. As the pin is biased to 2.5V by means of the resistance inside the IC, a decoupling
capacitor of around 1000pF is necessary.
GND ............. Input signal is high level clamped and the output signal turns into an inverted signal.
(2) I/O2 (Pin 2)
Control of the input signal clamp condition
0V ................. Internal clamp condition
5V ................. Non internal clamp condition
Center biased to approx. 2.1V by means of the IC internal resistance (several 10kΩ).
Usage in this mode is limited to APL 50% signals and in this mode, the maximum input
signal amplitude is 200mVp-p.
– 2 –
CXL5504M/P
Electrical Characteristics
(Ta = 25°C, VDD = 5V, fCLK = 14.318182MHz, VCLK = 500mVp-p, Sine wave)
See "Electrical Characteristics Test Circuit"
Bias condition
SW condition
Vbias1 (V)
(Note 1)
Item
Symbol
Test condition
—
Min. Typ. Max. Unit Note
1 2
3 4 5 6 7
b b
IDDPN
IDDNP
GLPN
GLNP
fPN
Supply
current
—
— c b
a —
2
3
4
5
5
6
7
10
–2
–2
0
18
0
28
2
mA
dB
a a
b b
a a
b b
a a
b b
a a
b b
a a
b b
a a
b b
a a
Low
frequency
gain
200kHz,
500mVp-p,
sine wave
—
2.1
—
a a b
a b
b b
a c
a c
b a
a d
b
200kHz ←→ 3.57MHz,
150mVp-p,
sine wave
Frequency
response
–1
5
0
dB
a a
c
fNP
DGPN
DGNP
DPPN
DPNP
CPPN
CPNP
SNPN
a
5-staircase wave
(See Note 5)
Differential
gain
7
%
d
d
b
b
b
a
b
5-staircase wave
(See Note 5)
Differential
phase
0
5
7
degree
—
VINPN + 0.5
VINNP
S/H pulse
coupling
No signal input
—
52
—
56
350 mVp-p
— c a
50% white
video signal
a
—
—
dB
S/N ratio
e
b
SNNP (See Note 7)
b
Notes
(1) VINPN and VINNP are defined as follows.
VINPN and VINNP are the input signal clamp levels of PN and NP modes clamping the video signal sync
tip level.
CXL5504
1
Input
(IN)
VINPN
VINNP
Testing of VINPN and VINNP is executed with a voltmeter under the following SW conditions.
SW condition
Test
point
Item
1
2
c
c
3
b
b
4
b
a
5
b
a
6
a
a
7
VINPN
VINNP
—
—
—
—
V1
– 3 –
CXL5504M/P
(2) This is the IC supply current value during clock and signal input.
(3) GLPN, GLNP are output gain of OUT pin when a 500mVp-p, 200kHz sine wave is fed to IN pin.
(Example of calculation)
OUT pin output voltage (PN mode) [mVp-p]
GLPN = 20 log
[dB]
500 [mVp-p]
(4) Indicates the dissipation at 3.57MHz in relation to 200kHz.
From the output voltage at OUT pin when a 150mVp-p, 200kHz sine wave is fed to IN pin, and from the
output voltage at OUT pin when a 150mVp-p, 3.57MHz sine wave is fed to same, calculation is made
according to the following formula. The input part bias is tested at 2.1V.
(Example of calculation)
OUT pin otuput voltage (PN mode, 3.57MHz) [mVp-p]
fPN = 20 log
[dB]
OUT pin output voltage (PN mode, 200kHz) [mVp-p]
(5) The differential gain (DG) and the differential phase (DP), when the 5-staircase wave in the figure below is
input are tested at the vector scope.
143mV
357mV
500mV
143mV
1H 63.56µs
Input waveform (Input waveform of NP mode is the inverted waveform in the figure above)
(6) The internal clock component to the output signal during no-signal input and the leakage of that high
harmonic component are tested. The input part bias is tested at VINPN + 0.5V and VINNP for PN and NP
modes respectively.
Test value
(mVp-p)
– 4 –
CXL5504M/P
(7) S/N ratio during a 50% white video signal input shown in figure below is tested at a video noise meter, in
BPF 100kHz to 4MHz, Sub Carrier Trap mode.
178mV
321mV
143mV
1H 63.56µs
Input waveform (Input waveform of NP mode is the inverted waveform in the figure above)
Clock
fsc (14.318182MHz) sine wave
0.4 to 1.0Vp-p
(0.5Vp-p typ.)
– 5 –
CXL5504M/P
– 6 –
CXL5504M/P
– 7 –
CXL5504M/P
Example of Representative Characteristics
Supply current vs. Ambient temprature
Low frequency gain vs. Ambient temprature
1
30
0
20
–1
–2
–3
10
–20
0
20
40
60
80
–20
0
20
40
60
80
Ambient temprature [°C]
Ambient temprature [°C]
Frequency response vs. Ambient temprature
Differential gain vs. Ambient temprature
0
10
8
–1
6
4
–2
–3
2
0
–20
0
20
40
60
80
–20
0
20
40
60
80
Ambient temprature [°C]
Ambient temprature [°C]
Supply current vs. Supply voltage
Low frequency gain vs. Supply voltage
30
20
10
1
0
–1
–2
–3
4.75
5
5.25
4.75
5
5.25
Supply voltage [V]
Supply voltage [V]
– 8 –
CXL5504M/P
Frequency response vs. Supply voltage
Differential gain vs. Supply voltage
0
10
8
–1
6
4
–2
–3
2
0
4.75
5
5.25
4.75
5
5.25
Supply voltage [V]
Supply voltage [V]
Frequency response
2
0
–2
–4
–6
10k
100k
1M
10M
Frequency [Hz]
– 9 –
CXL5504M/P
Package Outline
Unit: mm
CXL5504M
8PIN SOP (PLASTIC)
+ 0.4
1.85 – 0.15
+ 0.4
6.1– 0.1
8
5
0.15
+ 0.2
0.1– 0.05
1
4
+ 0.1
0.2 – 0.05
0.45 ± 0.1
1.27
0.24
M
PACKAGE STRUCTURE
EPOXY RESIN
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
SOLDER PLATING
SONY CODE
EIAJ CODE
SOP-8P-L01
SOP008-P-0300
42/COPPER ALLOY
0.1g
PACKAGE MASS
JEDEC CODE
8PIN SOP (PLASTIC)
S
6.2 ± 0.3
0.15
S
8
5
A
1
4
+ 0.05
0.15 – 0.02
0.4 ± 0.1
1.27
0.05 MIN
M
S
0.13
10° MAX
DETAIL
A
PACKAGE STRUCTURE
EPOXY RESIN
PACKAGE MATERIAL
LEAD TREATMENT
SONY CODE
EIAJ CODE
SOP-8P-L121
PALLADIUM PLATING
COPPER ALLOY
0.1g
SOP008-P-0300
LEAD MATERIAL
PACKAGE MASS
JEDEC CODE
– 10 –
CXL5504M/P
CXL5504P
8PIN DIP (PLASTIC)
+ 0.4
9.4 – 0.1
5
8
0° to 15°
4
1
2.54
0.5 ± 0.1
1.2 ± 0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
EPOXY RESIN
SOLDER PLATING
SONY CODE
DIP-8P-01
EIAJ CODE
DIP008-P-0300
COPPER ALLOY
0.5g
PACKAGE MASS
JEDEC CODE
– 11 –
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