LCX007CN [SONY]
3.4cm (1.35-inch) Black-and-White LCD Panel; 3.4厘米（ 1.35英寸）的黑白LCD面板
| 型号： | LCX007CN |
| 厂家： | 
SONY CORPORATION |
| 描述： | 3.4cm (1.35-inch) Black-and-White LCD Panel |
| 文件： | 总24页 (文件大小：611K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LCX007CN
3.4cm (1.35-inch) Black-and-White LCD Panel
Description
The LCX007CN is a 3.4cm diagonal active matrix
TFT-LCD panel addressed by polycrystalline silicon
super thin film transistors with built-in peripheral
driving circuit. Use of three panels in combination
with the LCX007CL provides a full-color representation.
(The LCX007CN has the visual field angle characteristics
of mirror symmetry to those of the LCX007CL.)
This panel provides a wide aspect ratio of 16:9,
such as those represented in HD. The built-in side-
black function also allows an aspect ratio of 4:3 in
the NTSC/PAL mode.
This panel has a polysilicon TFT high-speed
scanner and built-in function to display images
up/down and/or right/left inverse. The built-in 5V
interface circuit leads to lower voltage of timing
system and control signals.
Features
• The number of active dots: 512,880 (1.35-inch; 3.4cm in diagonal)
• Horizontal resolution: 600 TV lines
• High optical transmittance: 16.5% (typ.)
• High contrast ratio with normally white mode: 190 (typ.)
• Built-in H and V drivers (built-in input level conversion circuit, 5V driving possible)
• NTSC/NTSC-WIDE/HD (band: 20MHz) mode selectable
(PAL/PAL-WIDE mode also available through conversion of scanned dot numbers by an external IC)
• Up/down and/or right/left inverse display function
• Side-black function
• 16:9 and 4:3 aspect-ratio switching function
Element Structure
• Dots
16:9 display: 1068.5 (H) × 480 (V) = 512,880
4:3 display: 799.5 (H) × 480 (V) = 383,760
• Built-in peripheral driver using polycrystalline silicon super thin film transistors.
Applications
• Liquid crystal projectors
• Super compact liquid crystal monitors
• Viewfinders etc.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E95Z05-ST
LCX007CN
Block Diagram
1
8
10 11
6
7
16 14 15 17
13
12
5
18
9
2
3
4
19
Input Signal
Level Shifter
H Shift Register (Bidirectional Scanning)
COM
Pad
– 2 –
LCX007CN
Absolute Maximum Ratings (VSS = 0V)
• H driver supply voltage
• V driver supply voltage
• Common pad voltage
HVDD
–1.0 to +20
–1.0 to +20
–1.0 to +17
–1.0 to +17
V
V
V
V
VVDD
COM
• H shift register input pin voltage
HST, HCK1, HCK2
RGT, WID
• V shift register input pin voltage
VST, VCK, PCG
CLR, ENB, DWN
SIG1, SIG2, SIG3, SID
Topr
–1.0 to +17
V
• Video signal input pin voltage
• Operating temperature
• Storage temperature
–1.0 to +15
–10 to +70
–30 to +85
V
°C
°C
Tstg
Operating Conditions (VSS = 0V)
• Supply voltage
+0.3
HVDD
VVDD
15.7
15.7
V
V
–0.4
+0.3
–0.4
• Input pulse voltage (Vp-p of all input pins except video signal and side black signal input pins)
Vin
5.0 ± 0.5
V
Pin Description
Pin
Pin
No.
Symbol
No.
Description
Symbol
HCK2
CLR
Description
Clock pulse for H shift register
drive
1
2
SID
Side black signal for 4:3 display
11
12
13
14
15
16
17
18
19
20
Improvement pulse (1) for
uniformity
1
SIG1 (G) Video signal (G ) to panel
1
3
SIG2 (R) Video signal (R ) to panel
ENB
Enable pulse for gate selection
Clock pulse for V shift register
drive
1
4
SIG3 (B)
HVDD
WID
Video signal (B ) to panel
VCK
Improvement pulse (2) for
uniformity
5
Power supply for H driver
PCG
Aspect-ratio switching
(H: 16:9, L: 4:3)
Start pulse for V shift register
drive
6
VST
Drive direction pulse for H shift
register (H: normal, L: reverse)
Drive direction pulse for V shift
register (H: normal, L: reverse)
7
RGT
DWN
VVDD
COM
TEST
Start pulse for H shift register
drive
8
HST
Power supply for V driver
Common voltage of panel
Test; Open
9
Vss
GND (H, V drivers)
Clock pulse for H shift register
drive
10
HCK1
1
(R), (G) and (B) are indicated for convenience to show the correspondence with the dot arrangement
diagram.
– 3 –
LCX007CN
Input Equivalent Circuit
To prevent static charges, protective diodes are provided for each pin except the power supply. In addition,
protective resistors are added to all pins except video signal input. All pins are connected to Vss with a high
resistance of 1MΩ (typ.). The equivalent circuit of each input pin is shown below: (The resistor value: typ.)
(1) SIG1, SIG2, SIG3, SID
HVDD
Input
1MΩ
Signal line
(2) HCK1, HCK2
HVDD
250Ω
250Ω
Level conversion circuit
(2-phase input)
Input
250Ω
1MΩ
250Ω
1MΩ
(3) RGT, WID
HVDD
2.5kΩ
2.5kΩ
Level conversion circuit
(single-phase input)
Input
1MΩ
(4) HST
HVDD
250Ω
250Ω
Level conversion circuit
(single-phase input)
Input
1MΩ
(5) PCG, VCK
VVDD
250Ω
250Ω
Level conversion circuit
(single-phase input)
Input
1MΩ
(6) VST, CLR, ENB, DWN
VVDD
2.5kΩ
2.5kΩ
Level conversion circuit
(single-phase input)
Input
1MΩ
(7) COM
VVDD
Input
LC
1MΩ
– 4 –
LCX007CN
Input Signals
1. Input signal voltage conditions
(VSS = 0V)
Item
Symbol
(Low) VHIL
(High) VHIH
(Low) VVIL
(High) VVIH
VVC
Min.
–0.5
Typ.
0.0
5.0
0.0
5.0
7.0
—
Max.
0.3
5.5
0.3
5.5
7.2
Unit
V
H driver input voltage
WID, RGT, HST, HCK1, HCK2
4.5
V
–0.5
V
V driver input voltage
CLR, ENB, VCK, PCG, VST, DWN
4.5
V
6.5
Video signal center voltage
V
1
Vsig
VVC – 4.5
Video signal input range
VVC + 4.5
VVC – 0.3
V
V
2
Vcom VVC – 0.5 VVC – 0.4
Common voltage of panel
1 Video input signal shall be symmetrical to VVC.
2 Common voltage of the panel shall be adjusted to VVC – 0.4V.
Level Conversion Circuit
The LCX007CN has a built-in level conversion circuit in the clock input unit on the panel. The input signal level
increases to HVDD or VVDD. The VCC of external ICs are applicable to 5 ± 0.5V.
– 5 –
LCX007CN
2. Clock timing conditions
(Ta = 25°C) (fHCKn = 7.5MHz, fVCK = 15.7kHz)
Item
Symbol
trHst
Min.
—
Typ.
—
Max.
30
Unit
Hst rise time
Hst fall time
HST
tfHst
—
—
30
Hst data set-up time
Hst data hold time
Hckn 3 rise time
Hckn 3 fall time
tdHst
thHst
trHckn
tfHckn
to1Hck
to2Hck
trClr
20
67
0
100
40
–40
—
—
30
—
—
30
HCK
CLR
Hck1 fall to Hck2 rise time
Hck1 rise to Hck2 fall time
Clr rise time
–15
–15
—
0
15
ns
0
15
—
100
100
3200
50
Clr fall time
tfClr
—
—
Clr pulse width
twClr
tdClr
3000
–50
—
3100
0
Vck rise/fall to Clr fall time
Vst rise time
trVst
—
100
100
25
Vst fall time
tfVst
—
—
VST
VCK
ENB
Vst data set-up time
Vst data hold time
Vck rise time
tdVst
thVst
trVck
tfVck
trEnb
tfEnb
tdEnb
twEnb
trPcg
tfPcg
toVck
twPcg
–25
5
15
15
—
µs
25
—
100
100
100
100
450
3550
20
Vck fall time
—
—
Enb rise time
—
—
Enb fall time
—
—
Vck rise/fall to Enb rise time
Enb pulse width
Pcg rise time
350
3450
—
400
3500
—
ns
Pcg fall time
—
—
20
PCG
Pcg fall to Vck rise/fall time
Pcg pulse width
650
1150
700
1200
750
1250
3 Hckn means Hck1 and Hck2.
– 6 –
LCX007CN
<Horizontal Shift Register Driving Waveform>
Item
Symbol
Waveform
Conditions
90%
90%
3
O Hckn
Hst rise time
trHst
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
Hst
10%
trHst
10%
tfHst
Hst fall time
tfHst
4
HST
HCK
CLR
50%
50%
Hst data set-up time
tdHst
Hst
3
O Hckn
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
Hck1
50%
50%
Hst data hold time
thHst
tdHst
thHst
90%
10%
90%
10%
Hckn 3 rise time
Hckn 3 fall time
trHckn
tfHckn
3
O Hckn
3
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
Hckn
trHckn
tfHckn
4
50%
50%
Hck1 fall to Hck2 rise
time
to1Hck
to2Hck
Hck1
50%
50%
Hck2
Clr
Hck1 rise to Hck2 fall
time
to2Hck
to1Hck
90%
90%
3
Clr rise time
Clr fall time
trClr
tfClr
O Hckn
duty cycle 50%
to1Hck = 0ns
to2Hck = 0ns
10%
10%
trClr
tfClr
Vck
50%
Clr pulse width
twClr
tdClr
50%
50%
twClr
Clr
Vck rise/fall to Clr fall
time
tdClr
4
– 7 –
LCX007CN
<Vertical Shift Register Driving Waveform>
Item
Symbol
trVst
Waveform
Conditions
90%
90%
Vst rise time
Vst
10%
50%
10%
50%
tfVst
Vst fall time
trVst
tfVst
4
VST
Vst data set-up time
tdVst
Vst
50%
50%
Vck
Vck
Vst data hold time
thVst
tdVst
thVst
90%
10%
90%
10%
Vck rise time
Vck fall time
Enb rise time
Enb fall time
trVck
tfVck
trEnb
tfEnb
VCK
trVckn
tfVckn
90%
90%
10% 10%
Enb
tfEn
trEn
ENB
Vck rise/fall to Enb rise
time
Vck
Enb
50%
tdEnb
twEnb
50%
50%
Enb pulse width
twEnb
4
tdEnb
Pcg rise time
Pcg fall time
trPcg
tfPcg
toVck
twPcg
Vck
Pcg
50%
PCG
Pcg fall to Vck rise/fall
time
50%
50%
twPcg
toVck
Pcg pulse width
4
4 Definitions:
The right-pointing arrow (
The left-pointing arrow (
The black dot at an arrow (
) means +.
) means –.
) indicates the start of measurement.
– 8 –
LCX007CN
Electrical Characteristics (Ta = 25°C, HVDD = 15.7V, VVDD = 15.7V)
1. Horizontal drivers
Item
Symbol
Min.
—
Typ.
7
Max.
10
10
—
Unit
pF
pF
µA
µA
µA
µA
pF
Condition
Input pin capacitance HCKn CHckn
HST
HCK1
CHst
—
7
Input pin current
–500
–1000
–500
–150
—
–120
–450
–160
–30
250
7.5
HCK1 = GND
HCK2
—
HCK2 = GND
HST = GND
HST
—
WID, RGT
—
WID, RGT = GND
Video signal input pin capacitance Csig
—
Current consumption
IH
—
10
mA HCKn: HCK1, HCK2 (7.5MHz)
2. Vertical drivers
Item
Input pin capacitance VCK
VST
Symbol
CVck
Min.
—
Typ.
7
Max.
10
10
—
Unit
pF
Condition
CVst
—
7
pF
Input pin current
VCK
–1000
–150
—
–160
–30
1.5
µA
µA
mA
VCK = GND
PCG, VST, EN, CLR, DWN
Current consumption
—
PCG, VST, EN, CLR, DWN = GND
VCK: (15.7kHz)
IV
4
3. Total power consumption of the panel
Item
Symbol
PWR
Min.
—
Typ.
150
Max.
250
Unit
mW
Total power consumption of
the panel (NTSC)
4. Pin input resistance
Item
Symbol
Rpin
Min.
0.4
Typ.
1
Max.
—
Unit
Pin-VSS input resistance
MΩ
5. Side signal input pin capacitance
Item
Symbol
Min.
8
Typ.
10
Max.
12
Unit
nF
Side signal input pin
capacitance
CSIDon
– 9 –
LCX007CN
Electro-optical Characteristics
(Ta = 25°C, NTSC mode)
Measurement
method
Item
Symbol
Max.
Unit
Min.
Typ.
Contrast ratio
—
—
130
14.0
1.2
1.4
1.7
1.1
1.2
1.4
1.7
1.8
2.0
1.5
1.6
1.8
2.3
2.4
2.6
2.1
2.2
2.4
—
190
16.5
1.5
1.7
2.0
1.4
1.5
1.7
2.0
2.1
2.3
1.8
1.9
2.1
2.6
2.7
2.9
2.4
2.5
2.7
50
—
%
60°C
60°C
CR60
T
1
2
Optical transmittance
1.8
2.0
2.3
1.7
1.8
2.0
2.3
2.4
2.6
2.1
2.2
2.4
2.9
3.0
3.2
2.7
2.8
3.0
100
40
RV90-25
GV90-25
BV90-25
RV90-60
GV90-60
BV90-60
RV50-25
GV50-25
BV50-25
RV50-60
GV50-60
BV50-60
RV10-25
GV10-25
BV10-25
RV10-60
GV10-60
BV10-60
ton0
25°C
60°C
25°C
60°C
25°C
60°C
V90
V-T
characteristics
3
V50
V
V10
0°C
25°C
0°C
ON time
Response time
—
15
ton25
toff0
4
ms
150
60
—
52
OFF time
—
16
toff25
F
25°C
60°C
25°C
25°C
–30
0
—
—
Flicker
5
6
7
dB
s
—
—
Image retention time
Cross talk
YT60
5
—
—
CTK
%
– 10 –
LCX007CN
<Electro-optical Characteristics Measurement>
Basic measurement conditions
(1) Driving voltage
HVDD = 15.7V, VVDD = 15.7V
VVC = 7.0V, Vcom = 6.6V
(2) Measurement temperature
25°C unless otherwise specified.
(3) Measurement point
One point in the center of screen unless otherwise specified.
(4) Measurement systems
Two types of measurement system are used as shown below.
(5) Video input signal voltage (Vsig)
Vsig = 7.0 ± VAC [V]
(VAC: signal amplitude)
• Measurement system I
Measurement
Equipment
Luminance
Meter
3.5mm
Back light: color temperature 6500 ± 700K (25°C)
Polarizer: POLATECHNO Co., Ltd. THC-13U (Luminance meter side)
LCD panel
• Measurement system II
Optical fiber
Measurement
Light Detector
Light receptor lens
Equipment
LCD panel
Drive Circuit
Light
Source
1. Contrast Ratio
Contrast Ratio (CR) is given by the following formula (1).
L (White)
CR =
... (1)
L (Black)
L (White): Surface luminance of the TFT-LCD panel at the input signal amplitude VAC = 0.5V.
L (Black): Surface luminance of the panel at VAC = 4.5V.
Both luminosities are measured by System I.
– 11 –
LCX007CN
2. Optical Transmittance
Optical Transmittance (T) is given by the following formula (2).
L (White)
T =
× 100 [%] ... (2)
Luminance of Back Light
L (White) is the same expression as defined in the 'Contrast Ratio' section.
3. V-T Characteristics
V-T characteristics, the relationship between signal
amplitude and the transmittance of the panels, are
measured by System II. V90, V50 and V10 correspond to
the each voltage which defines 90%, 50% and 10% of
transmittance respectively.
90
50
10
V90 V50 V10
VAC – Signal amplitude [V]
4. Response Time
Input signal voltage (waveform applied to the measured pixels)
Response time ‘ton’ and ‘toff’ are defined by
the formula (5) and (6) respectively.
4.5V
0.5V
7.0V
ton = t1 – tON ... (5)
toff = t2 – tOFF ... (6)
0V
t1: time which gives 10% transmittance of
the panel.
t2: time which gives 90% transmittance of
the panel.
Light transmission output waveform
100%
90%
The relationships between t1, t2, tON and
tOFF are shown in the right figure.
10%
0%
tON t1
ton
tOFF t2
toff
– 12 –
LCX007CN
5. Flicker
Flicker (F) is given by the formula (7). DC and AC (NTSC: 30Hz, rms, PAL: 25Hz, rms) components of the
panel output signal for gray raster mode are measured by a DC voltmeter and a spectrum analyzer in
System II.
AC component
Each input signal condition for gray raster mode is given by
Vsig = 7.0 ± V50 [V]
F [dB] = 20 log
... (7)
{
}
DC component
where: V50 is the signal amplitude which gives 50% of
transmittance in V-T characteristics.
6. Image Retention Time
Image Retention time is given by following procedures.
Apply the monoscope signal to the LCD panel for 60 minutes and then change this signal to the gray scale
of Vsig = 7.0 ± VAC (VAC: 3 to 4V). Hold VAC that maximizes image retention judging by sight. Measure the
time till the residual image becomes indistinct.
Black level
Monoscope signal conditions:
4.5V
White level
Vsig = 7.0 ± 4.5 or ± 2.0 [V]
(shown in the right figure)
Vcom = 6.6V
2.0V
7.0V
0V
2.0V
4.5V
Vsig waveform
7. Cross talk
Cross talk is determined by the luminance differences between adjacent areas represented Wi’ and Wi (i = 1
to 4) around black window (Vsig = 4.5V/1V).
W1 W1’
Wi’ – Wi
Cross talk CTK =
× 100 [%]
W2
Wi
W4
W2’
W4’
W3 W3'
– 13 –
LCX007CN
Viewing angle characteristics
90
CR = 5
10
Phi
20
30
50
200
100
150
0
180
10
50
70 Theta
270
θ0°
Z
θ
Marking
φ90°
Y
φ
φ180°
φ0°
X
φ270°
Measurment method
– 14 –
LCX007CN
Optical transmittance of LCD panel (Typical Value)
20
15
10
5
0
400
500
600
700
Wavelength [nm]
Measurement method: Measurement system II
– 15 –
LCX007CN
3 d o t s
( E f f e c t i v e 1 6 . 8 0 0 m m )
3 d o t s
4 8 0 d o t s
– 16 –
LCX007CN
3 d o t s
( E f f e c t i v e 1 6 . 8 0 0 m m ) 3 d o t s
4 8 0 d o t s
– 17 –
LCX007CN
2. LCD Panel Operations
[Description of basic operations]
The basic operations of the LCD panel are shown below based on the wide-display mode.
• A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse
to every 480 gate lines sequentially in every horizontal scanning period.
• A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuits,
applies selected pulses to every 1068.5 signal electrodes sequentially in a single horizontal scanning period.
• Vertical and horizontal shift registers address one pixel, and then turn on Thin Film Transistors (TFTs; two
TFTs) to apply a video signal to the dot. The same procedures lead to the entire 480 x 1068.5 dots to display
a picture in a single vertical scanning period.
• The LCD pixel dots are arranged in a delta pattern, where the dots connected to the identical signal line are
positioned with 1.5-dot offset against those of the adjacent horizontal line. Horizontal Start Pulse (HST) is
generated with 1.5-bit offset between the horizontal lines to regulate the above offset. HCK and sample-hold
(S/H) pulses follow the same 1.5-bit offset scheme.
• The CLR pin is provided to eliminate the shading effect caused by the coupling of selected pulses. While
maintaining the CLR at High level, the VVDD potential drops to approximately 9.5V. This pin shall be
grounded when not in use.
• The video signal shall be input with polarity-inverted system in every horizontal cycle.
• Timing diagrams of the vertical and the horizontal display cycle are shown below:
(1) Vertical display cycle
VD
VST
VCK
1
2
480
Vertical display cycle 480H
(2) Horizontal display cycle (16:9)
BLK
HST
356
357
HCK1
1
2
3
4
5
6
HCK2
Horizontal display cycle
(3) Horizontal display cycle (4:3)
BLK
HST
267
268
HCK1
1
2
3
4
5
6
HCK2
Horizontal display cycle
– 18 –
LCX007CN
[Description of operating mode]
The LCD panel has the following functions to easily apply to various uses, as well as various broadcasting
systems.
• Right/left inverse mode
• Up/down inverse mode
• 4:3 display mode with side-black display
These modes are controlled by three signals (RGT, DWN, and WID). The setting mode is shown below:
WID RGT
Mode
16:9 right scan
DWN
Mode
Down scan
Up scan
H
H
L
H
L
H
L
16:9 left scan
4:3 right scan
4:3 left scan
H
L
L
The direction of the right/left and/or up/down mean when Pin 1 marking is located at right side with the pin
block upside.
• The analog signal (SID) to display side-black shall be input by 1H inversion synchronized with the signal.
3. 3-dot Simultaneous Sampling
Horizontal driver samples SIG1, SIG2 and SIG3 signal simultaneously, which requires the phase matching
between SIG1, SIG2, and SIG3 signals to prevent horizontal resolution from deteriorating. Thus phase
matching between each signal is required using an external signal delaying circuit before applying video
signal to the LCD panel.
The block diagram of the delaying procedure using sample-and-hold method is as follows.
The LCX007 has the right/left inverse function. The following phase relationship diagram indicates the phase
setting for the right scan (RGT = High level). For the left scan (RGT = Low level), the phase setting shall be
inverted between SIG2 and SIG3 signals.
3
SIG2
SIG1
SIG3
S/H
S/H
AC Amp
SIG2
CK3
CK2
S/H
S/H
CK3
S/H
CK3
AC Amp
AC Amp
2
4
SIG1
SIG3
CK1
<Phase relationship of delaying sample-and-hold pulses> (right scan)
HCKn
CK2
CK1
CK3
– 19 –
LCX007CN
Display System Block Diagram
An example of display system is shown below.
SID
SIG2
SIG2
SIG1
SIG1
RGB Driver
CXA1819Q
SIG3
COM
SIG3
The SIG1, 2, 3 and
H SYNC signals with
double-speed processing
shall be applied to those
pins in the NTSC/PAL
modes.
FRP
SH
HST
LCD Panel
LCX007CN
HCK1
HCK2
HSYNC
VSYNC
VST
VCK
PCG
ENB
CLR
TG
CXD2412AQ
WID
RGT
DWN
– 20 –
LCX007CN
Reliability test conditions
Items
Test conditions
Ta = 70°C
HVDD = 15.7V
VVDD = 15.7V
Time
High temperature
operation
250h
Panel appearance
High temperature storage
Ta = 85°C
250h
250h
10cy
and performance
after those tests must
conform with the
standards.
High temperature & high
humidity storage
Ta = 40°C
95% RH
Temperature cycle
Vibration
Ta = –30 to +85°C
X, Y, Z, 1.5mm
10 to 55Hz (1min. reciprocation) direction
20min. for each
Anti-electrostatic discharge test results
Conditions: C = 200pF, Rs = 0Ω
Result:
Breakdown
voltage
Up to 100V
101 to 200V
+
–
–
–
–
Pin 8
Pins except pin no.8 have the strength more than 200V.
– 21 –
LCX007CN
Important
(1) Anti-reflection coating
Use anti-reflection coating when using a phase-shifting plate on a light egress side of the LCD to align a
polarization axis with those of a polarization screen or a prism.
(2) Direction of incident light
Allow incident light to hit upon an opposite side of a mark-indicated surface.
Direction of incidence
Marking side
(3) Polarizer
This LCD is attached with a polarizer on a light egress side. A suitable heat-dissipation method shall be
incorporated to suppress optical degradation of a polarizer.
(4) Light source
• Use visible light (wavelength λ = 400 to 780nm) as a light source. Do not use a light source containing
infrared or ultraviolet components.
• Suppress leakage light (reflection light) into a backside of a panel to sufficiently weak level or shut it out
completely.
– 22 –
LCX007CN
Notes on Handling
(1) Static charge prevention
Be sure to take following protective measures. TFT-LCD panels are easily damaged by static charge.
a) Use non-chargeable gloves, or simply use bare hands.
b) Use an earth-band when handling.
c) Do not touch any electrodes of a panel.
d) Wear non-chargeable clothes and conductive shoes.
e) Install conductive mat on the working floor and working table.
f) Keep panels away from any charged materials.
g) Use ionized air to discharge the panels.
(2) Protection from dust and dirt
a) Handle in clean environment.
b) When delivered, a surface of a panel (Polarizer) is covered by a protective sheet.
Peel off the protective sheet carefully not to damage the panel.
c) Do not touch the surface of a panel. The surface is easily scratched. When cleaning, use a clean-room
wiper with isopropyl alcohol. Be careful not to leave stain on the surface.
d) Use ionized air to blow off dust at a panel.
(3) Other handling precautions
a) Do not twist or bend the flexible PC board especially at the connecting region because the board is
easily deformed.
b) Do not drop a panel.
c) Do not twist or bend a panel or a panel frame.
d) Keep a panel away from heat source.
e) Do not dampen a panel with water or other solvents.
f) Avoid to store or to use a panel in a high temperature or in a high humidity, which may result in
panel damages.
g) Minimum radius of bending curvature for a flexible substrate must be 1mm.
h) Torque required to tighten screws on a panel must be 3kg · cm or less.
– 23 –
LCX007CN
Package Outline
Unit: mm
3.4 ± 0.1
Thickness of the connector 0.3 ± 0.05
31.4 ± 0.2
4.55 ± 0.1
21.0 ± 0.15
9.75 ± 1.5
1.8 ± 0.1
4
1
3
5
6
2-φ3.5
2
Incident
light
Polarizing
Axis
Active Area
7
(29.9)
20.25 ± 0.25
40.5 ± 0.15
No
1
Description
1.5 ± 0.15
P 1.0 × 19 = 19.0 ± 0.1
0.6 ± 0.05
F P C
Molding material
Outside frame
Reinforcing board
1.0 ± 0.15
2
3
PIN1
PIN20
4
5
6
7
Reinforcing material
Polarizing film
electrode (enlarged)
Cover
The rotation angle of the active area relative to H and V is ± 1°.
weight 7g
– 24 –
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