SSM4532GM [SSC]
N AND P-CHANNEL ENHANCEMENT MODE POWER MOSFET; N和P沟道增强型功率MOSFET
| 型号： | SSM4532GM |
| 厂家： | 
SILICON STANDARD CORP. |
| 描述： | N AND P-CHANNEL ENHANCEMENT MODE POWER MOSFET |
| 文件： | 总12页 (文件大小：303K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SSM4532GM
N AND P-CHANNEL ENHANCEMENT
MODE POWER MOSFET
PRODUCT SUMMARY
N-CH BVDSS
30V
50mΩ
5A
D2
D2
Simple Drive Requirement
Low On-resistance
Fast Switching
RDS(ON)
D1
D1
ID
P-CH BVDSS
RDS(ON)
G2
S2
-30V
70mΩ
-4A
G1
SO-8
S1
DESCRIPTION
ID
The advanced power MOSFETs from Silicon Standard Corp.
provide the designer with the best combination of fast switching,
ruggedized device design, low on-resistance and cost-effectiveness.
The SO-8 package is universally preferred for all commercial-
industrial surface mount applications and suited for low voltage
applications such as DC/DC converters.
D2
D1
S1
Pb-free; RoHS-compliant
G2
G1
S2
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Rating
Units
N-channel
P-channel
-30
VDS
VGS
Drain-Source Voltage
Gate-Source Voltage
30
±20
5
V
V
±20
ID@TA=25℃
ID@TA=70℃
IDM
Continuous Drain Current3
Continuous Drain Current3
Pulsed Drain Current1
-4
A
A
4
-3.2
20
-20
A
PD@TA=25℃
Total Power Dissipation
2.0
W
Linear Derating Factor
0.016
W/℃
℃
TSTG
TJ
Storage Temperature Range
Operating Junction Temperature Range
-55 to 150
-55 to 150
℃
THERMAL DATA
Symbol
Parameter
Thermal Resistance Junction-ambient3
Value
62.5
Unit
Rthj-amb
Max.
℃/W
08/17/2007 Rev.1.00
www.SiliconStandard.com
1
SSM4532GM
N-CH ELECTRICAL CHARACTERISTICS
@Tj=25oC (unless otherwise specified)
Symbol
BVDSS
Parameter
Test Conditions
VGS=0V, ID=250uA
Min. Typ. Max. Units
Drain-Source Breakdown Voltage
30
-
-
-
-
V
ΔBVDSS/ΔTj
Breakdown Voltage Temperature Coefficient Reference to 25℃, ID=1mA
Static Drain-Source On-Resistance2 VGS=10V, ID=5A
VGS=4.5V, ID=4.2A
0.037
V/℃
RDS(ON)
-
-
-
50 mΩ
70 mΩ
-
VGS(th)
gfs
Gate Threshold Voltage
VDS=VGS, ID=250uA
VDS=10V, ID=5A
1
-
-
3
-
V
Forward Transconductance
8
S
IDSS
Drain-Source Leakage Current (T=25oC)
uA
uA
nA
nC
nC
nC
ns
ns
ns
ns
pF
pF
pF
VDS=30V, VGS=0V
VDS=24V, VGS=0V
VGS=±20V
ID=5A
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
j
Drain-Source Leakage Current (T=70oC)
25
j
IGSS
Qg
±100
Gate-Source Leakage
Total Gate Charge2
Gate-Source Charge
Gate-Drain ("Miller") Charge
Turn-on Delay Time2
Rise Time
-
10.2
1.2
3.4
6
-
-
-
-
-
-
Qgs
Qgd
td(on)
tr
VDS=10V
VGS=10V
VDS=10V
ID=1A
9
td(off)
tf
Turn-off Delay Time
Fall Time
RG=6Ω,VGS=10V
RD=10Ω
15
5.5
240
145
55
-
-
-
-
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
VGS=0V
VDS=25V
f=1.0MHz
SOURCE-DRAIN DIODE
Symbol
Parameter
Test Conditions
Min. Typ. Max. Units
A
V
IS
Continuous Source Current ( Body Diode )
VD=VG=0V , VS=1.2V
-
-
-
-
1.7
1.2
VSD
Forward On Voltage2
Tj=25℃, IS=1.7A, VGS=0V
08/17/2007 Rev.1.00
www.SiliconStandard.com
2
SSM4532GM
P-CH ELECTRICAL CHARACTERISTICS
@Tj=25oC (unless otherwise specified)
Symbol
BVDSS
Parameter
Test Conditions
VGS=0V, ID=250uA
Min. Typ. Max. Units
Drain-Source Breakdown Voltage
-30
-
-
-0.028
-
-
-
V
ΔBVDSS/ΔTj
Breakdown Voltage Temperature Coefficient Reference to 25℃, ID=-1mA
Static Drain-Source On-Resistance2 VGS=-10V, ID=-4A
V/℃
RDS(ON)
-
70 mΩ
90 mΩ
VGS=-4.5V, ID=-3A
-
-
VGS(th)
gfs
Gate Threshold Voltage
VDS=VGS, ID=-250uA
VDS=-10V, ID=-4A
VDS=-30V, VGS=0V
VDS=-24V, VGS=0V
VGS= ± 20V
ID=-4A
-1
-
-
-3
V
Forward Transconductance
Drain-Source Leakage Current (T=25oC)
5
-
S
IDSS
uA
uA
nA
nC
nC
nC
ns
ns
ns
ns
pF
pF
pF
-
-
-1
j
Drain-Source Leakage Current (T=70oC)
-
-
-25
j
IGSS
Qg
Gate-Source Leakage
Total Gate Charge2
Gate-Source Charge
Gate-Drain ("Miller") Charge
Turn-on Delay Time2
Rise Time
-
-
±100
-
18.3
3.6
1.5
8
-
-
-
-
-
-
-
-
-
-
Qgs
Qgd
td(on)
tr
VDS=-10V
-
VGS=-10V
-
VDS=-10V
-
ID=-1A
-
9
td(off)
tf
Turn-off Delay Time
Fall Time
RG=6Ω,VGS=-10V
RD=10Ω
-
21
10
760
345
90
-
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
VGS=0V
-
VDS=-25V
-
f=1.0MHz
-
SOURCE-DRAIN DIODE
Symbol
Parameter
Test Conditions
VD=VG=0V , VS=-1.2V
Tj=25℃, IS=-1.7A, VGS=0V
Min. Typ. Max. Units
A
V
IS
Continuous Source Current ( Body Diode )
-
-
-
-
-1.7
-1.2
VSD
Forward On Voltage2
Notes:
1.Pulse width limited by Max. junction temperature.
2.Pulse width <300us , duty cycle <2%.
3.Surface mounted on 1 in2 copper pad of FR4 board ; 135℃/W when mounted on Min. copper pad.
08/17/2007 Rev.1.00
www.SiliconStandard.com
3
SSM4532GM
N-Channel
50
40
30
20
10
0
70
T C=150 oC
T C=25 oC
60
50
40
30
20
10
0
10V
10V
8.0V
8.0V
6.0V
4.0V
6.0V
4.0V
VGS =3.0V
VGS =3.0V
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
85
1.8
1.6
1.4
1.2
1.0
0.8
0.6
I D=5A
I D=5A
V
GS =10V
T C=25 ℃
75
65
55
45
35
Ω
Ω
Ω
Ω
3
4
5
6
7
8
9
10
11
-50
0
50
100
150
T j , Junction Temperature ( oC)
VGS (V)
Fig 3. On-Resistance v.s. Gate Voltage
Fig 4. Normalized On-Resistance
v.s. Junction Temperature
08/17/2007 Rev.1.00
www.SiliconStandard.com
4
SSM4532GM
N-Channel
3
2
1
0
6
5
4
3
2
1
0
0
50
100
150
25
50
75
100
125
150
T c ,Case Temperature ( oC)
T c , Case Temperature ( oC)
Fig 5. Maximum Drain Current v.s.
Case Temperature
Fig 6. Typical Power Dissipation
100
1
Duty Factor = 0.5
0.2
10
0.1
0.1
1ms
0.05
10ms
1
0.02
0.01
100ms
1s
PDM
0.01
t
T
0.1
Single Pulse
Duty Factor = t/T
10s
DC
Peak Tj = PDM x R + Ta
thja
Rthja =135oC/W
T C=25 oC
Single Pulse
0.001
0.0001
0.01
0.001
0.01
0.1
1
10
100
1000
0.1
1
10
100
t , Pulse Width (s)
VDS (V)
Fig 7. Maximum Safe Operating Area
Fig 8. Effective Transient Thermal Impedance
08/17/2007 Rev.1.00
www.SiliconStandard.com
5
SSM4532GM
N-Channel
f=1.0MHz
12
1000
100
10
I D=5A
10
8
V
DS =10V
Ciss
Coss
6
Crss
4
2
0
0
2
4
6
8
10
12
1
5
9
13
17
21
25
29
VDS (V)
Q G , Total Gate Charge (nC)
Fig 9. Gate Charge Characteristics
Fig 10. Typical Capacitance Characteristics
3
2.5
2
100
10
T j =150 oC
T j =25 oC
1
1.5
1
0.1
0.5
0.01
0
0.1
0.3
0.5
0.7
0.9
1.1
1.3
1.5
-50
0
50
100
150
T j ,Junction Temperature ( oC)
VSD (V)
Fig 11. Forward Characteristic of
Reverse Diode
Fig 12. Gate Threshold Voltage v.s.
Junction Temperature
08/17/2007 Rev.1.00
www.SiliconStandard.com
6
SSM4532GM
N-Channel
VDS
RD
90%
VDS
TO THE
OSCILLOSCOPE
D
S
0.33x RATED VDS
RG
G
10%
VGS
+
-
VGS
10V
td(off)
td(on) tr
tf
Fig 13. Switching Time Circuit
Fig 14. Switching Time Waveform
VG
VDS
QG
TO THE
OSCILLOSCOPE
D
S
10V
0.33 x RATED VDS
QGD
QGS
G
VGS
+
1~ 3 mA
-
I
I
D
G
Q
Charge
Fig 15. Gate Charge Circuit
Fig 16. Gate Charge Waveform
08/17/2007 Rev.1.00
www.SiliconStandard.com
7
SSM4532GM
P-Channel
20
15
10
5
20
-10V
-8.0V
-6.0V
-10V
-8.0V
-6.0V
15
10
5
V GS =-4.0V
V GS =-4.0V
T C =25 o C
T C =150 o C
0
0
0
0
1
2
3
4
5
1
2
3
4
-VDS , Drain-to-Source Voltage (V)
-VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
90
80
70
60
50
40
30
1.8
1.6
1.4
1.2
1
I
D =-4.0A
I D =-4.0A
V GS = -10V
T C =25 ℃
Ω
Ω
Ω
Ω
0.8
0.6
-50
0
50
100
150
3
4
5
6
7
8
9
10
11
T j , Junction Temperature ( o C)
-VGS (V)
Fig 3. On-Resistance v.s. Gate Voltage
Fig 4. Normalized On-Resistance
v.s. Junction Temperature
08/17/2007 Rev.1.00
www.SiliconStandard.com
8
SSM4532GM
P-Channel
3
2.5
2
5
4
3
2
1
1.5
1
0.5
0
0
0
50
100
150
25
50
75
100
125
150
T c ,Case Temperature ( o C)
T c , Case Temperature ( o C)
Fig 5. Maximum Drain Current v.s.
Case Temperature
Fig 6. Typical Power Dissipation
1
100
Duty Factor = 0.5
0.2
0.1
10
0.1
1ms
0.05
0.02
10ms
1
0.01
PDM
100ms
1s
t
0.01
T
Single Pulse
0.1
Duty Factor = t/T
Peak Tj = PDM x Rthja+ Ta
Rthja=135oC/W
T C =25 o C
10s
DC
Single Pluse
0.01
0.001
0.1
1
10
100
0.0001
0.001
0.01
0.1
1
10
100
1000
t , Pulse Width (s)
-VDS (V)
Fig 7. Maximum Safe Operating Area
Fig 8. Effective Transient Thermal Impedance
08/17/2007 Rev.1.00
www.SiliconStandard.com
9
SSM4532GM
P-Channel
f=1.0MHz
12
10000
1000
100
I D =-4A
V DS =-10V
10
8
Ciss
6
Coss
4
Crss
2
0
10
0
2
4
6
8
10
12
14
16
18
20
1
5
9
13
17
21
25
29
-VDS (V)
Q G , Total Gate Charge (nC)
Fig 9. Gate Charge Characteristics
Fig 10. Typical Capacitance Characteristics
3
2.5
2
100
10
T j =150 o C
T j =25 o C
1.5
1
1
0.1
0.5
0
0.01
-50
0
50
100
150
0.1
0.3
0.5
0.7
0.9
1.1
1.3
1.5
T j ,Junction Temperature ( o C)
-V SD (V)
Fig 11. Forward Characteristic of
Reverse Diode
Fig 12. Gate Threshold Voltage v.s.
Junction Temperature
08/17/2007 Rev.1.00
www.SiliconStandard.com
10
SSM4532GM
P-Channel
VDS
RD
90%
VDS
TO THE
OSCILLOSCOPE
D
S
0.33 x RATED VDS
RG
G
10%
VGS
-10 V
VGS
td(off)
td(on) tr
tf
Fig 13. Switching Time Circuit
Fig 14. Switching Time Waveform
VG
VDS
QG
TO THE
OSCILLOSCOPE
D
S
-10V
0.33 x RATED VDS
QGD
QGS
G
VGS
-1~-3mA
I
ID
G
Q
Charge
Fig 15. Gate Charge Circuit
Fig 16. Gate Charge Waveform
08/17/2007 Rev.1.00
www.SiliconStandard.com
11
SSM4532GM
Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no
guarantee or warranty, expressed or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no
responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its
use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including
without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to
the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of
Silicon Standard Corporation or any third parties.
08/17/2007 Rev.1.00
www.SiliconStandard.com
12
相关型号：
©2020 ICPDF网 联系我们和版权申明