SSM9973GM [SSC]
Dual N-channel Enhancement-mode Power MOSFETs; 双N沟道增强型功率MOSFET
| 型号： | SSM9973GM |
| 厂家： | 
SILICON STANDARD CORP. |
| 描述： | Dual N-channel Enhancement-mode Power MOSFETs |
| 文件： | 总5页 (文件大小：260K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SSM9973GM
Dual N-channel Enhancement-mode Power MOSFETs
Simple drive requirement
Lower gate charge
BVDSS
RDS(ON)
IID
60V
D2
D2
D1
80mΩ
3.9A
D1
Fast switching characteristics
G2
S2
Pb-free; RoHS compliant.
G1
SO-8
S1
DESCRIPTION
D2
D1
Advanced Power MOSFETs from Silicon Standard provide the
designer with the best combination of fast switching, ruggedized
device design, low on-resistance and cost-effectiveness.
G2
G1
The SSM9973M is in an SO-8 package, which is widely preferred for
commercial and industrial surface mount applications. This device is
suitable for low voltage applications such as DC/DC converters.
S1
S2
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Drain-Source Voltage
Rating
Units
V
VDS
VGS
60
± 20
Gate-Source Voltage
V
ID @ TA=25°C
ID @ TA=70°C
IDM
Continuous Drain Current3
Continuous Drain Current3
Pulsed Drain Current1
3.9
A
2.5
A
20
A
PD @ TA=25°C
Total Power Dissipation
2
W
Linear Derating Factor
0.016
-55 to 150
-55 to 150
W/°C
°C
°C
TSTG
TJ
Storage Temperature Range
Operating Junction Temperature Range
THERMAL DATA
Symbol
Rthj-a
Parameter
Thermal Resistance Junction-ambient3
Value
62.5
Unit
Max.
°C/W
12/10/2004 Rev.2.03
www.SiliconStandard.com
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SSM9973GM
o
(unless otherwise specified)
ELECTRICAL CHARACTERISTICS @ T = 25 C
j
Symbol
BVDSS
Parameter
Test Conditions
VGS=0V, ID=250uA
Min. Typ. Max. Units
Drain-Source Breakdown Voltage
60
-
-
0.06
-
-
V
∆BVDSS/∆Tj
Breakdown Voltage Temperature Coefficient Reference to 25°C, ID=1mA
Static Drain-Source On-Resistance2 VGS=10V, ID=3.9A
VGS=4.5V, ID=2A
-
V/°C
mΩ
RDS(ON)
-
80
-
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
100 mΩ
VGS(th)
gfs
Gate Threshold Voltage
VDS=VGS, ID=250uA
VDS=10V, ID=3.9A
VDS=60V, VGS=0V
VDS=48V ,VGS=0V
3
-
V
Forward Transconductance
Drain-Source Leakage Current (T=25oC)
3.5
-
S
IDSS
uA
uA
nA
nC
nC
nC
ns
ns
ns
ns
pF
pF
pF
j
1
Drain-Source Leakage Current (T=70oC)
-
25
j
IGSS
Qg
± 20V
±100
Gate-Source Leakage
Total Gate Charge2
Gate-Source Charge
Gate-Drain ("Miller") Charge
Turn-on Delay Time2
Rise Time
VGS
=
-
ID=3.9A
8
13
-
Qgs
Qgd
td(on)
tr
VDS=48V
VGS=4.5V
VDS=30V
ID=1A
2
4
-
8
-
4
-
td(off)
tf
Turn-off Delay Time
Fall Time
RG=3.3Ω , VGS=10V
RD=30Ω
20
6
-
-
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
VGS=0V
700 1120
VDS=25V
f=1.0MHz
80
50
-
-
SOURCE-DRAIN DIODE
Symbol
Parameter
Forward On Voltage2
Test Conditions
IS=3.9A, VGS=0V
IS=3.9A, VGS=0V,
dI/dt=100A/µs
Min. Typ. Max. Units
VSD
trr
-
-
-
-
1.2
V
Reverse Recovery Time
Reverse Recovery Charge
28
35
-
-
ns
nC
Qrr
Notes:
1.Pulse width limited by maximum junction temperature.
2.Pulse width <300us, duty cycle <2%.
3.Surface-mounted on 1 in2 copper pad of FR4 board ; 135°C/W when mounted on minimum copper pad.
12/10/2004 Rev.2.03
www.SiliconStandard.com
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SSM9973GM
40
35
30
25
20
15
10
5
30
25
20
15
10
5
10V
6.0V
5.0V
4.5V
10V
6.0V
5.0V
4.5V
T
A =25 o C
T A =150 o C
V G =3.0V
V G =3.0V
0
0
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
V DS , Drain-to-Source Voltage (V)
V DS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
95
2.5
2.0
1.5
1.0
0.5
0.0
I
D =3.9A
I D =3.9A
V G =10V
T
A =25 o C
90
85
80
75
70
3
5
7
9
11
-50
0
50
100
150
T j , Junction Temperature ( o C)
V GS , Gate-to-Source Voltage (V)
Fig 3. On-Resistance vs. Gate Voltage
Fig 4. Normalized On-Resistance
vs. Junction Temperature
4
3
2
1
0
2.5
2
1.5
T j =150 o C
T j =25 o C
1
0.5
0
0.2
0.4
0.6
0.8
1
1.2
1.4
-50
0
50
100
150
T j ,Junction Temperature ( o C)
V SD , Source-to-Drain Voltage (V)
Fig 5. Forward Characteristic of
Reverse Diode
Fig 6. Gate Threshold Voltage vs.
Junction Temperature
12/10/2004 Rev.2.03
www.SiliconStandard.com
3 of 5
SSM9973GM
f=1.0MHz
14
12
10
8
10000
1000
100
I D =3.9A
V DS =30V
V DS =38V
V DS =48V
Ciss
6
4
Coss
Crss
2
0
10
0
4
8
12
16
20
1
5
9
13
17
21
25
29
V DS , Drain-to-Source Voltage (V)
Q G , Total Gate Charge (nC)
Fig 7. Gate Charge Characteristics
Fig 8. Typical Capacitance Characteristics
1
100
Duty factor=0.5
0.2
10
0.1
0.1
0.05
1ms
1
PDM
0.02
0.01
t
T
10ms
0.01
Duty factor = t/T
Peak Tj = PDM x Rthja + Ta
Single Pulse
Rthja=135℃/W
0.1
100ms
1s
T A =25 o C
Single Pulse
DC
0.01
0.001
0.1
1
10
100
1000
0.0001
0.001
0.01
0.1
1
10
100
1000
V DS , Drain-to-Source Voltage (V)
t , Pulse Width (s)
Fig 9. Maximum Safe Operating Area
Fig 10. Effective Transient Thermal Impedance
VG
VDS
90%
QG
4.5V
QGS
QGD
10%
VGS
tr
td(on)
td(off) tf
Q
Charge
Fig 11. Switching Time Waveform
Fig 12. Gate Charge Waveform
12/10/2004 Rev.2.03
www.SiliconStandard.com
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SSM9973GM
Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no
guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no
responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its
use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including
without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to
the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of
Silicon Standard Corporation or any third parties.
12/10/2004 Rev.2.03
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