74VHC74M [STMICROELECTRONICS]
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR; 带预置和清除两个D型触发器
| 型号： | 74VHC74M |
| 厂家： | 
ST |
| 描述： | DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR |
| 文件： | 总10页 (文件大小：77K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74VHC74
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
■
■
■
HIGH SPEED:
fMAX =170MHz (TYP.)atVCC =5V
LOW POWER DISSIPATION:
ICC =2 µA (MAX.) at TA =25 oC
HIGH NOISEIMMUNITY:
M
T
VNIH = VNIL =28% VCC (MIN.)
(Micro Package)
(TSSOPPackage)
■
■
POWERDOWN PROTECTIONON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 8 mA (MIN)
ORDER CODES :
74VHC74M
74VHC74T
■
■
■
■
BALANCEDPROPAGATIONDELAYS:
tPLH tPHL
OPERATING VOLTAGERANGE:
VCC (OPR)= 2V to 5.5V
PIN AND FUNCTION COMPATIBLEWITH
74 SERIES74
IMPROVED LATCH-UP IMMUNITY
CLEAR and PRESET are independent of the
clock and accomplished by a low setting on the
appropriateinput.
It is ideal for low power applications maintaining
high speed operation similar to equivalent Bipolar
SchottkyTTL.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
DESCRIPTION
The 74VHC74 is an advanced high-speed CMOS
DUAL D-TYPE FLIP FLOP WITH PRESET AND
CLEAR fabricated with sub-micron silicon gate
and
double-layer metal
wiring
C2MOS
technology.
A signal on the D INPUT is transfered to the Q
OUTPUT during the positive going transition of
the clock pulse.
PIN CONNECTION AND IEC LOGIC SYMBOLS
1/10
June 1999
74VHC74
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
SYMBOL NAME AND FUNCTION
1, 13
1CLR,
2CLR
Asyncronous Reset -
Direct Input
2, 12
3, 11
1D, 2D
Data Input
1CK, 2CK Clock Input
(LOW-to-HIGH, Edge-
Triggered)
4, 10
1PR, 2PR Asyncronous Set - Direct
Input
5, 9
6, 8
1Q, 2Q
1Q, 2Q
True Flip-Flop Outputs
Complement Flip-Flop
Outputs
7
GND
VCC
Ground (0V)
14
Positive Supply Voltage
TRUTH TABLE
INPUTS
OUTPUTS
FUNCTION
CLR
L
PR
H
L
D
X
X
X
L
CK
X
Q
L
Q
H
L
CLEAR
H
X
H
H
L
PRESET
L
L
X
H
H
L
H
H
H
H
H
H
X
H
Qn
H
Qn
NO CHANGE
X:Don’t Care
LOGIC DIAGRAMS
Thislogic diagram has notbe used to estimate propagation delays
2/10
74VHC74
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
VI
Parameter
Value
-0.5 to +7.0
-0.5 to +7.0
-0.5 to VCC + 0.5
- 20
Unit
V
Supply Voltage
DC Input Voltage
V
VO
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
V
IIK
mA
mA
mA
mA
oC
IOK
± 20
IO
25
50
±
±
ICC or IGND DC VCC or Ground Current
Tstg
TL
Storage Temperature
-65 to +150
300
Lead Temperature (10 sec)
oC
AbsoluteMaximum Ratingsarethose values beyond whichdamage tothe device may occur. Functional operation under these condition isnot implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VI
Parameter
Value
2.0 to 5.5
0 to 5.5
Unit
V
Supply Voltage
Input Voltage
V
VO
Output Voltage
0 to VCC
-40 to +85
V
oC
Top
Operating Temperature
dt/dv
0 to 100
0 to 20
ns/V
ns/V
Input Rise and Fall Time (see note 1) (VCC = 3.3 ± 0.3V)
(V CC = 5.0 0.5V)
±
1)VIN from30% to70%of VCC
DC SPECIFICATIONS
Symbol
Parameter
Test Conditions
VCC
Value
TA = 25 oC
Unit
-40 to 85 oC
(V)
Min. Typ. Max. Min. Max.
VIH
VIL
High Level Input
Voltage
2.0
3.0 to 5.5
2.0
1.5
1.5
V
V
0.7VCC
0.7VCC
Low Level Input
Voltage
0.5
0.5
3.0 to 5.5
2.0
0.3VCC
0.3VCC
VOH
High Level Output
Voltage
IO=-50 µA
IO=-50 µA
1.9
2.9
2.0
3.0
4.5
1.9
2.9
3.0
V
V
4.5
I =-50
O
A
4.4
4.4
µ
3.0
IO=-4 mA
IO=-8 mA
IO=50 µA
IO=50 µA
2.58
3.94
2.48
3.8
4.5
VOL
Low Level Output
Voltage
2.0
0.0
0.0
0.0
0.1
0.1
0.1
0.1
3.0
4.5
I =50
O
A
0.1
0.1
µ
3.0
IO=4 mA
IO=8 mA
0.36
0.36
±0.1
2
0.44
0.44
±1.0
20
4.5
II
Input Leakage Current
0 to 5.5
5.5
VI = 5.5V or GND
VI = VCC or GND
µA
µA
ICC
Quiescent Supply
Current
3/10
74VHC74
AC ELECTRICAL CHARACTERISTICS
(Input tr = tf =3 ns)
Symbol
Parameter
Test Condition
Value
TA = 25 oC
Min. Typ. Max. Min. Max.
Unit
VCC
(V)
CL
(pF)
-40 to 85 oC
tPLH
tPHL
Propagation Delay
Time
CK to Q or Q
3.3(*)
3.3(*)
15
50
6.7
9.2
4.6
6.1
7.6
10.1
4.8
6.3
11.9
15.4
7.3
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
14.0
17.5
8.5
ns
ns
5.0(**)
5.0(**)
3.3(*)
3.3(*)
5.0(**)
5.0(**)
3.3(*)
5.0(**)
3.3(*)
5.0(**)
15
50
15
50
15
50
9.3
10.5
14.5
18.0
9.0
tPLH
tPHL
Propagation Delay
Time
PR or CLR to Q or Q
12.3
15.8
7.7
9.7
11.0
7.0
tw
tw
CK Pulse Width
HIGH or LOW
6.0
ns
ns
ns
ns
ns
5.0
5.0
PR or CLR Pulse
Width LOW
6.0
7.0
5.0
5.0
ts
Setup Time D to CK
HIGH or LOW
3.3(*)
5.0(**)
6.0
5.0
7.0
5.0
th
Hold Time D to CK
HIGH or LOW
3.3(*)
5.0(**)
3.3(*)
5.0(**)
3.3(*)
3.3(*)
5.0(**)
5.0(**)
0.5
0.5
5.0
3.0
0.5
0.5
5.0
3.0
tREM
fMAX
Removal Time CLR or
PR to CK
Maximum Clock
Frequency
15
50
15
50
80
50
125
75
70
45
MHz
130
90
170
115
110
75
(*) Voltagerangeis3.3V 0.3V
±
(**) Voltagerange is 5V± 0.5V
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Test Conditions
Value
TA = 25 oC
Unit
VCC
-40 to 85 oC
(V)
Min. Typ. Max. Min. Max.
CIN
Input Capacitance
4
10
10
3.3
3.3
pF
pF
CPD
Power Dissipation
fIN = 10 MHz
25
Capacitance (note 1)
1)CPD isdefined as thevalue ofthe IC’sinternal equivalent capacitance whichiscalculated fromthe operating current consumption without load. (Referto
TestCircuit).Average operting current can beobtained bythe followingequation. ICC(opr)= CPD • VCC • fIN + ICC/2(per Flip-Fliop)
4/10
74VHC74
TEST CIRCUIT
CL = 15/50 pF or equivalent (includes jig and probe capacitance)
RT = ZOUT ofpulse generator (typically50Ω)
WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES
(f=1MHz; 50% duty cycle)
5/10
74VHC74
WAVEFORM 2: PROPAGATION DELAYS
(f=1MHz; 50% duty cycle)
6/10
74VHC74
WAVEFORM 3: RECOVERY TIMES
(f=1MHz; 50% duty cycle)
WAVEFORM 3: PULSE WIDTH
7/10
74VHC74
SO-14 MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
TYP.
MAX.
1.75
0.2
MIN.
MAX.
0.068
0.007
0.064
0.018
0.010
A
a1
a2
b
0.1
0.003
1.65
0.46
0.25
0.35
0.19
0.013
0.007
b1
C
0.5
0.019
c1
D
45 (typ.)
8.55
5.8
8.75
6.2
0.336
0.228
0.344
0.244
E
e
1.27
7.62
0.050
0.300
e3
F
3.8
4.6
0.5
4.0
5.3
0.149
0.181
0.019
0.157
0.208
0.050
0.026
G
L
1.27
0.68
M
S
8 (max.)
P013G
8/10
74VHC74
TSSOP14 MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
TYP.
MAX.
1.1
MIN.
MAX.
0.433
0.006
0.374
0.0118
0.0079
0.201
0.256
0.176
A
A1
A2
b
0.05
0.85
0.19
0.09
4.9
0.10
0.9
0.15
0.95
0.30
0.20
5.1
0.002
0.335
0.0075
0.0035
0.193
0.246
0.169
0.004
0.354
c
D
5
6.4
0.197
0.252
E
6.25
4.3
6.5
E1
e
4.4
4.48
0.173
0.65 BSC
4o
0.0256 BSC
4o
K
0o
8o
0o
8o
L
0.50
0.60
0.70
0.020
0.024
0.028
A2
A
K
L
b
e
A1
c
E
D
E1
PIN 1 IDENTIFICATION
1
9/10
74VHC74
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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10/10
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