E-TDA7333013TR [STMICROELECTRONICS]
SPECIALTY CONSUMER CIRCUIT, PDSO16, 4.40 MM, ROHS COMPLIANT, MO-15AB, TSSOP-16;
| 型号： | E-TDA7333013TR |
| 厂家： | 
ST |
| 描述： | SPECIALTY CONSUMER CIRCUIT, PDSO16, 4.40 MM, ROHS COMPLIANT, MO-15AB, TSSOP-16 光电二极管 商用集成电路 |
| 文件： | 总26页 (文件大小：356K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TDA7333
RDS/RBDS processor
Features
rd
■ 3 order high resolution sigma delta converter
for MPX sampling
■ Digital decimation and filtering stages
■ Demodulation of european radio data system
(RDS)
■ Demodulation of USA radio broadcast data
system (RBDS)
TSSO16
■ Automatic group and block synchronization
with flywheel mechanism
■ Error detection and correction
■ RAM buffer with a storage capacity of 24 RDS
blocks and related status information
■ Programmable interrupt source (RDS block
Description
TA)
2
The TDA7333 circuit is a RDS/RDBS signal
procesr, intended for recovering the inaudible
RDS/RBDS informations which are transmitted on
most FM radio broadcasting stations.
■ I C/SPI bus interface
■ Common quartz frequency 8.55 MHz or
8.664 MHz
■ 3.3 V power supply, 0.35 m CMOS
technology
Table 1.
Device summary
Ordecode(1)
Operating temp. range, °C
Package
Packing
-TDA7333
-40 to +85
-40 to +85
TSSOP16
TSSOP16
Tube
E-TDA7333013TR
Tape and reel
1. Devices in ECOPACK® package (see Section 5: Package information).
June 2008
Rev 1
1/26
www.st.com
1
Contents
TDA7333
Contents
1
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1
1.2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
2.2
2.3
2.4
Quick reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
General interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1
3.2
3.3
3.4
3.5
3.6
3.7
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Sigma delta converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Sinc4/16 decimation filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
RDS bandpass filter and inpolator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Group and block synchronization module . . . . . . . . . . . . . . . . . . . . . . . . 14
Programming through serial bus interface . . . . . . . . . . . . . . . . . . . . . . . . 15
3.7.1
.7.2
3.7.3
3.7.4
3.7.5
3.7.6
ds_int register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
rds_qu register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
rds_corrp register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
rds_bd_h register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
rds_bd_l register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
rds_bd_ctrl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.8
3.9
I2C transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.8.1
3.8.2
Write transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Read transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SPI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4
5
6
Application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2/26
TDA7333
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Quick Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
General interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
External pins alternate functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3/26
List of figures
TDA7333
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Transfer function of a 4 order sinc. filter, decimation factor is 16. . . . . . . . . . . . . . . . . . . 11
Magnitude response of sinc. 4/16 filter in RDS band . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Transfer function of RDS bandpass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Phase response of the RDS bandpass filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Demodulator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Group and block synchronization block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
rds_int register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
th
Figure 10. rds_qu register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11. rds_corrp register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12. rds_bd_h register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 13. rds_bd_l register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 14. rds_bd_ctrl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 15. I2C data transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 16. I2C write transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 17. I2C write operation example: write of rds_int and rds_bd_ctrl registers . . . . . . . . . . . . . . . 19
Figure 18. I2C read transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 19. I2C read access example 1: read of 5 bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 20. I2C read access example 2: read of 1 byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 21. SPI data transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 22. Write rds_int and rds_bd_ctrl registerSPI mode, reading RDS data and related flags 21
Figure 23. Read out RDS data and related flags, no update of rds_int and rds_bd_ctrl registers. . . . 22
Figure 24. Write rds_int registers in SPI mode, reading 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 25. TSSOP16 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4/26
TDA7333
Block diagram and pin description
1
Block diagram and pin description
1.1
Block diagram
Figure 1.
Block diagram
Cxti
Cxto
Cref
Cref
Cref
16pF
16pF
REF1 REF2 REF3
VDDA
1
VDDD
7
VSS
5
XTI
XTO
4
3
2
9
10
OSCILLATOR
MPX
SIGMA DELTA
converter
SINC4
filter
BANDPASS
filter
16
IRPOLATOR
Cmpx
sinc4reg
MPX
SCL_CLK
SDA_DATAIN
SA_DATAOUT
CSN
11
12
13
14
MPX
sdaout
sdain
sck
TEST LOGIC
&
PIN MUX's
RDS
I2C/SPI
intee
demodulator &
synchronisation
INTN
15
INTN
resetn
tm
6
8
TM
RESETN
1.2
Pin description
Figure 2.
Pin connection (top view)
VDDA
REF3
REF2
REF1
VSS
MPX
16
1
2
3
4
5
6
7
15 INTN
14 CSN
SA_DATAOUT
13
12
TDA7333
SDA_DATAIN
TM
11 SCL_CLK
VDDD
XTO
XTI
10
9
RESETN 8
5/26
Block diagram and pin description
TDA7333
Table 2.
Pin #
Pin description
Pin name
Function
1
2
3
4
5
VDDA
REF3
REF2
REF1
VSS
Analog supply voltage
Reference voltage 3 of A/D converter (2.65 V)
Reference voltage 2 of A/D converter (1.65 V)
Reference voltage 1 of A/D converter (0.65 V)
Common ground
Testmode selection (scan test).
Normal mode must be connected to gnd.
6
TM
7
VDDD
RESETN
XTI
Digital supply voltage
8
External reset input (active low)
Oscillator input
9
10
11
12
13
14
XTO
Oscillator output
SCL_CLK
Clock signal for I2C and SPI modes
SDA_DATAIN Data line in I2C mode, data input in SPI mode
SA_DATAOUT Slave address in I2C mode, datoutput in SPI mode
CSN
INTN
MPX
Chip select (1 = I2C mode=SPI mode)
Interrupt output (actlow), prog. at buff.not empty, buff. full, block A,B,D
,TA, TA EON
15
16
Multiplex input signal
6/26
TDA7333
Electrical specifications
2
Electrical specifications
2.1
Quick reference
Table 3.
Quick Reference
(Tamb = 25 °C, VDDA/VDDD = 3.3 V, f
= 8.55 MHz)
osc
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
DDA/VDDD
Analog/digital power supply
Operating temperature
3.0
-40
3.3
3.6
V
Tamb
+85
°C
8.55 or
8.664
fosc
Quartz frequency
MHz
Idd
Pd
Total supply current
10
33
mA
mW
Power dissipation
SRDS
VMPX
RDS input sensitivity
1
mVrms
mVrms
MHz
Input range of MPX signal
Maximum speed in SPI mode
Maximum speed in I2C mode
750
1
fSP
i
fi2c
400
kHz
2.2
Absolute maximum ratings
Table 4.
Symbol
Absolute maximum ratings
Parameter
Test conditions
Min.
Typ.
Max. Unit
VDD
Vin
3.3 V power supply ltages
Input voltae
-0.5
-0.5
4
V
V
V
V
5 V tolerant inputs
5.5
5.5
6
Vout
Vpeak
Output voltage
5 V tolerant output buffers in tri-state -0.5
Maximum peak voltage
23
General interface electrical characteristics
Table 5.
Symbol
General interface electrical characteristics
Parameter
Test conditions
Min.
Typ.
Max. Unit
Iil
Low level input current
High level input current
Vi = 0 V
Vi = VDD
1
1
1
3
µA
µA
µA
µA
Iih
Vo = 0 V or VDD
Vo = 5.5 V
Ioz
Tri-state output leakage
1
7/26
Electrical specifications
TDA7333
2.4
Electrical characteristics
Table 6.
Electrical characteristics
= -40 to +85 °C, V
T
/V
= 3.0 to 3.6 V, f = 8.55 MHz, unless otherwise specified
osc
amb
DDA DDD
V
and V
must not differ more than 0.15 V
DDD
DDA
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Supply (pin 1,5,7)
VDDD
VDDA
IDDD
IDDA
Pd
Digital supply voltage
Analog supply voltage
Digital supply current
Analog supply current
Total power dissipation
3.0
3.0
3.3
3.3
2
3.6
3.6
V
V
mA
mA
mW
8
33
Digital inputs (pin 6,8,11,12,13,14)
Vil
Low level input voltage
High level input voltage
0.8
V
V
Vih
2.0
1.0
Low level threshold input
falling
Vilhyst
1.15
V
High level threshold input
rising
Vihhyst
Vhst
1.5
0.4
1.7
0.7
V
V
Schmitt trigger hysteresis
Digital outputs (pin 12,13,15) are open drains
Open drain, depends on external
circuitry
Voh
Vol
High level output voltage
Low level output ltage
VDDD
0.4
V
V
Iol = 4 mA, takes into account
200 mV drop in the supply voltage
Analog inputs (pin 16)
VMPX
SRDS
RMPX
nput range of MPX signal
0.75
Vrms
mVrms
Ohm
RDS detection sensitivity
1
Input Impedance of MPX pin
55k
Crystal parameters
8.55 or
8.664
fosc
Quartz frequency
MHz
tsu
gm
Start up time
10
ms
A/V
pF
Transconductance
0.0006
Cxti,Cxto Load capacitance
16
8/26
TDA7333
Table 6.
Electrical specifications
Electrical characteristics (continued)
= -40 to +85 °C, V /V = 3.0 to 3.6 V, f = 8.55 MHz, unless otherwise specified
osc
T
amb
DDA DDD
V
and V
must not differ more than 0.15 V
DDD
DDA
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
MHz
dB
Sigma delta modulator
Fs
Sample rate
fosc = 8.55 MHz
4.275
38
OVR
Oversampling ratio
f = 57 kHz
Relative total harmonic dist.
plus noise
BW = 54.5 to 59.5 kHz,
unweigted, Vrds = 3 mVrms
THD+N
27
Sinc4/16 decimation filter
fs
Decimated sample rate
fosc = 8.55 MHz
267.2
-2.6
0
kHz
dB
A57
Attenuation at 57 kHz
Attenuation difference
BW = 54.5 to 59.5 kHz
dB
Bandpass filter
fs
fp
Sample rate
fosc = 8.55 MHz
267.2
kHz
kHz
dB
Pass-band frequencies
Pass-band ripple
55.6
-0.5
53.0
58.4
+0.5
61
Rp
fstop
Rs
Mi
Stop-band corner frequencies
Stop-band attenuation
Interpolation factor
kHz
dB
-43
32
I2C
fI2C
SPI
Clock frequency in I2C mode
400
1
kHz
fSPI
tch
tcl
Clock frequency in SPI mode
Clock high time
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
450
450
500
500
Clock low time
tcsu
tcsh
todv
toh
td
Chip select setup time
Chip select hold
Output data valid
Output hold
250
0
Deselect time
1000
200
200
tsu
th
Data setup time
Data hold time
9/26
Functional description
TDA7333
3
Functional description
3.1
Overview
The new RDS/RBDS processor contains all RDS/RBDS relevant functions on a single chip.
It recovers the inaudible RDS/RBDS information which are transmitted on most FM radio
broadcasting stations.
rd
Due to an integrated 3 order sigma delta converter, which samples the MPX signal, all
further processing is done in the digital domain and therefore very economical. After filtering
the highly oversampled output of the A/D converter, the RDS/RBDS demodulator extracts
the RDS DataClock, RDS Data Signal and the Quality information. A next RDS/RBDS
decoder will synchronize the bitwise RDS stream to a group and block wise information.
This processing includes an error detection and error correction algorithm. In addition, an
automatic flywheel control avoids exhaustive data exchange between the RDS/RBDS
processor and the host.
The device operates in accordance with the EBU (European Broadcsting Union)
specifications.
3.2
3.3
Sigma delta converter
rd
The sigma delta modulator is a 3 order (second order-first order cascade) structure.
Therefore a multibit output (2 bit streams) rpresents the analog input signal. A next digital
noise canceller will take the 2 bit streaand calculates a combined stream which is then
fed to the decimation filter. The modulator works at a sampling frequency of XTI/2. The
oversampling factor in relation to the band of interest (57 kHz 2.4 kHz) is 38.
Sinc4/16 decimation filter
The oversampled data delivered from the modulator are decimated by a value of 16 with a
th
4 order Sinc Filter.
rd
This is considered to be the optimum solution for high decimation factors and for a 3 order
sigma delta modulator.
The architecture is a very economical implementation because digital multipliers are not
required. It is implemented by cascading 4 integrators operating at full sampling rate (XTI/2)
followed by 4 differentiates operating at the reduced sampling rate (XTI/2/16). Also wrap
around logic is allowed and the internal overflow will not affect the output signal as long as a
minimum required bit width is maintained.
The transfer function of this Sinc4/16 filter is:
K
–M
⎛
⎜
⎝
⎞
⎟
⎠
1 1 – z
------------------------
H(z) =
M
–1
1 – z
with K = 4, M = 16
10/26
TDA7333
Functional description
and its frequency response is:
K
Mω
⎛
⎝
⎞
⎠
⎛
⎜
⎜
⎜
⎝
⎞
⎟
⎟
⎟
⎠
--------
sin
2
1
M
jω
H(e ) =
---------------------------
ω
⎛ ⎞
---
sin
⎝ ⎠
2
with
f
fs
----
ω = 2π
th
Figure 3.
Transfer function of a 4 order sinc. filter, decimation factor is 16.
Sinc4/16 Transfer Function
0
10
20
30
40
50
60
70
80
90
100
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
6
Frequency [Hz]
x 10
Figure 4.
Magnitude response of sinc. 4/16 filter in RDS band
Sinc4/16 Transfer Function (RDS Band)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.4
5.5
5.6
5.7
5.8
5.9
6
4
Frequency [Hz]
x 10
11/26
Functional description
TDA7333
3.4
RDS bandpass filter and interpolator
th
The 8 order digital RDS bandpass filter is of type Tschebyscheff and centered at 57 kHz.
With linear phase characteristics in the passband and approximately flat group delay it
guarantees best filter function of the RDS and ARI signal. Four biquads are cascaded
working at a common sampling frequency of XTI/2/16.
Figure 5.
Transfer function of RDS bandpass filter
Transfer Function of RDS Filter
10
0
10
20
30
40
50
60
70
80
90
100
4
4.5
5
5.5
Frequeny [Hz]
6
6.5
7
x 104
Figure 6.
Phase response of the RDS bandpass filter
Phase of RDS Filter
3
2
0
1
2
3
5.6
5.65
5.7
5.75
5.8
4
Frequency [Hz]
x 10
The output sample of the bandpass filter is picked up from a linear interpolator with sinc2
characteristics. The interpolation factor is 32. A zero cross detection is simply formed by
taking the sign bit of the interpolated signal. This signal which contains only phase
informations is processed by the RDS Demodulator.
12/26
TDA7333
Functional description
3.5
Demodulator
The demodulator includes:
●
●
●
●
RDS quality indicator with selectable sensitivity
Selectable time constant of 57 kHz PLL
Selectable time constant of bit PLL
time constant selection done automatically or by software
Figure 7.
Demodulator block diagram
MPX
Input-stage
ARI-indicator
frequency
offset comp.
57 kHz PLL
(digital Filter)
Sine comp.
Cosine comp.
mclk
Clock Generator
mclk
(8,550 or 8,664 MHz)
to RDS group and block synchronisation
module:
1187.5Hz
PLL
RDS Data
Extractor
RD
RDSDAT
RDSQUAL
Half Wave
Integrator
Half Wave
Extractor
RDS Quality
Extractor
from RDS group and block synchronisation
module:
AR_RES
The demodulator is fed by the 57 kHz bandpass filter and interpolated multiplex signal. The
input signal passes a digital filter extracting the sinus and cosinus components, to be used
for further processing.
The sign of bh channels are used as input for the ARI indicator and for the 57 kHz PLL.
A fast ARI indicator determines the presence of an ARI carrier. If an ARI carrier is present,
the 57 kHz PLL is operating as a normal PLL, else it is operating as a Costas loop.
One part of the PLL is compensating the integral offset (frequency deviation between
oscillator and input signal).
One channel of the filter is fed into the half wave integrator. Two half waves are created, with
a phase deviation of 90 degrees. One wave represents the RDS component, whereas the
other wave represents the ARI component. The sign of both waves are used as reference
for the bit PLL (1187.5 Hz).
The RDS wave is then fed into the half wave extractor. This leads into an RDS signal, which
after integration and differential decoding represents the RDS data.
In a similar way a quality bit can be calculated. This is useful to optimize error correction.
The module needs a fixed clock of 8.55 MHz. Optionally an 8.664 MHz clock may be used
by setting the corresponding bit in rds_bd_ctrl register (see Chapter 3.7.6).
In order to optimize the error correction in the group and block synchronization module, the
sensitivity level of the quality bit can be adjusted in three steps (see Chapter 3.7.6). Only
13/26
Functional description
TDA7333
bits marked as bad by the quality bit are allowed to be corrected in the group and block
synchronization module. Thus the error correction is directly influenced by this setup.
The time constant of the 57 kHz PLL and the 1187.5 Hz PLL may be influenced by software
(see Chapter 3.7.6).
This is useful in order to achieve a fast synchronization after a program resp. frequency
change (fast time constant) and to get a maximum of noise immunity after synchronization
(slow time constant).
The user may choose between 2 possibilities via bit rds_bd_ctrl[1] (see Chapter 3.7.6):
1. Hardware selected time constant - In this case both pll time constants are reset to the
fastest one with a reset from the group and block synchronization module. If the
software decides to re synchronize, it generates a reset. Both PLL are set to the fastest
time constant, which is automatically increased to the slowest one. This is done in four
steps within a total time of 215.6 ms (256 RDS clocks).
2. Software selected time constant - In this case the time constant of both PLL can be
selected individually by software.PLL time constants can be set independently.
3.6
Group and block synchronization module
The group and block synchronization module has the following features:
●
●
●
●
●
●
Hardware group and block synchronization
Hardware error detection
Hardware error correction using quality bit information of the demodulator
Hardware synchronization flywheel
TA information extraction
reset by software (ar_res)
Figure 8.
Group and block synchronization block diagram
Group & Block Synchronization Control Block
RDSCLK
RDSDAT
RDSQAL
next
RDS
bit
new
Block
available
from RDS
Demodulator
Block
missed
bit_int
int
set
rds_corrp
read only
rds_qu
rds_int
rds_bd_h,rds_bd_l
read only
set
read only
read/write
RDSDAT(15:0)
Q(3:0)
res
QU(0:3)
CP(9:5)
Syndrome register
S(9:0)
S(4:0)
Correct. pat.
Correction
logic
Corrected
Data_OK
Syndrom zero
Quality bit counter
RDS block counter
ABH
DBH
BLOCKE detected
BLOCK A
BLOCK B
BLOCK D
AR_RES
TAEON
TA
14/26
TDA7333
Functional description
This module is used to acquire group and block synchronization of the received RDS data
stream, which is provided in a modified shortened cyclic code. For the theory and
implementation of the modified shortened cyclic code, please refer to the specification of the
radio data system (RDS) EN50067.
It further detects errors in the data stream. Depending on the quality bit information of the
demodulator an error correction is made.
The RDS data bytes are available to the software together with status bits giving an
indication on the reliability of the data.
It also extracts TA information which can be used as interrupt source (see Chapter 3.7.1).
3.7
Programming through serial bus interface
The serial bus interface is used to access the different registers of the chip. It is able to
2
handle both I C and SPI transfer protocols, the selection between the two modes is done
thanks to the pin CSN:
2
●
if the pin CSN is high, the interface operates as an I C bus.
●
if the pin CSN is asserted low, the interface operates as a SPI bus.
In both modes, the device is a slave, i.e the clock pin SCL_CLK is only an input for the chip.
Depending on the transfer mode, external pins have alternate functions as following:
Table 7.
External pins alternate funcons
Function in SPI ode (CSN =0)
Pin
Function in I2C mode (CSN=1)
SCL_CLK
CLK (serial clock)
SCL (serial clock)
SDA (data line)
SDA_DATAIN
DATAIN (data input)
SA_DATAOUT
DATAOUT (data output)
SA (slave address)
Eight registeare available with read or read/write access rights as the following:
Table 8.
Registers description
Access
Register
Function
rights
rds_int[7:0] (see 3.7.1)
read/write
read
Interrupt source setting, sync., bne information
Quality counter, actual block name
rds_qu[7:0] (see 3.7.2)
rds_corrp[7:0] (see 3.7.3)
rds_bd_h[7:0] (see 3.7.4)
rds_bd_l[7:0] (see 3.7.5)
rds_bd_ctrl[7:0] (see 3.7.6)
sinc4reg[7:0]
read
Error correction status, buffer ovf information
High byte of current RDS block
read
read
Low byte of current RDS block
read/write
read/write
read/write
Frequency, quality sensitivity, demodulator pll settings
Sinc4 filter settings (for internal use only)
Test modes (for internal use only)
testreg[7:0]
The meaning of each bit is described below:
15/26
Functional description
TDA7333
3.7.1
rds_int register
Figure 9.
rds_int register
rds_int
reset value
bit name
access
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
0
0
0
0
0
0
0
0
interrupt bit. It is set to one on every programmed interrupt. It
is reset by reading rds_int register.
write bne ar_res synch itsrc2 itsrc1 itsrc0 int
r/w
r
r/w
r
r/w r/w r/w
r
interrupt source
itsrc[2:0] select the interrupt source
(1)
synchronization information.
1: the module is already synchronized.
0: the module is synchronizing
It is used to force a resynchronization. If it is set to one, the
RDS modules are forced to resynchronization state.
The bit is automatically reset. So it is always read as zero.
RDS block.
if 1, one block has been detected
rds_int and rds_bd_ctrl write order (when in SPI mode
)
1: rds_int and rds_bd_ctrl are updawith data shifted in.
0: rds_int and rds_bd_ctrl are nupdated.
(1)
interrupt source i
no interrupt
RDS Block
block A
tsrc2
itsrc1
itsrc0
0
0
0
1
1
1
1
0
0
1
0
0
1
1
0
1
1
0
1
0
1
Note : when changing the interrupt mode, one has to
perform a reseof the module (i.e set the bit “ar_res” at
one)
block B
block D
TA
TAEON
3.7.2
rds_qu register
Figure 10. rds_qu register
bit 7
it 6
0
bit 5
0
bit 4
0
bit 3
0
bit 2
0
bit 1
bit 0
0
rds_qu
reset value
bit
access
0
qu3
r
qu2
r
qu1
r
qu0
r
blk1
r
blk0
r
e
r
synz
r
It indicates if the error correction was successfull.
1: the syndrome was zero after the error correction.
0: the syndrome did not become zero and therefore the
correction was not successfull.
1: a block E is detected.This indicates a paging block
which is defined in the RBDS specification used in the
united states of America.
0: an ordinary RDS block A, B, C, c·or D is detected, or no
valid syndrome was found.
bit 0 of block counter (2)
bit 1 of block counter (2)
bit 0 of quality counter (3)
bit 1 of quality counter (3)
bit 2 of quality counter (3)
bit 3 of quality counter (3)
(2)
block name
block A
blk1
blk0
0
0
1
1
0
1
0
1
(3) qu[3..0] is a counter of the quality bit information coming
from the RDS demodulator. It is counting the number of bits
which are marked as bad by the demodulator. Only those bits
are allowed to be corrected. Thus the quality bit counter indi-
cates the maximum possible number of bits being corrected.
block B
block C,C’
block D
16/26
TDA7333
Functional description
3.7.3
rds_corrp register
Figure 11. rds_corrp register
rds_comp bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
reset value
bit name
access
0
0
0
0
0
0
0
0
cp9 cp8 cp7 cp6 cp5
correct data_ok
-
r
r
r
r
r
r
r
r
It is an information about a correct syndrome after recep-
tion resp. after an error correction routine.
1: a correct syndrome was detected.
0: the syndrome was wrong. The current RDS data cannot
be used.
It is an information about error correction.
1: an error correction was made.
0: the actual RDS block is detected as error free.
bit 5 of the syndrome register(*)
bit 6 of the syndrome register(*)
bit 7 of the syndrome rgister(*
bit 8 of the syndrome egister(*)
bit 9 of the synme register(*)
(*) (refer to: pecification of the radio data system EN50067
of CNELEC, ANNEX B). When bits 4...0 of the syndrome
regir are all zero a possible error burst is stored in this
bits. With the help of the correction pattern(bits 9..5 of the
syndrome register), the type of error can be measured in or-
der to classify the reliability of the correction.
3.7.4
rds_bd_h register
Figure 12. rds_bd_h register
0
bit 6
0
bit 5
0
bit 4
0
bit 3
0
bit 2
0
bit 1
0
bit 0
0
rds_ bd_h
reset alue
bit name
m15
r
m14
r
m13 m12
m11
r
m10
r
m9
r
m8
r
r
r
access
bit 15 of the actual RDS 16bits information
bit 14 of the actual RDS 16bits information
bit 13 of the actual RDS 16bits information
bit 12 of the actual RDS 16bits information
bit 11 of the actual RDS 16bits information
bit 10 of the actual RDS 16bits information
bit 9 of the actual RDS 16bits information
bit 8 of the actual RDS 16bits information
17/26
Functional description
TDA7333
3.7.5
rds_bd_l register
Figure 13. rds_bd_l register
bit 7
0
bit 6
0
bit 5
0
bit 4
0
bit 3
0
bit 2
0
bit 1
0
bit 0
0
rds_bd_I
reset value
m7
r
m6
r
m5
r
m4
r
m3
r
m2
r
m1
r
m0
r
bit name
access
bit 7 of the actual RDS 16bits information
bit 6 of the actual RDS 16bits information
bit 5 of the actual RDS 16bits information
bit 4 of the actual RDS 16bits information
bit 3 of the actual RDS 16bits information
bit 2 of the actual RDS 16bits information
bit 1of the actual RDS 16bits information
bit 0 of the actual RDS 16bits information
3.7.6
rds_bd_ctrl register
Figure 14. rds_bd_ctrl register
rds_bd_ctrl bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
0
0
0
0
0
0
0
1
reset value
bit name
access
freq qsens1qsens0 pllb1 pllb0 pllf shw
r/w r/w r/w r/w r/w r/w r/w
-
select PLL’s time constants by software or hardware:
1: software. Time constants are selected by pllb[1:0] resp.
pllf
0: hardware. (reset value) Time constants automatically
increase after a reset.
set the 57kHz pll time constant (1)
bit 0 of 1187.5Hz pll time constant (2)
bit 1 of 1187.5Hz pll time constant (2)
bit 0 of quality sensitivity (3)
bit 1 of quality sensitivity (3)
select oscillator frequency:
1: 8.664MHz
(1)
0: 8.55MHz (reset value)
pllf
lock time needed for 90 deg deviation
0
1
2 ms
10 ms
(3)
select sensitivity of quality bit.
00: minimum (reset value)
(2)
lock time needed for 90 deg deviation
11: maximum
pllb1 pllb0
0
0
1
1
0
1
0
1
5 ms (reset status)
15 ms
35 ms
76 ms
Note:
Sinc4reg and testreg are reserved registers dedicated to testing and evaluation.
18/26
TDA7333
Functional description
3.8
I2C transfer mode
This interface consists of three lines: a serial data line (SDA), a bit clock (SCL), and a slave
address select (SA).
The interface is capable of operating in fast mode (up to 400kbits/s) but also at lower rates
(<100kbits/s).
Data transfers follow the format shown in Figure 15. After the START condition (S), a slave
address is sent. The address is 7 bits long followed by an eighth bit which is a data direction
bit (R/_W).
A ’zero’ indicates a transmission (WRITE), a ’one’ indicates a request for data (READ).
The slave address of the chip is set to 001000S, where S is the least significant bit of the
slave address set externally via the pin SA_DATAOUT. This allows to choose between two
addresses in case of conflict with another device of the radio set.
Each byte has to be followed by an acknowledge bit (SDA low).
Data is transferred with the most significant (MSB) bit first.
A data transfer is always terminated by a stop condition (P) gerated by the master.
Figure 15. I2C data transfer
SDA
SCL
1-7
8
9
1-7
8
1-7
8
9
9
S
P
START
ADDRESS
R/W
ACK
DATA
ACK
DATA
STOP
ACK/ACK
CONDITION
CONDITION
3.8.1
Write transfe
Figure 6. I2C write transfer
rds_bd_ctrl
S
Slave address
W
A
rds_int
A
A
sinc4reg
A
testreg
A
P
S = start condition
W = write mode
Slave address = 001000S ( where S is the level of the pin
from master to slave
from slave to master
SA_DATAOUT)
A = acknowledge bit
P = stop condition
Figure 17. I2C write operation example: write of rds_int and rds_bd_ctrl registers
SA
0
1
CSN
SDA
rds_int[7:0]
rds_bd_ctrl[7:0]
SCL
P
S
SLAVE ADDRESS
W
ACK
ACK
ACK
STOP
START
CONDITION
CONDITION
19/26
Functional description
TDA7333
3.8.2
Read transfer
Figure 18. I2C read transfer
S
Slave address
R
A
rds_int
A
rds_qu
A
testreg
A
P
S = start condition
R = read mode
Slave address = 001000S ( where S is the level of the pin
SA_DATAOUT)
from master to slave
from slave to master
A = acknowledge bit
P = stop condition
Eight bytes can be read at a time (please refer to Section 3.7 for the meaning of each bit).
The master has always the possibility to read less than eight registers by not sending the
acknowledge bit and then generating a stop condition after having read the needed amount
of registers.
There are two typical read access:
●
read only the first register rds_int to check the interrupt bit.
●
read the first five registers rds_int, rds_qu, rds_corrp, rds_bd_h, rds_bd_l to get the
RDS data
The registers are read in the following order: rds_int, rds_qu, rds_corrp, rds_bd_h,rds_bd_l,
rds_bd_ctrl, sinc4reg, testreg.
Figure 19. I2C read access examp: read of 5 bytes
SA
0
1
CSN
SDA
rds_int[7:0]
rds_qu[7:0]
rds_corrp[7:0]
rds_bd_h[7:0]
rds_bd_l[7:0]
SCL
P
S
AVE ADDRESS
R
ACK
ACK
ACK
ACK
ACK
ACK
START
STOP
CO
CONDITION
Figure 20. I2C read access example 2: read of 1 byte
SA
0
1
CSN
SDA
rds_int[7:0]
SCL
P
S
SLAVE ADDRESS
R
ACK
ACK
STOP
START
CONDITION
CONDITION
20/26
TDA7333
Functional description
3.9
SPI mode
Figure 21. SPI data transfer
CSN
t
d
t
csu
t
su
tcsh
th
t
odv
t
oh
tcl tch
2
1
3
4
5
6
7
8
63
64
CLK
rds_int[1] rds_int[0]
testreg[1] testreg[0]
DATAIN
rds_int[7] rds_int[6] rds_int[5] rds_int[4] rds_int[3] rds_int[2] rds_int[1] rds_int[0]
DATAOUT
shift of DATAIN
in shiftregister
update of
shiftregister with
registers content
update oregsters
with shifregister
content if requested
This interface consists of four lines. A serial data input (DATAIN), a serial data output
(DATAOUT), a chip select input (CSN) and a bit clock input (CLK).
The chip select input signals the begin and end of the data trasfer. If the data transfer
starts, at each
bit clock one bit is clocked out via the serial data output and one bit is clocked in via the
serial data input.
When chip enable signals the begin of the data transfer the internal 64 bits shift register is
updated with the current registers cont of the V324.
When chip enable signals the end of the data transfer the registers with write access can be
updated with the bits which have been last shifted in.
The last byte on DATAIN input is always rds_int[7:0] and the former last one is
rds_bd_ctrl[7:0]. In other words, the master has to take in account the amount of bytes
transmitted wheintending to perform a write operation so that the last two bytes sent on
DATAIN are r_bd_ctrl[7:0] and rds_int[7:0].
If the update of both rds_int and rds_bd_ctrl registers is actually taking place depends on
the MSB of rds_int, i.e. rds_int[7] = 0 - no update, rds_int[7] = 1 update of both registers.
Hereafter you can find typical read/write access in SPI mode:
Figure 22. Write rds_int and rds_bd_ctrl registers in SPI mode, reading RDS data
and related flags
CSN
CLK
rds_bd_ctrl[7:0]
rds_bd_h[7:0]
{1,rds_int[6:0]}
rds_bd_l[7:0]
DATAIN
rds_int[7:0]
rds_qu[7:0]
rds_corrp[7:0]
DATAOUT
21/26
Functional description
TDA7333
Figure 23. Read out RDS data and related flags, no update of rds_int and
rds_bd_ctrl registers
CSN
CLK
{0,x,x,x,x,x,x,x}
rds_bd_l[7:0]
DATAIN
rds_int[7:0]
rds_qu[7:0]
rds_corrp[7:0]
rds_bd_h[7:0]
DATAOUT
Figure 24. Write rds_int registers in SPI mode, reading 1 register
CSN
CLK
{1,rds_int[6:0]}
DATAIN
rds_int[7:0]
DATAOUT
The content of the rds registers is clocked out on DATAOUT pin in the following order:
rds_int[7:0], rds_qu[7:0], rds_corrp[7:ds_bd_l[7:0], rds_bd_h[7:0], rds_ctrl[7:0],
sinc4reg[7:0], testreg[7:0]
For the meaning of the single bits please refer to the Section 3.7.
Note:
After 40 bit clocks the whole RDS data and flags are clocked out.
22/26
TDA7333
Application notes
4
Application notes
A typical rds data transfer could work like this:
1. The micro sets the interrupt source to “RDS block” interrupt by setting itsrc[2:0] to 001.
2. The micro continuously checks the rds_int[7:0] bits for the first interrupt (rds_int[0] goes
high). If there is no interrupt it stops the transfer after these 8 bits. No update of the
rds_int[7:0] is performed.
3. Once there is an interrupt detected the micro will also clock out all the other RDS bits
(rds_qu[7:0], rds_corrp[7:0], rds_bd_h[7:0], rds_bd_l[7:0]).
4. The next interrupt can not be expected before 22ms.
The above example is working by polling the rds_int[0] bit. An easier and better application
is possible by checking the RDS interrupt pin INTN (see below) and starting the transfer only
when this interrupt is present.
The output pin INTN acts as an interrupt pin. The source of interrupt is rogrammable
through the register rds_int (see Section 3.7.1), the value on the pin the inverted value of
the bit rds_int[0] (i.e this interrupt pin is active low). With the hp of this pin an interrupt
driven request of the rds data is possible (the external processor only starts the transfer if an
interrupt is active).
23/26
Package information
TDA7333
5
Package information
In order to meet environmental requirements, ST (also) offers these devices in ECOPACK®
packages. ECOPACK® packages are lead-free. The category of second Level Interconnect
is marked on the package and on the inner box label, in compliance with JEDEC Standard
JESD97. The maximum ratings related to soldering conditions are also marked on the inner
box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 25. TSSOP16 mechanical data and package dimensions
mm
inch
DIM.
OUTLINE AND
MECHANICAL DATA
MIN. TYP. MAX. MIN.
1.200
TYP. MAX.
0.047
A
A1
A2
b
0.050
0.150 0.002
0.006
0.800 1.000 1.050 0.031 0.039 0.041
0.190
0.090
0.300 0.007
0.200 0.005
0.012
0.009
c
D (1) 4.900 5.000 5.100 0.114 0.118 0.122
6.200 6.400 6.600 0.244 0.252 0.260
E1 (1) 4.300 4.400 4.500 0.170 0.173 0.177
E
e
L
0.650
0.450 0.600 0.750 0.018 0.024 0.030
1.000 0.039
0.02
L1
k
0˚ (min.) 8˚ (max.)
0.100
aaa
0.004
TSSOP16
Note: 1. D d E1 does not include mold flash or protrusions.
Mlash or potrusions shall not exceed 0.15mm
.006inch) per side.
(Body 4.4mm)
0080338 (Jedec MO-153-AB)
24/26
TDA7333
Revision history
6
Revision history
Table 9.
Date
25-Jun-2008
Document revision history
Revision
Changes
1
Initial release.
25/26
TDA7333
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Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
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