L9822N013TR [STMICROELECTRONICS]

BUF OR INV BASED PRPHL DRVR, PDSO20, POWER, SO-20;


型号：	L9822N013TR
厂家：	ST
描述：	BUF OR INV BASED PRPHL DRVR, PDSO20, POWER, SO-20 驱动 CD 光电二极管接口集成电路
文件：	总9页 (文件大小：745K)
中文：	中文翻译
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L9822N

OCTAL SERIAL SOLENOID DRIVER

MULTIPOWER BCD TECHNOLOGY

EIGHT LOW R_DSonDMOS OUTPUTS

(0.5Ω AT I_O= 1A @ 25°C V_CC= 5V± 5%)

8 BIT SERIAL INPUT DATA (SPI)

8 BIT SERIAL DIAGNOSTIC OUTPUT FOR

OVERLOAD AND OPEN CIRCUIT CONDITIONS

OUTPUT SHORT CIRCUIT PROTECTION

CHIP ENABLESELECT FUNCTION (active low)

INTERNAL 35V CLAMPING FOR EACH OUT-

PUT

CASCADABLE WITH ANOTHER OCTAL

DRIVER

LOW QUIESCENT CURRENT (10mA MAX.)

PACKAGE Power SO20

PowerSO20

ORDERING NUMBER: L9822N

automotive environment. The DMOS outpts

L9822N has a very low power consumption.

DESCRIPTION

Data is transmitted serially to the device using the

Serial Peripheral Interface (SPI) protocol.

The L9822N is an octal low side solenoid driver

rea lized in Multipower-BCD technology particularly

suited for driving lamps, relays and solenoids in

The L9822N features the outputs status monitoring

function.

BLOCK DIAGRAM

October 2003

1/9

L9822N

PIN CONNECTIONS (top view)

GND

V_CC

SCLK

RESET

OUT7

OUT6

OUT5

OUT4

N.C.

OUT0

OUT1

OUT2

OUT3

N.C.

GND

D94AT119A

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Value

Unit

V_CC

V_O

I_I

DC Logic Supply

Output Voltage

– 0.7

Input Transient Current

(CE, SI, SCLK, RESET, SO) :

Duration Time t = 1s,

V_I< 0

– 25

– 40

V_I> V_CC

+ 25

150

T_j, T_stg

Junction and Storage Temperature Range

THERMAL DATA

Symbol

Parameter

Value

1.5

Unit

R_{th j-case}

R_{th j-amb}

Thermal Resistance Junction-Case

Thermal Resistance Junction-Ambient

Max.

C/W

2/9

L9822N

PIN DESCRIPTION

V_CC

ticular output is high. A low on this pin for a data bit

indicates that the output is low.

Logic supply voltage - nominally 5V

Comparing the serial output bits with the previous

serial input bits the external microcontroller imple-

ments the diagnostic data supplied by the L9822.

GROUND

Device Ground. This ground applies for the logic cir-

cuits as well as the power output stages.

RESET

Serial Input. This pin is the serial data input. A high

on thispinwill programaparticularoutput tobeOFF,

while a low will turn it ON.

Asynchronous reset for the output stages, the par-

allel latch and the shift register inside the

L9822NSP. This pin is active low and it must not be

left floating. A power on clear function may be im-

plemented connecting this pin to V_CCwith an exter-

nal resistor and to ground with an external capacitor.

SCLK

Serial Clock. This pin clocks the shift register. New

SO data will appear on every rising edge of this pin

and new SI data will be latched on every SCLK’sfall-

ing edge into the shift register.

Chip Enable. Data is transferred from the shift reg-

isters to the outputs on the rising edge of this signal.

The falling edge of this signal sets the shift register

with the output voltage sense bits coming from the

output stages. The output driver for the SOpin isen-

abled when this pin is low.

OUTPUTS 00-07

Power output pins. The input and output bits corres-

ponding to 07 are sent and received first via the SPI

bus and 00 is the last.

The outputs are provided with current limiting and

voltage sense functions for fault indication and pro-

tection. The nominal load current for these outputs

is 500mA. The outputs also have on board clamps

set at about 36V for recirculation of inductive load

current.

Serial Output. This pin is the serial output from the

shift register and it is tri-stated when CE is high. A

high for a data bit on this pin indicates that the par-

ELECTRICAL CHARACTERISTICS (V_CC= 5V ± 5%. T_j= – 40 to 125°C ; unless otherwise speciifed)

Symbol

V_OC

Parameter

Test Conditions

I_O= 0.5A, Output Programmed OFF

I_O= 0.5A, When ON

Min.

Typ.

Max.

Unit

Output Clamping Volt.

Out. Clamping Energy

Out. Leakage Current

On Resistance

E_OC

I_OFF

V_O= 24V, Output Progr. OFF

R_DSon

Output Progr. ON

_O= 0.5A

_O= 0.75A

_O= 1A

0.53

Ω

With Fault Reset Disabled

t_PHL

t_P

V_OREF

t_UD

Turn-on Delay

I_O= 500mA

No Reactive Load

Turn-off Delay

I_O= 500mA

No Reactive Load

Fault Refer. Voltage

Output Progr. OFF

Fault detected if V_O> V_OREF

1.6

Fault Reset Delay

(after CE L to H

transition)

See fig. 3

250

V_OFF

Output OFF Voltage

Output Pin Floating.cOutput Progr. OFF,

1.0

3/9

L9822N

ELECTRICAL CHARACTERISTICS (Continued)

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

INPUT BUFFER (SI, CE, SCLK and RESET pins)

V_T–

V_T+

Threshold Voltage at

Falling Edge

0.2V_CC

Threshold Voltage at

Rising Edge

0.7V_CC

V_H

I_I

Hysteresis Voltage

Input Current

V_T+– V_T–

1.45

V_CC= 5.25V, 0 < V_I< V_CC

0 < V_I< V_CC

– 10

+ 10

C_I

Input Capacitance

OUTPUT BUFFER (SO pin)

V_SOL

V_SOH

Output LOW Voltage

Output HIGH Voltage

I_O= 1.6mA

I_O= 0.8mA

0.4

V_CC

– 1.3V

I_SOtl

C_SO

I_CC

Output Tristate Leakage 0 < V_O< V_CC, CE Pin Held High,

– 10

Current

V_CC= 5.25V

Output Capacitance

0 < V_O< V_CC

CE Pin Held High

Quiescent Supply

Current at V_CCPin

All Outputs Progr. ON. I_O= 0.5A

per Output Simultaneously

SERIAL PERIPHERAL INTERFACE (see fig. 2, timing diagram)

f_op

t_lead

t_lag

Operating Frequency

Enable Lead Time

Enable Lag Time

Clock HIGH Time

Clock LOW Time

Data Setup Time

Data Hold Time

D.C.

250

200

MHz

t_wSCKH

t_wSCKL

t_su

t_H

t_EN

Enable Time

250

100

t_DIS

t_V

Disable Time

Data Valid Time

Rise Time (SO output)

Fall Time (SO output)

t_rSO

t_fSO

t_rSI

V_CC= 20 to 70% C_L= 200pF

V_CC= 70 to 20% C_L= 200pF

V_CC= 20 to 70% C_L= 200pF

Rise Time SPI

200

Inputs (SCK, SI, CE)

t_fSI

t_ho

Fall Time SPI

Inputs (SCLK, SI, CE)

V_CC= 70 to 20% C_L= 200pF

200

Output Data Hold Time

4/9

L9822N

FUNCTIONAL DESCRIPTION

The L9822N DMOS output is a low operating power

device featu-ring, eight 1Ω R_DSONDMOS drivers

with transient protection circuits in output stages.

Each channel is independently controlled by an out-

put latch and a common RESET line which disables

all eight outputs. The driver has low saturation and

short circuitprotection and can drive inductive and re-

sistive loads such as solenoids, lamps and relais.

Data is transmitted to the device serially using the

Serial Peripheral Interface (SPI) protocol. The circuit

receives 8 bit serial data by means of the serial input

(SI) which is stored in an internal register to control

the output drivers. The serial output (SO) provides 8

bit of diagnostic data representing the voltage level

at the driver output. This allows the microprocessor

to diagnose the condition of the output drivers.

Individual registers in the latch may be cleared by

fault conditions in order to protect the overloaded

output stages. The entire latch may also be cleared

by the RESET signal.

Output Stages

The output stages provide an active low drive signal

suitable for 0.75A continuous loads. The outputs

have internal zeners set to 36 volts to clamp induc-

tive transients at turn-off. Each output also has a

voltage comparator observingthe outputnode.Ifthe

voltage exceeds 1.8V on an ON output pin, a fault

condition is assumed and the latch driving this par-

ticular stage is reset, turning the output OFF to pro-

tect it. The timing of this action is described below.

These comparators also provide diagnostic feed-

back data to the shift register. Additionally, the com-

parators contain an internal pulldown current which

will cause the cell to indicate a low output voltage if

the output is programmed OFF and the output pin

is open circuited.

The output saturation voltage is monitored by a

comparator for an out of saturation condition and is

able to unlatch the particular driver through the fault

reset line. This circuit is also cascadable with an-

other octal driver in order to jam 8 bit multiple data.

The device is selected when the chip enable (CE)

line is low.

TIMING DATA TRANSFER

Figure #2 shows the overall timing diagram from a

byte transfer to and from the L9822NSP using the

SPI bus.

Additionally the (SO) is placed in a tri-state mode

when the device is deselected. The negative edge

of the (CE) transfers the voltage level of the drivers

to the shift register and the positive edge of the (CE)

latches the new data from the shift register to the

drivers. When CE is Low, data bit contained into the

shift register is transferred to SO output at every

SCLK positive transition while data bit present at SI

input is latched into the shift register on every SCLK

negative transition.

CE High to Low Transition

The action begins when the Chip Enable (CE) pin is

pulled low. The tri-state Serial Output (SO)pin driver

will be enabled entire time that CE is low. At the fall-

ing edge of the CE pin, the diagnostic data from the

voltage comparators in the output stages will be

latched into the shift register. If a particular output is

high, a logic one will be jammed into that bit in the

shift register. If the output is low, a logic zero will be

loaded there. The most significant bit (07) should be

presented at the Serial Input (SI) pin. A zero at this

pin will program an output ON, while a one will pro-

gram the output OFF.

Internal Blocks Description

The internal architecture of the device is based on

the three internal major blocks : the octal shift reg-

isterfortalking totheSPIbus,the octal latch forhold-

ing control bits written into the device and the octal

load driver array.

SCLK Transitions

Shift Register

The Serial Clock (SCLK) pin should then be pulled

high. At this point the diagnostic bit from the most

significant output (07) will appear at the SO pin. A

high here indicates that the 07 pin is higher than

1.8V. The SCLK pin should then be toggled lowthen

high. New SO data will appear following every rising

edge of SCLK and new SI data will be latched into

the L9822N shiftregisteron the falling edges. An un-

limited amount of data may be shifted through the

device shift register (into the SI pin and out the SO

pin), allowing the other SPI devices to be cascaded

in a daisy chain with the L9822N.

The shift register has both serial and parallel inputs

and serial and parallel outputs. The serial input ac-

cepts data from the SPI bus and the serial output

simultaneously sends data into the SPI bus. The

parallel outputs are latched into the parallel latch in-

side the L9822N at the end of a data transfer. The

parallel inputs jam diagnostic data into the shift reg-

ister at the beginning of a data transfer cycle.

Parallel Latch

The parallel latch holds the input data from the shift

5/9

L9822N

CE pin, so that the SCLK pin is ignored whenever

the CE pin is high.

CE Low to High Transition

Once the last data bit has been shifted into the

L9822NSP, the CE pin should be pulled high.

FAULT CONDITIONS CHECK

At the rising edge of CE the shift register data is

latched into the parallel latch and the output stages

will be actuated by the new data. An internal 160µs

delay timer will also be started at this rising edge

(see t_UD). During the 160µs period, the outputs will

be protected only by the analog current limiting cir-

cuits since the resetting of the parallel latches by

faults conditions will be inhibited during this period.

Thisallowsthe partto overcomeanyhighinrushcur-

rents that may flow immediately after turn on. Once

the delay period has elapsed, the output voltages

are sensed by the comparators and any output with

voltageshigher than 1.8V are latched OFF. It should

be noted that the SCLK pin should be low at both

transitions of the CE pin to avoid any false clocking

of the shift register. The SCLK input is gated by the

Checking for fault conditions may be done in the fol-

lowing way. Clock in a new control byte. Wait 160

microseconds or so to allow the outputs to settle.

Clockin the same control byte and observethe diag-

nostic data that comes out of the device. The diag-

nostic bits should be identical to the bits that were

first clocked in. Any differences would point to a fault

on that output. If the output was programmed ON by

clocking in a zero, and a one came back as the di-

agnostic bit for that output, the output pin was still

high and a short circuit or overload condition exists.

If the output was programmed OFF by clocking in a

one, and a zero came back as the diagnostic bit for

that output, nothing had pulled the output pin high

and it must be floating, so an open circuit condition

exists for that output.

Figure 1 : Byte Timing with Asynchronous Reset.

6/9

L9822N

Figure 2 : Timing Diagram.

Figure 3 : Typical Application Circuit.

7/9

L9822N

inch

DIM.

OUTLINE AND

MECHANICAL DATA

MIN. TYP. MAX. MIN.

TYP. MAX.

0.104

2.35

0.10

0.33

0.23

12.60

2.65 0.093

0.30 0.004

0.51 0.013

0.32 0.009

13.00 0.496

0.012

0.200

0.013

(1)

0.512

7.40

7.60 0.291

0.299

0.050

1.27

10.0

0.25

0.40

10.65 0.394

0.75 0.010

1.27 0.016

0˚ (min.), 8˚ (max.)

0.10

0.419

0.030

0.050

ddd

0.004

SO20

(1) “D” dimension does not include mold flash, protusions or gate

burrs. Mold flash, protusions or gate burrs shall not exceed

0.15mm per side.

0016022 D

8/9

L9822N

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the conse-

quences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No

license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this

publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMi-

croelectronics products are not authorized for use as critical components in life support devices or systems without express written

approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

All other names are the property of their respective owners

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9/9

L9822N013TR [STMICROELECTRONICS]

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