M24LR64-RZ185/2_技术文档

M24LR64-R

Dynamic NFC/RFID tag IC with 64-Kbit EEPROM

with I²C bus and ISO 15693 RF interface

Datasheet - production data

Contactless interface

• ISO 15693 and ISO 18000-3 mode 1

compatible

• 13.56 MHz ± 7 kHz carrier frequency

SO8 (MN)

150 mils width

• To tag:

– 10% or 100% ASK modulation using 1/4

(26 kbit/s) or 1/256 (1.6 kbit/s) pulse

position coding

• From tag:

UFDFPN8 (MC)

2 × 3 mm

– load modulation using Manchester coding

with 423 kHz and 484 kHz subcarriers in

low (6.6 kbit/s) or high (26 kbit/s) data rate

mode.

– Supports the 53 kbit/s data rate with Fast

commands

TSSOP8 (DW)

• Internal tuning capacitance:

– 27.5 pF

• 64-bit unique identifier (UID)

• Read Block & Write (32-bit Blocks)

Memory

• 64-Kbit EEPROM organized into:

2

– 8192 bytes in I C mode

Sawn wafer on UV tape

– 2048 blocks of 32 bits in RF mode

• Write time:

Features

2

– I C: 5 ms (Max.)

– RF: 5.75 ms including the internal Verify

time

I²C interface

2

• Two-wire I C serial interface supports 400 kHz

• More than 1 Million write cycles

protocol

• Multiple password protection in RF mode

• Single supply voltage:

2

• Single password protection in I C mode

– 1.8 V to 5.5 V

• More than 40-year data retention

• Package:

• Byte and Page Write (up to 4 bytes)

• Random and Sequential Read modes

• Self-timed programming cycle

®

– ECOPACK2 (RoHS compliant and

Halogen-free)

• Automatic address incrementing

• Enhanced ESD/latch-up protection

July 2013

DocID15170 Rev 16

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This is information on a product in full production.

www.st.com

1

Contents

M24LR64-R

Contents

1

2

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.1

2.2

2.3

2.4

2.5

2.6

Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Chip Enable (E0, E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Antenna coil (AC0, AC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

V_SSground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Supply voltage (V_CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.6.1

2.6.2

2.6.3

2.6.4

Operating supply voltage V

CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3

4

User memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

System memory area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

4.1

4.2

4.3

4.4

4.5

M24LR64-R RF block security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Example of the M24LR64-R security protection . . . . . . . . . . . . . . . . . . . . 25

I2C_Write_Lock bit area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

System parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

M24LR64-R I²C password security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2

4.5.1

4.5.2

I C Present Password command description . . . . . . . . . . . . . . . . . . . . 27

2

I C Write Password command description . . . . . . . . . . . . . . . . . . . . . . 28

2

5

I C device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.1

5.2

5.3

5.4

5.5

5.6

5.7

Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

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5.8

5.9

Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 34

5.10 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.11 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5.12 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.13 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.14 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

6

7

User memory initial state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

RF device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7.1

7.2

Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Initial dialog for vicinity cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

7.2.1

7.2.2

7.2.3

Power transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Operating field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

8

9

Communication signal from VCD to M24LR64-R . . . . . . . . . . . . . . . . . 40

Data rate and data coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

9.1

9.2

9.3

9.4

Data coding mode: 1 out of 256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Data coding mode: 1 out of 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

VCD to M24LR64-R frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Start of frame (SOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

10

11

Communications signal from M24LR64-R to VCD . . . . . . . . . . . . . . . . 47

10.1 Load modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

10.2 Subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

10.3 Data rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Bit representation and coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

11.1 Bit coding using one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

11.1.1

11.1.2

High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

11.2 Bit coding using two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

11.3 High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

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11.4 Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

12

M24LR64-R to VCD frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

12.1 SOF when using one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

12.2 High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

12.3 Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

12.4 SOF when using two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

12.5 High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

12.6 Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

12.7 EOF when using one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

12.8 High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

12.9 Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

12.10 EOF when using two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

12.11 High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

12.12 Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

13

14

15

Unique identifier (UID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Application family identifier (AFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Data storage format identifier (DSFID) . . . . . . . . . . . . . . . . . . . . . . . . . 57

15.1 CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

16

17

M24LR64-R protocol description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

M24LR64-R states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

17.1 Power-off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

17.2 Ready state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

17.3 Quiet state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

17.4 Selected state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

18

Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

18.1 Addressed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

18.2 Non-addressed mode (general request) . . . . . . . . . . . . . . . . . . . . . . . . . 62

18.3 Select mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

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19

Request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

19.1 Request flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

20

21

Response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

20.1 Response flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

20.2 Response error code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Anticollision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

21.1 Request parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

22

23

24

25

Request processing by the M24LR64-R . . . . . . . . . . . . . . . . . . . . . . . . 69

Explanation of the possible cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Inventory Initiated command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Timing definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

25.1 t1: M24LR64-R response delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

25.2 t2: VCD new request delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

25.3 t₃: VCD new request delay in the absence of a response from

the M24LR64-R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

26

Commands codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

26.1 Inventory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

26.2 Stay Quiet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

26.3 Read Single Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

26.4 Write Single Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

26.5 Read Multiple Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

26.6 Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

26.7 Reset to Ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

26.8 Write AFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

26.9 Lock AFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

26.10 Write DSFID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

26.11 Lock DSFID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

26.12 Get System Info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

26.13 Get Multiple Block Security Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

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26.14 Write-sector Password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

26.15 Lock-sector Password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

26.16 Present-sector Password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

26.17 Fast Read Single Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

26.18 Fast Inventory Initiated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

26.19 Fast Initiate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

26.20 Fast Read Multiple Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

26.21 Inventory Initiated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

26.22 Initiate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

27

28

29

30

31

Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

2

I C DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

RF electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Appendix A Anticollision algorithm (informative) . . . . . . . . . . . . . . . . . . . . . . . 116

A.1

Algorithm for pulsed slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116

Appendix B CRC (informative) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

B.1

B.2

CRC error detection method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

CRC calculation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

Appendix C Application family identifier (AFI) (informative) . . . . . . . . . . . . . . 119

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

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List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Address most significant byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Address least significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Sector details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Sector Security Status Byte area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Sector security status byte organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Read / Write protection bit setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Password Control bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Password system area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

M24LR64-R sector security protection after power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

M24LR64-R sector security protection after a valid presentation of password 1 . . . . . . . . 26

I2C_Write_Lock bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

System parameter sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

10% modulation parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Response data rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

UID format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

CRC transmission rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

VCD request frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

M24LR64-R Response frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

M24LR64-R response depending on Request_flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

General request format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Definition of request flags 1 to 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Request flags 5 to 8 when Bit 3 = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Request flags 5 to 8 when Bit 3 = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

General response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Definitions of response flags 1 to 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Response error code definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Inventory request format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Example of the addition of 0 bits to an 11-bit mask value . . . . . . . . . . . . . . . . . . . . . . . . . 67

Timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Inventory request format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Inventory response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Stay Quiet request format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Read Single Block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Read Single Block response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . 76

Sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Read Single Block response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . 77

Write Single Block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Write Single Block response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . 78

Write Single Block response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . 78

Read Multiple Block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Read Multiple Block response format when Error_flag is NOT set. . . . . . . . . . . . . . . . . . . 79

Sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Read Multiple Block response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . 79

Select request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

Table 25.

Table 26.

Table 27.

Table 28.

Table 29.

Table 30.

Table 31.

Table 32.

Table 33.

Table 34.

Table 35.

Table 36.

Table 37.

Table 38.

Table 39.

Table 40.

Table 41.

Table 42.

Table 43.

Table 44.

Table 45.

Table 46.

Table 47.

Table 48.

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Table 49.

Table 50.

Table 51.

Table 52.

Table 53.

Table 54.

Table 55.

Table 56.

Table 57.

Table 58.

Table 59.

Table 60.

Table 61.

Table 62.

Table 63.

Table 64.

Table 65.

Table 66.

Table 67.

Table 68.

Table 69.

Table 70.

Table 71.

Table 72.

Table 73.

Table 74.

Table 75.

Table 76.

Table 77.

Table 78.

Table 79.

Table 80.

Table 81.

Table 82.

Table 83.

Table 84.

Table 85.

Table 86.

Table 87.

Table 88.

Table 89.

Table 90.

Table 91.

Table 92.

Table 93.

Table 94.

Table 95.

Table 96.

Table 97.

Table 98.

Table 99.

Select Block response format when Error_flag is NOT set. . . . . . . . . . . . . . . . . . . . . . . . . 80

Select response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Reset to Ready request format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Reset to Ready response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . 81

Reset to ready response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Write AFI request format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Write AFI response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Write AFI response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Lock AFI request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Lock AFI response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Lock AFI response format when Error_flag is set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Write DSFID request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Write DSFID response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . 85

Write DSFID response format when Error_flag is set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Lock DSFID request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Lock DSFID response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . . 87

Lock DSFID response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Get System Info request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Get System Info response format when Error_flag is NOT set. . . . . . . . . . . . . . . . . . . . . . 88

Get System Info response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Get Multiple Block Security Status request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Get Multiple Block Security Status response format when Error_flag is NOT set . . . . . . . 90

Sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Get Multiple Block Security Status response format when Error_flag is set. . . . . . . . . . . . 90

Write-sector Password request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Write-sector Password response format when Error_flag is NOT set . . . . . . . . . . . . . . . . 91

Write-sector Password response format when Error_flag is set. . . . . . . . . . . . . . . . . . . . . 91

Lock-sector Password request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Lock-sector Password response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . 93

Lock-sector Password response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . 93

Present-sector Password request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Present-sector Password response format when Error_flag is NOT set . . . . . . . . . . . . . . 94

Present-sector Password response format when Error_flag is set. . . . . . . . . . . . . . . . . . . 94

Fast Read Single Block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Fast Read Single Block response format when Error_flag is NOT set . . . . . . . . . . . . . . . . 95

Sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Fast Read Single Block response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . 96

Fast Inventory Initiated request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Fast Inventory Initiated response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Fast Initiate request format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Fast Initiate response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Fast Read Multiple Block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Fast Read Multiple Block response format when Error_flag is NOT set. . . . . . . . . . . . . . . 99

Sector security status if Option_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Fast Read Multiple Block response format when Error_flag is set . . . . . . . . . . . . . . . . . . 100

Inventory Initiated request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Inventory Initiated response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Initiate request format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Initiate Initiated response format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

2

Table 100. I C operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

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Table 101. AC test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Table 102. Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

2

Table 103. I C DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

2

Table 104. I C AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 105. RF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 106. Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Table 107. SO8N – 8-lead plastic small outline, 150 mils body width, package data. . . . . . . . . . . . . 111

Table 108. UFDFPN8 (MLP8) – Ultra thin fine pitch dual flat package no lead 2 x 3 mm,

package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Table 109. TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . 113

Table 110. Ordering information scheme for packaged devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Table 111. Ordering information scheme for bare die devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Table 112. CRC definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Table 113. AFI coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Table 114. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

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List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

8-pin package connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2

I C Fast mode (f = 400 kHz): maximum R

value versus bus parasitic

C

bus

capacitance (C ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

bus

2

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

I C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Memory sector organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2

I C Present Password command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2

I C Write Password command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 10. Write mode sequences with I2C_Write_Lock bit = 1 (data write inhibited). . . . . . . . . . . . . 31

Figure 11. Write mode sequences with I2C_Write_Lock bit = 0 (data write enabled) . . . . . . . . . . . . . 33

Figure 12. Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 13. Read mode sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 14. 100% modulation waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 15. 10% modulation waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 16. 1 out of 256 coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 17. Detail of a time period. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 18. 1 out of 4 coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 19. 1 out of 4 coding example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 20. SOF to select 1 out of 256 data coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 21. SOF to select 1 out of 4 data coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 22. EOF for either data coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 23. Logic 0, high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 24. Logic 0, high data rate x2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 25. Logic 1, high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 26. Logic 1, high data rate x2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 27. Logic 0, low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 28. Logic 0, low data rate x2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 29. Logic 1, low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 30. Logic 1, low data rate x2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 31. Logic 0, high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 32. Logic 1, high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 33. Logic 0, low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 34. Logic 1, low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 35. Start of frame, high data rate, one subcarrier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 36. Start of frame, high data rate, one subcarrier x2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 37. Start of frame, low data rate, one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 38. Start of frame, low data rate, one subcarrier x2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 39. Start of frame, high data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 40. Start of frame, low data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 41. End of frame, high data rate, one subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 42. End of frame, high data rate, one subcarriers x2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 43. End of frame, low data rate, one subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 44. End of frame, low data rate, one subcarriers x2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 45. End of frame, high data rate, two subcarriers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 46. End of frame, low data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 47. M24LR64-R decision tree for AFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

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List of figures

Figure 48. M24LR64-R protocol timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 49. M24LR64-R state transition diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 50. Principle of comparison between the mask, the slot number and the UID . . . . . . . . . . . . . 68

Figure 51. Description of a possible anticollision sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 52. Stay Quiet frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 53. Read Single Block frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . 77

Figure 54. Write Single Block frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . 78

Figure 55. Read Multiple Block frame exchange between VCD and M24LR64-R. . . . . . . . . . . . . . . . 80

Figure 56. Select frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Figure 57. Reset to Ready frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . . . 82

Figure 58. Write AFI frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 59. Lock AFI frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 60. Write DSFID frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . . . . . 86

Figure 61. Lock DSFID frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . . . . . . 88

Figure 62. Get System Info frame exchange between VCD and M24LR64-R. . . . . . . . . . . . . . . . . . . 89

Figure 63. Get Multiple Block Security Status frame exchange between VCD and M24LR64-R . . . . 90

Figure 64. Write-sector Password frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . 92

Figure 65. Lock-sector Password frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . 93

Figure 66. Present-sector Password frame exchange between VCD and M24LR64-R . . . . . . . . . . . 95

Figure 67. Fast Read Single Block frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . 96

Figure 68. Fast Initiate frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . . . . . . 98

Figure 69. Fast Read Multiple Block frame exchange between VCD and M24LR64-R. . . . . . . . . . . 100

Figure 70. Initiate frame exchange between VCD and M24LR64-R . . . . . . . . . . . . . . . . . . . . . . . . . 103

Figure 71. AC test measurement I/O waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

2

Figure 72. I C AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Figure 73. M24LR64-R synchronous timing, transmit and receive . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Figure 74. SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . 111

Figure 75. UFDFPN8 (MLP8) – Ultra thin fine pitch dual flat package no lead 2 x 3 mm,

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 76. TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . 113

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Description

M24LR64-R

1

Description

The M24LR64-R device is a Dynamic NFC/RFID tag IC with a dual-interface, electrically

2

erasable programmable memory (EEPROM). It features an I C interface and can be

operated from a V power supply. It is also a contactless memory powered by the received

CC

2

carrier electromagnetic wave. The M24LR64-R is organized as 8192 × 8 bits in the I C

mode and as 2048 × 32 bits in the ISO 15693 and ISO 18000-3 mode 1 RF mode.

Figure 1. Logic diagram

V

CC

2

E0-E1

SCL

SDA

AC0

AC1

M24LR64-R

V

SS

AI15106b

2

I C uses a two-wire serial interface, comprising a bidirectional data line and a clock line. The

2

devices carry a built-in 4-bit device type identifier code (1010) in accordance with the I C

bus definition.

2

The device behaves as a slave in the I C protocol, with all memory operations synchronized

by the serial clock. Read and Write operations are initiated by a Start condition, generated

by the bus master. The Start condition is followed by a device select code and Read/Write

bit (RW) (as described in Table 2), terminated by an acknowledge bit.

th

When writing data to the memory, the device inserts an acknowledge bit during the 9 bit

time, following the bus master’s 8-bit transmission. When data is read by the bus master,

the bus master acknowledges the receipt of the data byte in the same way. Data transfers

are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.

In the ISO15693/ISO18000-3 mode 1 RF mode, the M24LR64-R is accessed via the

13.56 MHz carrier electromagnetic wave on which incoming data are demodulated from the

received signal amplitude modulation (ASK: amplitude shift keying). The received ASK

wave is 10% or 100% modulated with a data rate of 1.6 kbits/s using the 1/256 pulse coding

mode or a data rate of 26 kbit/s using the 1/4 pulse coding mode.

Outgoing data are generated by the M24LR64-R load variation using Manchester coding

with one or two subcarrier frequencies at 423 kHz and 484 kHz. Data are transferred from

the M24LR64-R at 6.6 kbit/s in low data rate mode and 26 kbit/s high data rate mode. The

M24LR64-R supports the 53 kbit/s in high data rate mode in one subcarrier frequency at 423

kHz.

The M24LR64-R follows the ISO 15693 and ISO 18000-3 mode 1 recommendation for

radio-frequency power and signal interface.

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M24LR64-R

Description

Table 1. Signal names

Function

Signal name

Direction

E0, E1

SDA

Chip Enable

Serial Data

Serial Clock

Antenna coils

Supply voltage

Ground

Input

I/O

Input

I/O

-

SCL

AC0, AC1

V_CC

V_SS

-

Figure 2. 8-pin package connections

E0

AC0

AC1

1

2

3

4

8

7

6

5

V

E1

SCL

SDA

CC

V

SS

AI15107

1. See Package mechanical data section for package dimensions, and how to identify pin-1.

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Signal description

M24LR64-R

2

Signal description

2.1

Serial Clock (SCL)

This input signal is used to strobe all data in and out of the device. In applications where this

signal is used by slave devices to synchronize the bus to a slower clock, the bus master

must have an open drain output, and a pull-up resistor must be connected from Serial Clock

(SCL) to V . (Figure 4 indicates how the value of the pull-up resistor can be calculated). In

CC

most applications, though, this method of synchronization is not employed, and so the pull-

up resistor is not necessary, provided that the bus master has a push-pull (rather than open

drain) output.

2.2

2.3

Serial Data (SDA)

This bidirectional signal is used to transfer data in or out of the device. It is an open drain

output that may be wire-OR’ed with other open drain or open collector signals on the bus. A

pull up resistor must be connected from Serial Data (SDA) to V . (Figure 4 indicates how

CC

the value of the pull-up resistor can be calculated).

Chip Enable (E0, E1)

These input signals are used to set the value that is to be looked for on the two least

significant bits (b2, b1) of the 7-bit device select code. These inputs must be tied to V or

CC

V

, to establish the device select code as shown in Figure 3. When not connected (left

SS

floating), these inputs are read as low (0,0).

Figure 3. Device select code

V

CC

M24xxx

E

i

V

SS

Ai12806

2.4

Antenna coil (AC0, AC1)

These inputs are used to connect the device to an external coil exclusively. It is advised to

not connect any other DC or AC path to AC0 and AC1 pads. When correctly tuned, the coil

is used to power and access the device using the ISO 15693 and ISO 18000-3 mode 1

protocols.

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M24LR64-R

Signal description

2.5

V_SSground

V

is the reference for the V supply voltage.

CC

SS

2.6

Supply voltage (V_CC)

This pin can be connected to an external DC supply voltage.

Note:

An internal voltage regulator allows the external voltage applied on V to supply the

CC

M24LR64-R, while preventing the internal power supply (rectified RF waveforms) to output a

DC voltage on the V pin.

CC

2.6.1

Operating supply voltage V

CC

Prior to selecting the memory and issuing instructions to it, a valid and stable V voltage

CC

within the specified [V (min), V (max)] range must be applied (see Table 100). To

CC

maintain a stable DC supply voltage, it is recommended to decouple the V line with a

CC

suitable capacitor (usually of the order of 10 nF) close to the V /V package pins.

CC SS

This voltage must remain stable and valid until the end of the transmission of the instruction

and, for a Write instruction, until the completion of the internal I²C write cycle (t ).

W

2.6.2

2.6.3

Power-up conditions

When the power supply is turned on, V rises from V to V . The V rise time must not

vary faster than 1V/µs.

CC

SS

CC

Device reset

In order to prevent inadvertent write operations during power-up, a power-on reset (POR)

circuit is included. At power-up (continuous rise of V ), the device does not respond to any

CC

instruction until V has reached the power-on reset threshold voltage (this threshold is

CC

lower than the minimum V operating voltage defined in Table 100). When V passes

CC

over the POR threshold, the device is reset and enters the Standby Power mode, however,

the device must not be accessed until V has reached a valid and stable V voltage

CC

within the specified [V (min), V (max)] range.

CC

In a similar way, during power-down (continuous decrease in V ), as soon as V drops

CC

below the power-on reset threshold voltage, the device stops responding to any instruction

sent to it.

2.6.4

Power-down conditions

During power-down (continuous decay of V ), the device must be in Standby Power mode

CC

(mode reached after decoding a Stop condition, assuming that there is no internal write

cycle in progress).

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Signal description

M24LR64-R

2

Figure 4. I C Fast mode (f = 400 kHz): maximum R

value versus bus parasitic

C

bus

capacitance (C

)

bus

100

The R

x C time constant

bus

must be below the 400 ns

time constant line represented

on the left.

V

CC

10

R

bus

Here R

bus

× C = 120 ns

bus

4 k

SCL

SDA

I²C bus

master

M24xxx

1

30 pF

C

bus

10

100

Bus line capacitor (pF)

1000

ai14796b

2

Figure 5. I C bus protocol

SCL

SDA

Input

SDA

Change

START

Condition

STOP

Condition

1

2

3

7

8

9

SCL

SDA

ACK

MSB

START

Condition

1

2

3

7

8

9

SCL

SDA

MSB

ACK

STOP

Condition

AI00792B

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Signal description

Table 2. Device select code

Device type identifier⁽¹⁾

Chip Enable address⁽²⁾

RW

b7

b6

b5

b4

b3

b2

b1

b0

Device select code

1

0

1

0

E2⁽³⁾

E1

E0

RW

1. The most significant bit, b7, is sent first.

2. E0 and E1 are compared against the respective external pins on the memory device.

3. E2 is not connected to any external pin. It is however used to address the M24LR64-R as described in

Section 3 and Section 4.

Table 3. Address most significant byte

b15

b7

b14

b6

b13

b12

b11

b10

b9

b1

b8

b0

Table 4. Address least significant byte

b5 b4 b3 b2

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User memory organization

M24LR64-R

3

User memory organization

The M24LR64-R is divided into 64 sectors of 32 blocks of 32 bits as shown in Table 5.

Figure 7 shows the memory sector organization. Each sector can be individually read-

and/or write-protected using a specific password command. Read and write operations are

possible if the addressed data are not in a protected sector.

The M24LR64-R also has a 64-bit block that is used to store the 64-bit unique identifier

(UID). The UID is compliant with the ISO 15963 description, and its value is used during the

anticollision sequence (Inventory). This block is not accessible by the user and its value is

written by ST on the production line.

The M24LR64-R includes an AFI register that stores the application family identifier, and a

DSFID register that stores the data storage family identifier used in the anticollision

algorithm.

2

The M24LR64-R has four additional 32-bit blocks that store an I C password plus three RF

password codes.

Figure 6. Block diagram

EEPROM

Latch

AC0

SCL

SDA

2

Logic

RF

I C

AC1

V

CC

SS

Power management

Contact V

RF V

CC

ai15123

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M24LR64-R

User memory organization

Figure 7. Memory sector organization

Sector

Area

Sector security

status

0

1

2

3

1 Kbit EEPROM sector

5 bits

60

61

62

63

1 Kbit EEPROM sector

5 bits

I2C Password

RF Password 1

RF Password 2

RF Password 3

8 bit DSFID

System

8 bit AFI

64 bit UID

ai15124

Sector details

The M24LR64-R user memory is divided into 64 sectors. Each sector contains 1024 bits.

The protection scheme is described in Section 4: System memory area.

In RF mode, a sector provides 32 blocks of 32 bits. Each read and write access are done by

block. Read and write block accesses are controlled by a Sector Security Status byte that

defines the access rights to all the 32 blocks contained in the sector. If the sector is not

protected, a Write command updates the complete 32 bits of the selected block.

2

In I C mode, a sector provides 128 bytes that can be individually accessed in read and write

modes. When protected by the corresponding I2C_Write_Lock bit, the entire sector is write-

2

protected. To access the user memory, the device select code used for any I C command

must have the E2 Chip Enable address at 0.

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User memory organization

M24LR64-R

Bits [7:0]

Table 5. Sector details

I²C byte

Sector

RF block

Bits [31:24] Bits [23:16]

Bits [15:8]

number

address

0

4

user

1

2

8

3

12

16

20

24

28

32

36

40

44

48

52

56

60

64

68

72

76

80

84

88

92

96

100

104

108

112

116

120

124

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

0

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User memory organization

Table 5. Sector details (continued)

Sector

number

RF block

address

I²C byte

Bits [31:24] Bits [23:16]

address

Bits [15:8]

Bits [7:0]

32

33

34

35

36

37

38

39

...

128

132

136

140

144

148

152

156

...

user

...

user

...

user

...

user

...

1

...

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User memory organization

M24LR64-R

Bits [7:0]

Table 5. Sector details (continued)

Sector

RF block

I²C byte

Bits [31:24] Bits [23:16]

address

Bits [15:8]

number

address

2016

2017

2018

2019

2020

2021

2022

2023

2024

2025

2026

2027

2028

2029

2030

2031

2032

2033

2034

2035

2036

2037

2038

2039

2040

2041

2042

2043

2044

2045

2046

2047

8064

8068

8072

8076

8080

8084

8088

8092

8096

8100

8104

8108

8112

8116

8120

8124

8128

8132

8136

8140

8144

8148

8152

8156

8160

8164

8168

8172

8176

8180

8184

8188

user

63

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System memory area

4

System memory area

4.1

M24LR64-R RF block security

The M24LR64-R provides a special protection mechanism based on passwords. Each

memory sector of the M24LR64-R can be individually protected by one out of three available

passwords, and each sector can also have Read/Write access conditions set.

Each memory sector of the M24LR64-R is assigned with a Sector security status byte

including a Sector Lock bit, two Password Control bits and two Read/Write protection bits as

shown in Table 7. Table 6 describes the organization of the Sector security status byte

which can be read using the Read Single Block and Read Multiple Block commands with

the Option_flag set to ‘1’.

On delivery, the default value of the SSS bytes is reset to 00h.

Table 6. Sector Security Status Byte area

I²C byte address

Bits [31:24]

Bits [23:16]

Bits [15:8]

Bits [7:0]

E2 = 1

0

SSS 3

SSS 7

SSS 2

SSS 6

SSS 1

SSS 5

SSS 0

SSS 4

4

8

SSS 11

SSS 15

SSS 19

SSS 23

SSS 27

SSS 31

SSS 35

SSS 39

SSS 43

SSS 47

SSS 51

SSS 55

SSS 59

SSS 63

SSS 10

SSS 14

SSS 18

SSS 22

SSS 26

SSS 30

SSS 34

SSS 38

SSS 42

SSS 46

SSS 50

SSS 54

SSS 58

SSS 62

SSS 9

SSS 8

12

16

20

24

28

32

36

40

44

48

52

56

60

SSS 13

SSS 17

SSS 21

SSS 25

SSS 29

SSS 33

SSS 37

SSS 41

SSS 45

SSS 49

SSS 53

SSS 57

SSS 61

SSS 12

SSS 16

SSS 20

SSS 24

SSS 28

SSS 32

SSS 36

SSS 40

SSS 44

SSS 48

SSS 52

SSS 56

SSS 60

Table 7. Sector security status byte organization

b₇

0

b₆

0

b₅

b₄

b₃

b₂

b₁

b₀

Read / Write protection

bits

Sector

Lock

0

Password Control bits

When the Sector Lock bit is set to ‘1’, for instance by issuing a Lock-sector Password

command, the 2 Read/Write protection bits (b , b ) are used to set the Read/Write access of

1

2

the sector as described in Table 8.

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System memory area

M24LR64-R

Table 8. Read / Write protection bit setting

Sector

Lock

Sector access when password

presented

Sector access when password not

presented

b₂, b₁

0

1

xx

00

01

10

11

Read

Write

Read

Write

No Write

Write

Read

Write

No Read

No Write

The next 2 bits of the Sector security status byte (b , b ) are the Password Control bits. The

3

4

value these two bits is used to link a password to the sector as defined in Table 9.

Table 9. Password Control bits

b₄, b₃

Password

00

01

10

11

The sector is not protected by a Password

The sector is protected by the Password 1

The sector is protected by the Password 2

The sector is protected by the Password 3

The M24LR64-R password protection is organized around a dedicated set of commands

plus a system area of three password blocks where the password values are stored. This

system area is described in Table 10.

Table 10. Password system area

Block number

32-bit password number

1

2

3

Password 1

Password 2

Password 3

The dedicated password commands are:

•

Write-sector Password:

The Write-sector Password command is used to write a 32-bit block into the password

system area. This command must be used to update password values. After the write

cycle, the new password value is automatically activated. It is possible to modify a

password value after issuing a valid Present-sector Password command.

On delivery, the three default password values are set to 0000 0000h and are

activated.

•

Lock-sector Password:

The Lock-sector Password command is used to set the Sector security status byte of

the selected sector. Bits b to b of the Sector security status byte are affected by the

4

1

Lock-sector Password command. The Sector Lock bit, b , is set to ‘1’ automatically.

0

After issuing a Lock-sector Password command, the protection settings of the selected

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M24LR64-R

System memory area

sector are activated. The protection of a locked block cannot be changed in RF mode.

A Lock-sector Password command sent to a locked sector returns an error code.

•

Present-sector Password:

The Present-sector Password command is used to present one of the three passwords

to the M24LR64-R in order to modify the access rights of all the memory sectors linked

to that password (Table 8) including the password itself. If the presented password is

correct, the access rights remain activated until the tag is powered off or until a new

Present-sector Password command is issued. If the presented password value is not

correct, all the access rights of all the memory sectors are deactivated.

2

Sector security status byte area access conditions in I C mode:

2

In I C mode, read access to the Sector security status byte area is always allowed.

2

Write access depends on the correct presentation of the I C password (see I C

Present Password command description on page 27).

2

To access the Sector security status byte area, the device select code used for any I C

command must have the E2 Chip Enable address at 1.

2

An I C write access to a Sector security status byte re-initializes the RF access

condition to the given memory sector.

4.2

Example of the M24LR64-R security protection

Table 11 and Table 12 show the sector security protections before and after a valid Present-

sector Password command. Table 11 shows the sector access rights of an M24LR64-R after

power-up. After a valid Present-sector Password command with password 1, the memory

sector access is changed as shown in Table 12.

Table 11. M24LR64-R sector security protection after power-up

Sector security status byte

Sector

address

b₇b₆b₅b₄b₃b₂b₁b₀

0

1

2

3

4

Protection: Standard

Protection: Pswd 1

Read

No Write

Write

xxx

0

1

0

1

0

1

0

1

Read

No Read

No Write

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System memory area

M24LR64-R

Table 12. M24LR64-R sector security protection after a valid presentation of password 1

Sector security status byte

Sector

address

b₇b₆b₅b₄b₃b₂b₁b₀

0

1

2

3

4

Protection: Standard

Protection: Pswd 1

Read

No Write

Write

xxx

0

1

0

1

0

1

0

1

Write

No Write

4.3

I2C_Write_Lock bit area

2

In the I C mode only, it is possible to protect individual sectors against Write operations.

This feature is controlled by the I2C_Write_Lock bits stored in the 8 bytes of the

I2C_Write_Lock bit area starting from the location 2048 (see Table 13). Using these 64 bits,

it is possible to write-protect all the 64 sectors of the M24LR64-R memory.

2

Each bit controls the I C write access to a specific sector as shown in Table 13. It is always

2

possible to unprotect a sector in the I C mode. When an I2C_Write_Lock bit is reset to 0,

the corresponding sector is unprotected. When the bit is set to 1, the corresponding sector

is write-protected.

2

In I C mode, read access to the I2C_Write_Lock bit area is always allowed. Write access

2

depends on the correct presentation of the I C password.

2

To access the I2C_Write_Lock bit area, the device select code used for any I C command

must have the E2 Chip Enable address at 1.

On delivery, the default value of the 8 bytes of the I2C_Write_Lock bit area is reset to 00h.

Table 13. I2C_Write_Lock bit

I²C byte address

Bits [31:24]

Bits [23:16]

Bits [15:8]

Bits [7:0]

E2 = 1

2048

2052

sectors 31-24

sectors 63-56

sectors 23-16

sectors 55-48

sectors 15-8

sectors 7-0

sectors 47-40

sectors 39-32

4.4

System parameters

The M24LR64-R provides the system area required by the ISO 15693 RF protocol, as

shown in Table 14.

2

The first 32-bit block starting from I C address 2304 stores the I C password. This

2

password is used to activate/deactivate the write protection of the protected sector in I C

mode. At power-on, all user memory sectors protected by the I2C_Write_Lock bits can be

2

read but cannot be modified. To remove the write protection, it is necessary to use the I C

Present Password described in Figure 8. When the password is correctly presented — that

is, when all the presented bits correspond to the stored ones — it is also possible to modify

2

the I C password using the I C Write Password command described in Figure 9.

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System memory area

The next three 32-bit blocks store the three RF passwords. These passwords are neither

2

read- nor write- accessible in the I C mode.

2

The next 2 bytes are used to store the AFI, at I C location 2322, and the DSFID, at I C

location 2323. These 2 values are used during the RF Inventory sequence. They are read-

only in the I C mode.

2

The next 8 bytes, starting from location 2324, store the 64-bit UID programmed by ST on the

2

production line. Bytes at I C locations 2332 to 2335 store the IC Ref and the Mem_Size data

used by the RF Get_System_Info command. The UID, Mem_Size and IC Ref values are

read-only data.

Table 14. System parameter sector

I²C byte address

Bits [31:24]

Bits [23:16]

Bits [15:8]

Bits [7:0]

E2 = 1

2304

2308

2312

2316

2320

2324

2328

2332

I²C password ⁽¹⁾

RF password 1⁽¹⁾

RF password 2⁽¹⁾

RF password 3 ⁽¹⁾

DSFID (FFh)

UID

AFI (00h)

ST reserved

UID

ST reserved

UID

UID (E0h)

UID (02h)

UID

Mem_Size (03 07FFh)

IC Ref (2Ch)

1. Delivery state: I²C password= 0000 0000h, RF password = 0000 0000h,

4.5

M24LR64-R I²C password security

2

The M24LR64-R controls I C sector write access using the 32-bit-long I C password and

2

the 64-bit I2C_Write_Lock bit area. The I C password value is managed using two I C

commands: I C Present Password and I C Write Password.

2

4.5.1

I C Present Password command description

2

The I C Present Password command is used in I C mode to present the password to the

M24LR64-R in order to modify the write access rights of all the memory sectors protected by

the I2C_Write_Lock bits, including the password itself. If the presented password is correct,

2

the access rights remain activated until the M24LR64-R is powered off or until a new I C

Present Password command is issued.

Following a Start condition, the bus master sends a device select code with the Read/Write

bit (RW) reset to 0 and the Chip Enable bit E2 at 1. The device acknowledges this, as shown

2

in Figure 8, and waits for two I C password address bytes 09h and 00h. The device

responds to each address byte with an acknowledge bit, and then waits for the 4 password

data bytes, the validation code, 09h, and a resend of the 4 password data bytes. The most

significant byte of the password is sent first, followed by the least significant bytes.

It is necessary to send the 32-bit password twice to prevent any data corruption during the

sequence. If the two 32-bit passwords sent are not exactly the same, the M24LR64-R does

not start the internal comparison.

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System memory area

M24LR64-R

When the bus master generates a Stop condition immediately after the Ack bit (during the

th

“10 bit” time slot), an internal delay equivalent to the write cycle time is triggered. A Stop

condition at any other time does not trigger the internal delay. During that delay, the

2

M24LR64-R compares the 32 received data bits with the 32 bits of the stored I C password.

If the values match, the write access rights to all protected sectors are modified after the

internal delay. If the values do not match, the protected sectors remains protected.

During the internal delay, Serial Data (SDA) is disabled internally, and the device does not

respond to any requests.

2

Figure 8. I C Present Password command

Ack

Device select

code

Password

[31:24]

Password

[23:16]

Password

[15:8]

Password

[7:0]

address 09h

address 00h

R/W

Ack

Password

[31:24]

Password

[23:16]

Password

[15:8]

Password

[7:0]

Validation

code 09h

Device select code = 1010 1 E1 E0

th

Ack generated during

9

bit time slot.

ai15125b

2

4.5.2

I C Write Password command description

2

The I C Write Password command is used to write a 32-bit block into the M24LR64-R I C

2

password system area. This command is used in I C mode to update the I C password

value. It cannot be used to update any of the RF passwords. After the write cycle, the new

I C password value is automatically activated. The I C password value can only be modified

2

after issuing a valid I C Present Password command.

2

On delivery, the I C default password value is set to 0000 0000h and is activated.

Following a Start condition, the bus master sends a device select code with the Read/Write

bit (RW) reset to 0 and the Chip Enable bit E2 at 1. The device acknowledges this, as shown

2

in Figure 9, and waits for the two I C password address bytes, 09h and 00h. The device

responds to each address byte with an acknowledge bit, and then waits for the 4 password

data bytes, the validation code, 07h, and a resend of the 4 password data bytes. The most

significant byte of the password is sent first, followed by the least significant bytes.

It is necessary to send twice the 32-bit password to prevent any data corruption during the

write sequence. If the two 32-bit passwords sent are not exactly the same, the M24LR64-R

2

does not modify the I C password value.

When the bus master generates a Stop condition immediately after the Ack bit (during the

th

10 bit time slot), the internal write cycle is triggered. A Stop condition at any other time

does not trigger the internal write cycle.

During the internal write cycle, Serial Data (SDA) is disabled internally, and the device does

not respond to any requests.

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System memory area

2

Figure 9. I C Write Password command

Ack

Device select

Password

New password New password New password New password

[31:24] [23:16] [15:8] [7:0]

code

address 09h

address 00h

R/W

Ack

New password New password New password New password

Validation

code 07h

[31:24]

[23:16]

[15:8]

[7:0]

Device select code = 1010 1 E1 E0

th

Ack generated during

9

bit time slot.

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2

I C device operation

M24LR64-R

2

5

I C device operation

2

The device supports the I C protocol. This is summarized in Figure 5. Any device that sends

data on to the bus is defined to be a transmitter, and any device that reads the data to be a

receiver. The device that controls the data transfer is known as the bus master, and the

other as the slave device. A data transfer can only be initiated by the bus master, which will

also provide the serial clock for synchronization. The M24LR64-R device is always a slave

in all communications.

5.1

5.2

Start condition

Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in

the high state. A Start condition must precede any data transfer command. The device

continuously monitors (except during a write cycle) Serial Data (SDA) and Serial Clock

(SCL) for a Start condition, and will not respond unless one is given.

Stop condition

Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and

driven high. A Stop condition terminates communication between the device and the bus

master. A Read command that is followed by NoAck can be followed by a Stop condition to

force the device into the Standby mode. A Stop condition at the end of a Write command

triggers the internal write cycle.

5.3

5.4

5.5

Acknowledge bit (ACK)

The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,

whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits

th

of data. During the 9 clock pulse period, the receiver pulls Serial Data (SDA) low to

acknowledge the receipt of the eight data bits.

Data Input

During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock

(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge

of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock

(SCL) is driven low.

Memory addressing

To start communication between the bus master and the slave device, the bus master must

initiate a Start condition. Following this, the bus master sends the device select code, shown

in Table 2 (on Serial Data (SDA), most significant bit first).

The device select code consists of a 4-bit device type identifier, and a 3-bit Chip Enable

“Address” (E2, E1, E0). To address the memory array, the 4-bit device type identifier is

1010b.

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I C device operation

2

Up to four memory devices can be connected on a single I C bus. Each one is given a

unique 2-bit code on the Chip Enable (E0, E1) inputs. When the device select code is

received, the device only responds if the Chip Enable Address is the same as the value on

the Chip Enable (E0, E1) inputs.

th

The 8 bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.

If a match occurs on the device select code, the corresponding device gives an

th

acknowledgment on Serial Data (SDA) during the 9 bit time. If the device does not match

the device select code, it deselects itself from the bus, and goes into Standby mode.

Table 15. Operating modes

Mode

RW bit

Bytes

Initial sequence

Current Address Read

1

0

1

0

1

Start, device select, RW = 1

Start, device select, RW = 0, Address

reStart, device select, RW = 1

Similar to Current or Random Address Read

Start, device select, RW = 0

Random Address Read

1

Sequential Read

Byte Write

≥ 1

1

Page Write

≤ 4 bytes

Start, device select, RW = 0

Figure 10. Write mode sequences with I2C_Write_Lock bit = 1 (data write inhibited)

ACK

NO ACK

Byte Write

Page Write

Dev select

Byte address

Data in

R/W

ACK

Byte address

ACK

NO ACK

Dev select

NO ACK

Byte address

Data in 1

Data in 2

R/W

NO ACK

Data in N

Page Write

(cont'd)

AI15115

5.6

Write operations

Following a Start condition the bus master sends a device select code with the Read/Write

bit (RW) reset to 0. The device acknowledges this, as shown in Figure 11, and waits for two

address bytes. The device responds to each address byte with an acknowledge bit, and

then waits for the data byte.

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2

I C device operation

M24LR64-R

Writing to the memory may be inhibited if the I2C_Write_Lock bit = 1. A Write instruction

issued with the I2C_Write_Lock bit = 1 and with no I2C_Password presented, does not

modify the memory contents, and the accompanying data bytes are not acknowledged, as

shown in Figure 10.

Each data byte in the memory has a 16-bit (two byte wide) address. The most significant

byte (Table 3) is sent first, followed by the least significant byte (Table 4). Bits b15 to b0 form

the address of the byte in memory.

th

When the bus master generates a Stop condition immediately after the Ack bit (in the “10

bit” time slot), either at the end of a Byte Write or a Page Write, the internal write cycle is

triggered. A Stop condition at any other time slot does not trigger the internal write cycle.

After the Stop condition, the delay t , and the successful completion of a Write operation,

W

the device’s internal address counter is incremented automatically, to point to the next byte

address after the last one that was modified.

During the internal write cycle, Serial Data (SDA) is disabled internally, and the device does

not respond to any requests.

5.7

5.8

Byte Write

After the device select code and the address bytes, the bus master sends one data byte. If

the addressed location is write-protected by the I2C_Write_Lock bit (= 1), the device replies

with NoAck, and the location is not modified. If, instead, the addressed location is not Write-

protected, the device replies with Ack. The bus master terminates the transfer by generating

a Stop condition, as shown in Figure 11.

Page Write

The Page Write mode allows up to 4 bytes to be written in a single Write cycle, provided that

they are all located in the same “row” in the memory: that is, the most significant memory

address bits (b12-b2) are the same. If more bytes are sent than will fit up to the end of the

row, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to

become overwritten in an implementation dependent way.

The bus master sends from 1 to 4 bytes of data, each of which is acknowledged by the

device if the I2C_Write_Lock bit = 0 or the I2C_Password was correctly presented. If the

I2C_Write_Lock_bit = 1 and the I2C_password is not presented, the contents of the

addressed memory location are not modified, and each data byte is followed by a NoAck.

After each byte is transferred, the internal byte address counter (inside the page) is

incremented. The transfer is terminated by the bus master generating a Stop condition.

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I C device operation

Figure 11. Write mode sequences with I2C_Write_Lock bit = 0 (data write enabled)

ACK

Byte Write

Dev Select

Byte address

Data in

R/W

ACK

Byte address

ACK

Page Write

Dev Select

Byte address

Data in 1

Data in 2

Data in N

R/W

AI15116

Figure 12. Write cycle polling flowchart using ACK

Write cycle

in progress

Start condition

Device select

with RW = 0

ACK

NO

returned

First byte of instruction

with RW = 0 already

decoded by the device

YES

addressing the

memory

NO

YES

NO

Send Address

and Receive ACK

ReStart

StartCondition

YES

Stop

Data for the

Write cperation

Ddevice select

with RW = 1

Continue the

Random Read operation

Continue the

Write operation

AI01847d

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I C device operation

M24LR64-R

5.9

Minimizing system delays by polling on ACK

During the internal write cycle, the device disconnects itself from the bus, and writes a copy

of the data from its internal latches to the memory cells. The maximum I²C write time (t_w) is

shown in Table 104, but the typical time is shorter. To make use of this, a polling sequence

can be used by the bus master.

The sequence, as shown in Figure 12, is:

1. Initial condition: a write cycle is in progress.

2. Step 1: the bus master issues a Start condition followed by a device select code (the

first byte of the new instruction).

3. Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and

the bus master goes back to Step 1. If the device has terminated the internal write

cycle, it responds with an Ack, indicating that the device is ready to receive the second

part of the instruction (the first byte of this instruction having been sent during Step 1).

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I C device operation

Figure 13. Read mode sequences

ACK

NO ACK

Current

Address

Read

Dev sel

Data out

R/W

ACK

NO ACK

Random

Address

Read

Dev sel *

Byte addr

Dev sel *

Data out

R/W

ACK

NO ACK

Data out N

Sequential

Current

Read

Dev sel

Data out 1

R/W

ACK

R/W

ACK

R/W

ACK

Sequention

Random

Read

Dev sel *

ACK

Byte addr

Dev sel *

Data out1

NO ACK

Data out N

AI01105d

1. The seven most significant bits of the device select code of a Random Read (in the 1^stand 4^thbytes) must

be identical.

5.10

5.11

Read operations

Read operations are performed independently of the state of the I2C_Write_Lock bit.

After the successful completion of a Read operation, the device’s internal address counter is

incremented by one, to point to the next byte address.

Random Address Read

A dummy Write is first performed to load the address into this address counter (as shown in

Figure 13) but without sending a Stop condition. Then, the bus master sends another Start

condition, and repeats the device select code, with the Read/Write bit (RW) set to 1. The

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I C device operation

M24LR64-R

device acknowledges this, and outputs the contents of the addressed byte. The bus master

must not acknowledge the byte, and terminates the transfer with a Stop condition.

5.12

5.13

Current Address Read

For the Current Address Read operation, following a Start condition, the bus master only

sends a device select code with the Read/Write bit (RW) set to 1. The device acknowledges

this, and outputs the byte addressed by the internal address counter. The counter is then

incremented. The bus master terminates the transfer with a Stop condition, as shown in

Figure 13, without acknowledging the byte.

Sequential Read

This operation can be used after a Current Address Read or a Random Address Read. The

bus master does acknowledge the data byte output, and sends additional clock pulses so

that the device continues to output the next byte in sequence. To terminate the stream of

bytes, the bus master must not acknowledge the last byte, and must generate a Stop

condition, as shown in Figure 13.

The output data comes from consecutive addresses, with the internal address counter

automatically incremented after each byte output. After the last memory address, the

address counter ‘rolls-over’, and the device continues to output data from memory address

00h.

5.14

Acknowledge in Read mode

For all Read commands, the device waits, after each byte read, for an acknowledgment

th

during the 9 bit time. If the bus master does not drive Serial Data (SDA) low during this

time, the device terminates the data transfer and switches to its Standby mode.

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User memory initial state

6

User memory initial state

The device is delivered with all bits in the user memory array set to 1 (each byte contains

FFh).

7

RF device operation

The M24LR64-R is divided into 64 sectors of 32 blocks of 32 bits as shown in Table 5. Each

sector can be individually read- and/or write-protected using a specific lock or password

command.

Read and Write operations are possible if the addressed block is not protected. During a

Write, the 32 bits of the block are replaced by the new 32-bit value.

The M24LR64-R also has a 64-bit block that is used to store the 64-bit unique identifier

(UID). The UID is compliant with the ISO 15963 description, and its value is used during the

anticollision sequence (Inventory). This block is not accessible by the user and its value is

written by ST on the production line.

The M24LR64-R also includes an AFI register in which the application family identifier is

stored, and a DSFID register in which the data storage family identifier used in the

anticollision algorithm is stored. The M24LR64-R has three additional 32-bit blocks in which

the password codes are stored.

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RF device operation

M24LR64-R

7.1

Commands

The M24LR64-R supports the following commands:

•

Inventory, used to perform the anticollision sequence.

Stay Quiet, used to put the M24LR64-R in quiet mode, where it does not respond to

any inventory command.

•

Select, used to select the M24LR64-R. After this command, the M24LR64-R

processes all Read/Write commands with Select_flag set.

•

Reset To Ready, used to put the M24LR64-R in the ready state.

Read Block, used to output the 32 bits of the selected block and its locking status.

Write Block, used to write the 32-bit value in the selected block, provided that it is not

locked.

•

Read Multiple Blocks, used to read the selected blocks and send back their value.

Write AFI, used to write the 8-bit value in the AFI register.

Lock AFI, used to lock the AFI register.

Write DSFID, used to write the 8-bit value in the DSFID register.

Lock DSFID, used to lock the DSFID register.

Get System Info, used to provide the system information value

Get Multiple Block Security Status, used to send the security status of the selected

block.

•

Initiate, used to trigger the tag response to the Inventory Initiated sequence.

Inventory Initiated, used to perform the anticollision sequence triggered by the Initiate

command.

•

Write-sector Password, used to write the 32 bits of the selected password.

Lock-sector Password, used to write the Sector security status bits of the selected

sector.

•

Present-sector Password, enables the user to present a password to unprotect the

user blocks linked to this password.

•

Fast Initiate, used to trigger the tag response to the Inventory Initiated sequence.

Fast Inventory Initiated, used to perform the anticollision sequence triggered by the

Initiate command.

•

Fast Read Single Block, used to output the 32 bits of the selected block and its

locking status.

Fast Read Multiple Blocks, used to read the selected blocks and send back their

value.

7.2

Initial dialog for vicinity cards

The dialog between the vicinity coupling device or VCD (commonly the “RF reader”) and the

vicinity integrated circuit card or VICC (M24LR64-R) takes place as follows:

•

activation of the M24LR64-R by the RF operating field of the VCD

transmission of a command by the VCD

transmission of a response by the M24LR64-R

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RF device operation

These operations use the RF power transfer and communication signal interface described

below (see Power transfer, Frequency and Operating field). This technique is called RTF

(Reader Talk First).

7.2.1

Power transfer

Power is transferred to the M24LR64-R by radio frequency at 13.56 MHz via coupling

antennas in the M24LR64-R and the VCD. The RF operating field of the VCD is transformed

on the M24LR64-R antenna to an AC Voltage which is rectified, filtered and internally

regulated. The amplitude modulation (ASK) on this received signal is demodulated by the

ASK demodulator.

7.2.2

7.2.3

Frequency

The ISO 15693 standard defines the carrier frequency (f ) of the operating field as

13.56 MHz ±7 kHz.

C

Operating field

The M24LR64-R operates continuously between the minimum and maximum values of the

electromagnetic field H defined in Table 105. The VCD has to generate a field within these

limits.

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Communication signal from VCD to M24LR64-R

M24LR64-R

8

Communication signal from VCD to M24LR64-R

Communications between the VCD and the M24LR64-R takes place using the modulation

principle of ASK (Amplitude Shift Keying). Two modulation indexes are used, 10% and

100%. The M24LR64-R decodes both. The VCD determines which index is used.

The modulation index is defined as [a – b]/[a + b] where a is the peak signal amplitude and

b, the minimum signal amplitude of the carrier frequency.

Depending on the choice made by the VCD, a “pause” will be created as described in

Figure 14 and Figure 15.

The M24LR64-R is operational for any degree of modulation index from between 10% and

30%.

Figure 14. 100% modulation waveform

t₁

t₃

Carrier

Amplitude

t₄

105%

a

95%

60%

t₂

5%

b

t

Min (μs) Max (μs)

9,44

t1

4,5

0,8

t1

t2

t3

t4

6,0

2,1

0

The clock recovery shall be operational after t₄max.

ai15793

Table 16. 10% modulation parameters

Symbol

Parameter definition

Value

hr

hf

0.1 x (a – b)

max

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Communication signal from VCD to M24LR64-R

Figure 15. 10% modulation waveform

Carrier

Amplitude

t1

t2

t3

y

hf

a

b

hr

y

t

Min

Max

9,44 μs

t1

t2

t3

6,0 μs

3,0 μs

0

4,5 μs

y

0,05 (a-b)

0,1 (a-b) max

Modulation

Index

10%

30%

hf, hr

The VICC shall be operational for any value of modulation index between 10 % and 30 %.

ai15794

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Data rate and data coding

M24LR64-R

9

Data rate and data coding

The data coding implemented in the M24LR64-R uses pulse position modulation. Both data

coding modes that are described in the ISO15693 are supported by the M24LR64-R. The

selection is made by the VCD and indicated to the M24LR64-R within the start of frame

(SOF).

9.1

Data coding mode: 1 out of 256

The value of one single byte is represented by the position of one pause. The position of the

pause on 1 of 256 successive time periods of 18.88 µs (256/f ), determines the value of the

C

byte. In this case the transmission of one byte takes 4.833 ms and the resulting data rate is

1.65 kbit/s (f /8192).

C

Figure 16 illustrates this pulse position modulation technique. In this figure, data E1h (225

decimal) is sent by the VCD to the M24LR64-R.

The pause occurs during the second half of the position of the time period that determines

the value, as shown in Figure 17.

A pause during the first period transmits the data value 00h. A pause during the last period

transmit the data value FFh (255 decimal).

Figure 16. 1 out of 256 coding mode

9.44 μs

Pulse

Modulated

Carrier

18.88 μs

0

1

2

3

. .

.

2

5

.

2

5

2

5

3

2

5

4

2

5

. .

.

4.833 ms

AI06656

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Data rate and data coding

Figure 17. Detail of a time period

9.44 μs

18.88 μs

Pulse

Modulated

Carrier

.

2

4

2

5

2

6

Time Period

one of 256

AI06657

9.2

Data coding mode: 1 out of 4

The value of 2 bits is represented by the position of one pause. The position of the pause on

1 of 4 successive time periods of 18.88 µs (256/f ), determines the value of the 2 bits. Four

C

successive pairs of bits form a byte, where the least significant pair of bits is transmitted first.

In this case the transmission of one byte takes 302.08 µs and the resulting data rate is

26.48 kbit/s (f /512). Figure 18 illustrates the 1 out of 4 pulse position technique and coding.

C

Figure 19 shows the transmission of E1h (225d - 1110 0001b) by the VCD.

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Data rate and data coding

M24LR64-R

Figure 18. 1 out of 4 coding mode

Pulse position for "00"

9.44 μs

75.52 μs

Pulse position for "01" (1=LSB)

28.32 μs

9.44 μs

75.52 μs

Pulse position for "10" (0=LSB)

47.20μs

75.52 μs

9.44 μs

Pulse position for "11"

66.08 μs

9.44 μs

75.52 μs

AI06658

Figure 19. 1 out of 4 coding example

ꢌꢂ

ꢂꢂ

ꢂꢌ

ꢌꢌ

ꢆ ꢇꢄ ꢉꢊꢋ

ꢁꢂ

ꢃ

ꢄ

ꢅ

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M24LR64-R

Data rate and data coding

9.3

VCD to M24LR64-R frames

Frames are delimited by a start of frame (SOF) and an end of frame (EOF). They are

implemented using code violation. Unused options are reserved for future use.

The M24LR64-R is ready to receive a new command frame from the VCD 311.5 µs (t ) after

2

sending a response frame to the VCD.

The M24LR64-R takes a power-up time of 0.1 ms after being activated by the powering

field. After this delay, the M24LR64-R is ready to receive a command frame from the VCD.

9.4

Start of frame (SOF)

The SOF defines the data coding mode the VCD is to use for the following command frame.

The SOF sequence described in Figure 20 selects the 1 out of 256 data coding mode. The

SOF sequence described in Figure 21 selects the 1 out of 4 data coding mode. The EOF

sequence for either coding mode is described in Figure 22.

Figure 20. SOF to select 1 out of 256 data coding mode

ꢇꢁꢁꢉꢊꢋ

ꢀ ꢇꢆ ꢉꢊꢋ

ꢁꢂ

ꢃ

ꢌ

Figure 21. SOF to select 1 out of 4 data coding mode

ꢅꢇꢆꢆꢉꢃꢄ ꢅꢇꢆꢆꢉꢃꢄ

ꢅꢇꢆꢆꢉꢃꢄ

ꢁꢂꢇꢂꢀꢉꢃꢄ

ꢃꢂ

ꢀ

ꢂ

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Data rate and data coding

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Figure 22. EOF for either data coding mode

ꢇꢁꢁꢉꢊꢋ

ꢀ ꢇꢆ ꢉꢊꢋ

ꢁꢂꢃꢃꢃꢄ

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M24LR64-R

Communications signal from M24LR64-R to VCD

10

Communications signal from M24LR64-R to VCD

The M24LR64-R has several modes defined for some parameters, owing to which it can

operate in different noise environments and meet different application requirements.

10.1

Load modulation

The M24LR64-R is capable of communication to the VCD via an inductive coupling area

whereby the carrier is loaded to generate a subcarrier with frequency f . The subcarrier is

S

generated by switching a load in the M24LR64-R.

The load-modulated amplitude received on the VCD antenna must be of at least 10mV

when measured as described in the test methods defined in International Standard

ISO10373-7.

10.2

10.3

Subcarrier

The M24LR64-R supports the one-subcarrier and two-subcarrier response formats. These

formats are selected by the VCD using the first bit in the protocol header. When one

subcarrier is used, the frequency f of the subcarrier load modulation is 423.75 kHz (f /32).

S1

C

When two subcarriers are used, the frequency f is 423.75 kHz (f /32), and frequency f

S1

C

S2

is 484.28 kHz (f /28). When using the two-subcarrier mode, the M24LR64-R generates a

C

continuous phase relationship between f and f

.

S1

S2

Data rates

The M24LR64-R can respond using the low or the high data rate format. The selection of

the data rate is made by the VCD using the second bit in the protocol header. It also

supports the x2 mode available on all the Fast commands. Table 17 shows the different data

rates produced by the M24LR64-R using the different response format combinations.

Table 17. Response data rates

Data rate

One subcarrier

Two subcarriers

Standard commands

Fast commands

6.62 kbit/s (f_c/2048)

13.24 kbit/s (f_c/1024)

26.48 kbit/s (f_c/512)

52.97 kbit/s (f_c/256)

6.67 kbit/s (f_c/2032)

not applicable

Low

Standard commands

Fast commands

26.69 kbit/s (f_c/508)

not applicable

High

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Bit representation and coding

M24LR64-R

11

Bit representation and coding

Data bits are encoded using Manchester coding, according to the following schemes. For

the low data rate, same subcarrier frequency or frequencies is/are used, in this case the

number of pulses is multiplied by 4 and all times will increase by this factor. For the Fast

commands using one subcarrier, all pulse numbers and times are divided by 2.

11.1

Bit coding using one subcarrier

11.1.1

High data rate

A logic 0 starts with 8 pulses at 423.75 kHz (f /32) followed by an unmodulated time of

C

18.88 µs as shown in Figure 23.

Figure 23. Logic 0, high data rate

ꢀ ꢇꢆ ꢉꢁꢂ

ꢄꢌꢈꢂꢆꢃ

For the fast commands, a logic 0 starts with 4 pulses at 423.75 kHz (f /32) followed by an

C

unmodulated time of 9.44 µs as shown in Figure 24.

Figure 24. Logic 0, high data rate x2

ꢌꢅꢇꢅꢅꢉꢅꢇ

ꢆꢈꢌꢈꢂꢀꢀ

A logic 1 starts with an unmodulated time of 18.88 µs followed by 8 pulses at 423.75 kHz

(f /32) as shown in Figure 25.

C

Figure 25. Logic 1, high data rate

ꢀꢁꢂꢁꢃꢄꢅꢆ

ꢇꢈꢉꢊꢋꢁꢁ

For the Fast commands, a logic 1 starts with an unmodulated time of 9.44 µs followed by

4 pulses of 423.75 kHz (f /32) as shown in Figure 26.

C

Figure 26. Logic 1, high data rate x2

ꢉꢀꢂꢀꢀꢄꢅꢆ

ꢇꢈꢉꢊꢋꢁꢂ

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Bit representation and coding

11.1.2

Low data rate

A logic 0 starts with 32 pulses at 423.75 kHz (f /32) followed by an unmodulated time of

C

75.52 µs as shown in Figure 27.

Figure 27. Logic 0, low data rate

ꢌꢆ ꢇꢂꢁꢉꢊꢋ

ꢁꢌꢈꢂꢂꢃ

For the Fast commands, a logic 0 starts with 16 pulses at 423.75 kHz (f /32) followed by an

C

unmodulated time of 37.76 µs as shown in Figure 28.

Figure 28. Logic 0, low data rate x2

ꢁꢀꢂꢀꢊꢄꢌꢁ

ꢂꢃꢉꢊꢋꢃꢄ

A logic 1 starts with an unmodulated time of 75.52 µs followed by 32 pulses at 423.75 kHz

(f /32) as shown in Figure 29.

C

Figure 29. Logic 1, low data rate

ꢌꢄ ꢇꢂꢅꢉꢆꢂ

ꢄꢌꢈꢂꢆꢂ

For the Fast commands, a logic 1 starts with an unmodulated time of 37.76 µs followed by

16 pulses at 423.75 kHz (f /32) as shown in Figure 29.

C

Figure 30. Logic 1, low data rate x2

ꢂ ꢇꢄ ꢉꢅꢇ

ꢆꢈꢌꢈꢂꢂꢌ

11.2

11.3

Bit coding using two subcarriers

High data rate

A logic 0 starts with 8 pulses at 423.75 kHz (f /32) followed by 9 pulses at 484.28 kHz

C

(f /28) as shown in Figure 31. For the Fast commands, the x2 mode is not available.

C

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Bit representation and coding

M24LR64-R

Figure 31. Logic 0, high data rate

ꢀꢀꢇꢁꢂꢉꢊꢋ

ꢄꢌꢈꢂꢀꢁ

A logic 1 starts with 9 pulses at 484.28 kHz (f /28) followed by 8 pulses at 423.75 kHz

C

(f /32) as shown in Figure 32. For the Fast commands, the x2 mode is not available.

C

Figure 32. Logic 1, high data rate

ꢅꢀꢇꢁꢂꢉꢊꢋ

ꢄꢌꢈꢂꢀꢅ

11.4

Low data rate

A logic 0 starts with 32 pulses at 423.75 kHz (f /32) followed by 36 pulses at 484.28 kHz

C

(f /28) as shown in Figure 33. For the Fast commands, the x2 mode is not available.

C

Figure 33. Logic 0, low data rate

ꢌꢅ ꢇꢇꢅꢉꢊꢋ

ꢄꢌꢈꢂꢂꢈ

A logic 1 starts with 36 pulses at 484.28 kHz (f /28) followed by 32 pulses at 423.75 kHz

C

(f /32) as shown in Figure 34. For the Fast commands, the x2 mode is not available.

C

Figure 34. Logic 1, low data rate

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ꢅꢌꢈꢂꢆꢆ

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M24LR64-R to VCD frames

12

M24LR64-R to VCD frames

Frames are delimited by an SOF and an EOF. They are implemented using code violation.

Unused options are reserved for future use. For the low data rate, the same subcarrier

frequency or frequencies is/are used. In this case the number of pulses is multiplied by 4.

For the Fast commands using one subcarrier, all pulse numbers and times are divided by 2.

12.1

12.2

SOF when using one subcarrier

High data rate

The SOF includes an unmodulated time of 56.64 µs, followed by 24 pulses at 423.75 kHz

(f /32), and a logic 1 that consists of an unmodulated time of 18.88 µs followed by 8 pulses

C

at 423.75 kHz as shown in Figure 35.

Figure 35. Start of frame, high data rate, one subcarrier

ꢌꢌꢅꢇꢈꢇꢉꢆꢂ

ꢅꢆꢂꢆꢇꢄꢈꢀ

ꢄꢌꢈꢂꢂꢇ

For the Fast commands, the SOF comprises an unmodulated time of 28.32 µs, followed by

12 pulses at 423.75 kHz (f /32), and a logic 1 that consists of an unmodulated time of

C

9.44µs followed by 4 pulses at 423.75 kHz as shown in Figure 36.

Figure 36. Start of frame, high data rate, one subcarrier x2

ꢆꢂꢇꢂꢂꢉꢎꢈ

ꢌꢁꢇꢁꢁꢉꢎꢂ

ꢈꢇꢌꢈꢂꢀꢀ

12.3

Low data rate

The SOF comprises an unmodulated time of 226.56 µs, followed by 96 pulses at 423.75

kHz (f /32), and a logic 1 that consists of an unmodulated time of 75.52 µs followed by 32

C

pulses at 423.75 kHz as shown in Figure 37.

Figure 37. Start of frame, low data rate, one subcarrier

ꢁꢂꢀꢂꢉꢊꢄꢃꢄ

ꢉꢂꢉꢂꢋꢁꢄꢃꢄ

ꢄꢅ

ꢆ

ꢇ

ꢈ

ꢇ

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M24LR64-R to VCD frames

M24LR64-R

For the Fast commands, the SOF comprises an unmodulated time of 113.28 µs, followed by

48 pulses at 423.75 kHz (f /32), and a logic 1 that includes an unmodulated time of 37.76

C

µs followed by 16 pulses at 423.75 kHz as shown in Figure 38.

Figure 38. Start of frame, low data rate, one subcarrier x2

ꢈꢈ ꢇꢄ ꢉꢊꢋ

ꢆ ꢇꢄ ꢉꢊꢋ

ꢄꢌꢈꢂꢉꢌ

12.4

12.5

SOF when using two subcarriers

High data rate

The SOF comprises 27 pulses at 484.28 kHz (f /28), followed by 24 pulses at 423.75 kHz

C

(f /32), and a logic 1 that includes 9 pulses at 484.28 kHz followed by 8 pulses at

C

423.75 kHz as shown in Figure 39.

For the Fast commands, the x2 mode is not available.

Figure 39. Start of frame, high data rate, two subcarriers

ꢄ

ꢌꢌ ꢇꢅꢀꢉꢎꢂ

ꢅꢀꢇꢌꢍꢉꢎꢂ

ꢋꢌꢈꢂꢁꢈ

12.6

Low data rate

The SOF comprises 108 pulses at 484.28 kHz (f /28), followed by 96 pulses at 423.75 kHz

C

(f /32), and a logic 1 that includes 36 pulses at 484.28 kHz followed by 32 pulses at

C

423.75 kHz as shown in Figure 40.

For the Fast commands, the x2 mode is not available.

Figure 40. Start of frame, low data rate, two subcarriers

ꢁꢁꢅꢂꢂꢃꢄꢍꢎ

ꢉꢁꢅꢂꢄꢁꢄꢍꢎ

ꢆꢇꢉꢊꢋꢄꢀ

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M24LR64-R to VCD frames

12.7

EOF when using one subcarrier

High data rate

12.8

The EOF comprises a logic 0 that includes 8 pulses at 423.75 kHz and an unmodulated time

of 18.88 µs, followed by 24 pulses at 423.75 kHz (f /32), and by an unmodulated time of

C

56.64 µs as shown in Figure 41.

Figure 41. End of frame, high data rate, one subcarriers

ꢅꢀꢇꢀꢍꢉꢍꢃ

ꢌꢌꢅꢇꢈꢁꢉꢍꢃ

ꢅꢌꢈꢂꢁꢌ

For the Fast commands, the EOF comprises a logic 0 that includes 4 pulses at 423.75 kHz

and an unmodulated time of 9.44 µs, followed by 12 pulses at 423.75 kHz (f /32) and an

C

unmodulated time of 37.76 µs as shown in Figure 42.

Figure 42. End of frame, high data rate, one subcarriers x2

ꢀꢁꢂꢁꢂꢄꢌꢃ

ꢉꢆꢂꢆꢆꢄꢌꢃ

ꢄꢅꢉꢊꢋꢆꢀ

12.9

Low data rate

The EOF comprises a logic 0 that includes 32 pulses at 423.75 kHz and an unmodulated

time of 75.52 µs, followed by 96 pulses at 423.75 kHz (f /32) and an unmodulated time of

C

226.56 µs as shown in Figure 43.

Figure 43. End of frame, low data rate, one subcarriers

ꢁꢂꢀꢂꢉꢊꢄꢇꢈ

ꢉꢂꢉꢂꢋꢁꢄꢇꢈ

ꢅꢆꢉꢊꢋꢄꢃ

For the Fast commands, the EOF comprises a logic 0 that includes 16 pulses at 423.75 kHz

and an unmodulated time of 37.76 µs, followed by 48 pulses at 423.75 kHz (f /32) and an

C

unmodulated time of 113.28 µs as shown in Figure 44.

Figure 44. End of frame, low data rate, one subcarriers x2

ꢁꢀꢂꢀꢊꢄꢌꢃ

ꢊꢊꢃꢂꢀꢃꢄꢌꢃ

ꢄꢅꢉꢊꢋꢆꢁ

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M24LR64-R

12.10

12.11

EOF when using two subcarriers

High data rate

The EOF comprises a logic 0 that includes 8 pulses at 423.75 kHz and 9 pulses at

484.28 kHz, followed by 24 pulses at 423.75 kHz (f /32) and 27 pulses at 484.28 kHz

C

(f /28) as shown in Figure 45.

C

For the Fast commands, the x2 mode is not available.

Figure 45. End of frame, high data rate, two subcarriers

ꢅꢀꢇꢌꢍꢉꢎꢂ

ꢌꢌ ꢇꢅꢀꢉꢎꢂ

ꢋꢌ

ꢈ

ꢂ

ꢁ

12.12

Low data rate

The EOF comprises a logic 0 that includes 32 pulses at 423.75 kHz and 36 pulses at

484.28 kHz, followed by 96 pulses at 423.75 kHz (f /32) and 108 pulses at 484.28 kHz

C

(f /28) as shown in Figure 46.

C

For the Fast commands, the x2 mode is not available.

Figure 46. End of frame, low data rate, two subcarriers

ꢌꢂꢀꢇꢉꢂꢉꢍꢃ

ꢂꢂꢀꢇꢆꢍꢉꢍꢃ

ꢅꢌ

ꢈ

ꢂ

ꢉ

ꢀ

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M24LR64-R

Unique identifier (UID)

13

Unique identifier (UID)

The M24LR64-R is uniquely identified by a 64-bit unique identifier (UID). This UID complies

with ISO/IEC 15963 and ISO/IEC 7816-6. The UID is a read-only code and comprises:

•

8 MSBs with a value of E0h

The IC manufacturer code of ST 02h, on 8 bits (ISO/IEC 7816-6/AM1)

a unique serial number on 48 bits

Table 18. UID format

MSB

LSB

63

56 55

48 47

0

0xE0

0x02

Unique serial number

With the UID each M24LR64-R can be addressed uniquely and individually during the

anticollision loop and for one-to-one exchanges between a VCD and an M24LR64-R.

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Application family identifier (AFI)

M24LR64-R

14

Application family identifier (AFI)

The AFI (application family identifier) represents the type of application targeted by the VCD

and is used to identify, among all the M24LR64-Rs present, only the M24LR64-Rs that meet

the required application criteria.

Figure 47. M24LR64-R decision tree for AFI

Inventory request

received

No

AFI flag

set?

Yes

No

AFI value

= 0?

Yes

AFI value

= Internal

value?

No

Yes

Answer given by the M24LR64

to the Inventory request

No answer

AI15130V2

The AFI is programmed by the M24LR64-R issuer (or purchaser) in the AFI register. Once

programmed and Locked, it can no longer be modified.

The most significant nibble of the AFI is used to code one specific or all application families.

The least significant nibble of the AFI is used to code one specific or all application

subfamilies. Subfamily codes different from 0 are proprietary.

(See ISO 15693-3 documentation)

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Data storage format identifier (DSFID)

15

Data storage format identifier (DSFID)

The data storage format identifier indicates how the data is structured in the M24LR64-R

memory. The logical organization of data can be known instantly using the DSFID. It can be

programmed and locked using the Write DSFID and Lock DSFID commands.

15.1

CRC

The CRC used in the M24LR64-R is calculated as per the definition in ISO/IEC 13239. The

initial register contents are all ones: “FFFF”.

The two-byte CRC are appended to each request and response, within each frame, before

the EOF. The CRC is calculated on all the bytes after the SOF up to the CRC field.

Upon reception of a request from the VCD, the M24LR64-R verifies that the CRC value is

valid. If it is invalid, the M24LR64-R discards the frame and does not answer to the VCD.

Upon reception of a Response from the M24LR64-R, it is recommended that the VCD

verifies whether the CRC value is valid. If it is invalid, actions to be performed are left to the

discretion of the VCD designer.

The CRC is transmitted least significant byte first. Each byte is transmitted least significant

bit first.

Table 19. CRC transmission rules

LSByte

MSByte

LSBit

MSBit LSBit

MSBit

CRC 16 (8 bits)

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M24LR64-R protocol description

M24LR64-R

16

M24LR64-R protocol description

The transmission protocol (or simply protocol) defines the mechanism used to exchange

instructions and data between the VCD and the M24LR64-R, in both directions. It is based

on the concept of “VCD talks first”.

This means that an M24LR64-R will not start transmitting unless it has received and

properly decoded an instruction sent by the VCD. The protocol is based on an exchange of:

•

a request from the VCD to the M24LR64-R

a response from the M24LR64-R to the VCD

Each request and each response are contained in a frame. The frame delimiters (SOF,

EOF) are described in Section 12: M24LR64-R to VCD frames.

Each request consists of:

•

a request SOF (see Figure 20 and Figure 21)

flags

a command code

parameters, depending on the command

application data

a 2-byte CRC

a request EOF (see Figure 22)

Each response consists of:

•

an answer SOF (see Figure 35 to Figure 40)

flags

parameters, depending on the command

application data

a 2-byte CRC

an answer EOF (see Figure 41 to Figure 46)

The protocol is bit-oriented. The number of bits transmitted in a frame is a multiple of eight

(8), that is an integer number of bytes.

A single-byte field is transmitted least significant bit (LSBit) first. A multiple-byte field is

transmitted least significant byte (LSByte) first, each byte is transmitted least significant bit

(LSBit) first.

The setting of the flags indicates the presence of the optional fields. When the flag is set (to

one), the field is present. When the flag is reset (to zero), the field is absent.

Table 20. VCD request frame format

Command

code

Request

EOF

Request SOF Request_flags

Parameters

Data

2-byte CRC

Table 21. M24LR64-R Response frame format

Response

SOF

Response

EOF

Response_flags

Parameters

Data

2-byte CRC

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M24LR64-R protocol description

Figure 48. M24LR64-R protocol timing

Request

frame

Request

frame

VCD

(Table 20)

Response

frame

Response

frame

M24LR64-R

(Table 21)

Timing

<-t₁->

<-t₂->

<-t₁->

<-t₂->

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M24LR64-R states

M24LR64-R

17

M24LR64-R states

An M24LR64-R can be in one of 4 states:

•

Power-off

Ready

Quiet

Selected

Transitions between these states are specified in Figure 49: M24LR64-R state transition

diagram and Table 22: M24LR64-R response depending on Request_flags.

17.1

17.2

17.3

17.4

Power-off state

The M24LR64-R is in the Power-off state when it does not receive enough energy from the

VCD.

Ready state

The M24LR64-R is in the Ready state when it receives enough energy from the VCD. When

in the Ready state, the M24LR64-R answers any request where the Select_flag is not set.

Quiet state

When in the Quiet state, the M24LR64-R answers any request except for Inventory requests

with the Address_flag set.

Selected state

In the Selected state, the M24LR64-R answers any request in all modes (see Section 18:

Modes):

•

Request in Select mode with the Select_flag set

Request in Addressed mode if the UID matches

Request in Non-Addressed mode as it is the mode for general requests

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M24LR64-R states

Table 22. M24LR64-R response depending on Request_flags

Address_flag Select_flag

0

Flags

1

0

1

Non

selected

Addressed Non addressed

Selected

M24LR64-R in Ready or Selected

state (Devices in Quiet state do not

answer)

X

M24LR64-R in Selected state

X

M24LR64-R in Ready, Quiet or

Selected state (the device which

matches the UID)

X

Error (03h)

Figure 49. M24LR64-R state transition diagram

Power-off

In field

Out of field

after t_{RF_OFF}

Any other Command

Ready

where Select_Flag

is not set

Out of RF field

after t_{RF_OFF}

Out of RF field

after t_{RF_OFF}

Select (UID)

Quiet

Selected

Stay quiet(UID)

Any other command where the

Address_Flag is set AND

where Inventory_Flag is not set

Any other command

AI06681b

1. The M24LR64-R returns to the “Power Off” state only when both conditions are met: the V_CCpin is not

supplied (0 V or HiZ) and the tag is out of the RF field. Please refer to application note AN3057 for more

information.

2. The intention of the state transition method is that only one M24LR64-R should be in the selected state at a

time.

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Modes

M24LR64-R

18

Modes

The term “mode” refers to the mechanism used in a request to specify the set of M24LR64-

Rs that will answer the request.

18.1

Addressed mode

When the Address_flag is set to 1 (Addressed mode), the request contains the Unique ID

(UID) of the addressed M24LR64-R.

Any M24LR64-R that receives a request with the Address_flag set to 1 compares the

received Unique ID to its own. If it matches, then the M24LR64-R executes the request (if

possible) and returns a response to the VCD as specified in the command description.

If the UID does not match, then it remains silent.

18.2

18.3

Non-addressed mode (general request)

When the Address_flag is cleared to 0 (Non-Addressed mode), the request does not contain

a Unique ID. Any M24LR64-R receiving a request with the Address_flag cleared to 0

executes it and returns a response to the VCD as specified in the command description.

Select mode

When the Select_flag is set to 1 (Select mode), the request does not contain an M24LR64-

R Unique ID. The M24LR64-R in the Selected state that receives a request with the

Select_flag set to 1 executes it and returns a response to the VCD as specified in the

command description.

Only M24LR64-Rs in the Selected state answer a request where the Select_flag set to 1.

The system design ensures in theory that only one M24LR64-R can be in the Select state at

a time.

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Request format

19

Request format

The request consists of:

•

an SOF

flags

a command code

parameters and data

a CRC

an EOF

Table 23. General request format

Command code Parameters

S

O

F

E

O

F

Request_flags

Data

CRC

19.1

Request flags

In a request, the “flags” field specifies the actions to be performed by the M24LR64-R and

whether corresponding fields are present or not.

The flags field consists of eight bits. The bit 3 (Inventory_flag) of the request flag defines the

contents of the 4 MSBs (bits 5 to 8). When bit 3 is reset (0), bits 5 to 8 define the M24LR64-

R selection criteria. When bit 3 is set (1), bits 5 to 8 define the M24LR64-R Inventory

parameters.

Table 24. Definition of request flags 1 to 4

Bit No

Flag

Level

Description

0

1

0

1

0

1

0

1

A single subcarrier frequency is used by the M24LR64-R

Two subcarrier are used by the M24LR64-R

Low data rate is used

Bit 1

Subcarrier_flag⁽¹⁾

Bit 2

Bit 3

Bit 4

Data_rate_flag⁽²⁾

Inventory_flag

High data rate is used

The meaning of flags 5 to 8 is described in Table 25

The meaning of flags 5 to 8 is described in Table 26

No Protocol format extension

Protocol_extension_flag

Protocol format extension

1. Subcarrier_flag refers to the M24LR64-R-to-VCD communication.

2. Data_rate_flag refers to the M24LR64-R-to-VCD communication

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Request format

M24LR64-R

.

Table 25. Request flags 5 to 8 when Bit 3 = 0

Bit No

Flag

Level

Description

Request is executed by any M24LR64-R according to the setting of

Address_flag

0

1

0

Bit 5

Select flag⁽¹⁾

Request is executed only by the M24LR64-R in Selected state

Request is not addressed. UID field is not present. The request is

executed by all M24LR64-Rs.

Address

flag⁽¹⁾

Bit 6

Request is addressed. UID field is present. The request is executed

only by the M24LR64-R whose UID matches the UID specified in

the request.

1

0

1

0

Option not activated.

Bit 7

Bit 8

Option flag

RFU

Option activated.

-

1. If the Select_flag is set to 1, the Address_flag is set to 0 and the UID field is not present in the request.

Table 26. Request flags 5 to 8 when Bit 3 = 1

Bit No

Bit 5

Flag

Level

Description

0

1

0

1

0

AFI field is not present

AFI flag

AFI field is present

16 slots

Bit 6

Nb_slots flag

1 slot

Bit 7

Bit 8

Option flag

RFU

-

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Response format

20

Response format

The response consists of:

•

an SOF

flags

parameters and data

a CRC

an EOF

Table 27. General response format

S

E

O

F

Response_flags

Parameters

Data

CRC

O

F

20.1

Response flags

In a response, the flags indicate how actions have been performed by the M24LR64-R and

whether corresponding fields are present or not. The response flags consist of eight bits.

Table 28. Definitions of response flags 1 to 8

Bit No

Flag

Error_flag

Level

Description

0

1

0

No error

Bit 1

Error detected. Error code is in the “Error” field.

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 8

RFU

-

RFU

-

Extension flag

RFU

No extension

-

RFU

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Response format

M24LR64-R

20.2

Response error code

If the Error_flag is set by the M24LR64-R in the response, the Error code field is present and

provides information about the error that occurred.

Error codes not specified in Table 29 are reserved for future use.

Table 29. Response error code definition

Error code

Meaning

02h

03h

0Fh

10h

11h

12h

13h

14h

15h

The command is not recognized, for example a format error occurred

The option is not supported

Error with no information given

The specified block is not available

The specified block is already locked and thus cannot be locked again

The specified block is locked and its contents cannot be changed.

The specified block was not successfully programmed

The specified block was not successfully locked

The specified block is read-protected

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Anticollision

21

Anticollision

The purpose of the anticollision sequence is to inventory the M24LR64-Rs present in the

VCD field using their unique ID (UID).

The VCD is the master of communications with one or several M24LR64-Rs. It initiates

M24LR64-R communication by issuing the Inventory request.

The M24LR64-R sends its response in the determined slot or does not respond.

21.1

Request parameters

When issuing the Inventory Command, the VCD:

•

sets the Nb_slots_flag as desired

adds the mask length and the mask value after the command field

The mask length is the number of significant bits of the mask value.

The mask value is contained in an integer number of bytes. The mask length indicates

the number of significant bits. LSB is transmitted first

•

If the mask length is not a multiple of 8 (bits), as many 0 bits as required will be added

to the mask value MSB so that the mask value is contained in an integer number of

bytes

The next field starts at the next byte boundary.

Table 30. Inventory request format

MSB

SOF

LSB

EOF

Request_

flags

Optional

AFI

Mask

length

Command

8 bits

Mask value

0 to 8 bytes

CRC

8 bits

16 bits

In the example of the Table 31 and Figure 50, the mask length is 11 bits. Five 0 bits are

added to the mask value MSB. The 11-bit Mask and the current slot number are compared

to the UID.

Table 31. Example of the addition of 0 bits to an 11-bit mask value

(b₁₅) MSB

LSB (b₀)

0000 0

100 1100 1111

0 bits added

11-bit mask value

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Anticollision

M24LR64-R

Figure 50. Principle of comparison between the mask, the slot number and the UID

MSB

LSB

Mask value received in the Inventory command

0000 0100 1100 1111

16 bits

b

MSB

LSB

The Mask value less the padding 0s is loaded

into the Tag comparator

100 1100 1111 11 bits

b

MSBLSB

The Slot counter is calculated

Nb_slots_flags = 0 (16 slots), Slot Counter is 4 bits

xxxx

4 bits

The Slot counter is concatened to the Mask value

Nb_slots_flags = 0

MSB

LSB

xxxx 100 1100 1111 15 bits

b

UID

b63

b0

b

The concatenated result is compared with

the least significant bits of the Tag UID.

xxxx xxxx ..... xxxx xxxx x xxx xxxx xxxx xxxx

64 bits

Bits ignored

Compare

AI06682

The AFI field is present if the AFI_flag is set.

The pulse is generated according to the definition of the EOF in ISO/IEC 15693-2.

The first slot starts immediately after the reception of the request EOF. To switch to the next

slot, the VCD sends an EOF.

The following rules and restrictions apply:

•

if no M24LR64-R answer is detected, the VCD may switch to the next slot by sending

an EOF,

•

if one or more M24LR64-R answers are detected, the VCD waits until the complete

frame has been received before sending an EOF for switching to the next slot.

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Request processing by the M24LR64-R

22

Request processing by the M24LR64-R

Upon reception of a valid request, the M24LR64-R performs the following algorithm:

•

NbS is the total number of slots (1 or 16)

SN is the current slot number (0 to 15)

LSB (value, n) function returns the n Less Significant Bits of value

MSB (value, n) function returns the n Most Significant Bits of value

“&” is the concatenation operator

Slot_Frame is either an SOF or an EOF

SN = 0

if (Nb_slots_flag)

then NbS = 1

SN_length = 0

endif

else NbS = 16

SN_length = 4

endif

label1:

if LSB(UID, SN_length + Mask_length) =

LSB(SN,SN_length)&LSB(Mask,Mask_length)

then answer to inventory request

endif

wait (Slot_Frame)

if Slot_Frame = SOF

then Stop Anticollision

decode/process request

exit

endif

if Slot_Frame = EOF

if SN < NbS-1

then SN = SN + 1

goto label1

exit

endif

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Explanation of the possible cases

M24LR64-R

23

Explanation of the possible cases

Figure 51 summarizes the main possible cases that can occur during an anticollision

sequence when the slot number is 16.

The different steps are:

•

The VCD sends an Inventory request, in a frame terminated by an EOF. The number of

slots is 16.

M24LR64-R_1 transmits its response in Slot 0. It is the only one to do so, therefore no

collision occurs and its UID is received and registered by the VCD;

•

The VCD sends an EOF in order to switch to the next slot.

In slot 1, two M24LR64-Rs, M24LR64-R_2 and M24LR64-R_3 transmit a response,

thus generating a collision. The VCD records the event and remembers that a collision

was detected in Slot 1.

•

The VCD sends an EOF in order to switch to the next slot.

In Slot 2, no M24LR64-R transmits a response. Therefore the VCD does not detect any

M24LR64-R SOF and decides to switch to the next slot by sending an EOF.

•

In slot 3, there is another collision caused by responses from M24LR64-R_4 and

M24LR64-R_5

The VCD then decides to send a request (for instance a Read Block) to M24LR64-R_1

whose UID has already been correctly received.

All M24LR64-Rs detect an SOF and exit the anticollision sequence. They process this

request and since the request is addressed to M24LR64-R_1, only M24LR64-R_1

transmits a response.

•

All M24LR64-Rs are ready to receive another request. If it is an Inventory command,

the slot numbering sequence restarts from 0.

Note:

The decision to interrupt the anticollision sequence is made by the VCD. It could have

continued to send EOFs until Slot 16 and only then sent the request to M24LR64-R_1.

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Explanation of the possible cases

Figure 51. Description of a possible anticollision sequence

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Inventory Initiated command

M24LR64-R

24

Inventory Initiated command

The M24LR64-R provides a special feature to improve the inventory time response of

moving tags using the Initiate_flag value. This flag, controlled by the Initiate command,

allows tags to answer to Inventory Initiated commands.

For applications in which multiple tags are moving in front of a reader, it is possible to miss

tags using the standard inventory command. The reason is that the inventory sequence has

to be performed on a global tree search. For example, a tag with a particular UID value may

have to wait the run of a long tree search before being inventoried. If the delay is too long,

the tag may be out of the field before it has been detected.

Using the Initiate command, the inventory sequence is optimized. When multiple tags are

moving in front of a reader, the ones which are within the reader field will be initiated by the

Initiate command. In this case, a small batch of tags will answer to the Inventory Initiated

command which will optimize the time necessary to identify all the tags. When finished, the

reader has to issue a new Initiate command in order to initiate a new small batch of tags

which are new inside the reader field.

It is also possible to reduce the inventory sequence time using the Fast Initiate and Fast

Inventory Initiated commands. These commands allow the M24LR64-Rs to increase their

response data rate by a factor of 2, up to 53 kbit/s.

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Timing definition

25

Timing definition

25.1

25.2

t₁: M24LR64-R response delay

Upon detection of the rising edge of the EOF received from the VCD, the M24LR64-R waits

for a time t before transmitting its response to a VCD request or before switching to the

1nom

next slot during an inventory process. Values of t are given in Table 32. The EOF is defined

in Figure 22 on page 46.

1

t₂: VCD new request delay

t is the time after which the VCD may send an EOF to switch to the next slot when one or

2

more M24LR64-R responses have been received during an Inventory command. It starts

from the reception of the EOF from the M24LR64-Rs.

The EOF sent by the VCD may be either 10% or 100% modulated regardless of the

modulation index used for transmitting the VCD request to the M24LR64-R.

t is also the time after which the VCD may send a new request to the M24LR64-R as

2

described in Table 48: M24LR64-R protocol timing.

Values of t are given in Table 32.

2

25.3

t₃: VCD new request delay in the absence of a response from

the M24LR64-R

t is the time after which the VCD may send an EOF to switch to the next slot when no

3

M24LR64-R response has been received.

The EOF sent by the VCD may be either 10% or 100% modulated regardless of the

modulation index used for transmitting the VCD request to the M24LR64-R.

From the time the VCD has generated the rising edge of an EOF:

•

If this EOF is 100% modulated, the VCD waits a time at least equal to t

sending a new EOF.

before

3min

•

If this EOF is 10% modulated, the VCD waits a time at least equal to the sum of t

the M24LR64-R nominal response time (which depends on the M24LR64-R data rate

and subcarrier modulation mode) before sending a new EOF.

+

3min

(1)

Table 32. Timing values

Minimum (min) values

Nominal (nom) values

Maximum (max) values

t₁

t₂

t₃

318.6 µs

309.2 µs

320.9 µs

No t_nom

323.3 µs

No t_max

t_1max⁽²⁾+ t_SOF

(3)

1. The tolerance of specific timings is ± 32/f_C.

2. _1maxdoes not apply for write alike requests. Timing conditions for write alike requests are defined in the

t

command description.

3. t_SOFis the time taken by the M24LR64-R to transmit an SOF to the VCD. t_SOFdepends on the current data

rate: High data rate or Low data rate.

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Commands codes

M24LR64-R

26

Commands codes

The M24LR64-R supports the commands described in this section. Their codes are given in

Table 33.

Table 33. Command codes

Command code

standard

Command code

custom

Function

Get Multiple Block Security

Status

01h

Inventory

2Ch

02h

20h

21h

23h

25h

26h

27h

28h

29h

2Ah

2Bh

Stay Quiet

B1h

B2h

B3h

C0h

C1h

C2h

C3h

D1h

D2h

Write-sector Password

Lock-sector Password

Present-sector Password

Fast Read Single Block

Fast Inventory Initiated

Fast Initiate

Read Single Block

Write Single Block

Read Multiple Block

Select

Reset to Ready

Write AFI

Fast Read Multiple Block

Inventory Initiated

Lock AFI

Write DSFID

Lock DSFID

Initiate

Get System Info

26.1

Inventory

When receiving the Inventory request, the M24LR64-R runs the anticollision sequence. The

Inventory_flag is set to 1. The meaning of flags 5 to 8 is shown in Table 26: Request flags 5

to 8 when Bit 3 = 1.

The request contains:

•

the flags,

the Inventory command code (see Table 33: Command codes)

the AFI if the AFI flag is set

the mask length

the mask value

the CRC

The M24LR64-R does not generate any answer in case of error.

Table 34. Inventory request format

Request

SOF

Optional

AFI

Mask

length

Mask

value

Request

EOF

Request_flags Inventory

8 bits 01h

CRC16

8 bits

0 - 64 bits

16 bits

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Commands codes

The response contains:

•

the flags

the Unique ID

Table 35. Inventory response format

Response Response_

Response

DSFID

UID

CRC16

EOF

SOF

flags

8 bits

64 bits

16 bits

During an Inventory process, if the VCD does not receive an RF M24LR64-R response, it

waits a time t before sending an EOF to switch to the next slot. t starts from the rising edge

3

of the request EOF sent by the VCD.

•

If the VCD sends a 100% modulated EOF, the minimum value of t is:

3

t min = 4384/f (323.3 µs) + t

3

C

SOF

•

If the VCD sends a 10% modulated EOF, the minimum value of t is:

3

t min = 4384/f (323.3 µs) + t

3

C

NRT

where:

•

t

is the time required by the M24LR64-R to transmit an SOF to the VCD

is the nominal response time of the M24LR64-R

SOF

NRT

t

and t

are dependent on the M24LR64-R-to-VCD data rate and subcarrier

SOF

NRT

modulation mode.

26.2

Stay Quiet

Command code = 0x02

On receiving the Stay Quiet command, the M24LR64-R enters the Quiet State if no error

occurs, and does NOT send back a response. There is NO response to the Stay Quiet

command even if an error occurs.

When in the Quiet state:

•

the M24LR64-R does not process any request if the Inventory_flag is set,

the M24LR64-R processes any Addressed request

The M24LR64-R exits the Quiet State when:

•

it is reset (power off),

receiving a Select request. It then goes to the Selected state,

receiving a Reset to Ready request. It then goes to the Ready state.

Table 36. Stay Quiet request format

Request

SOF

Request

EOF

Request flags

Stay Quiet

UID

CRC16

8 bits

02h

64 bits

16 bits

The Stay Quiet command must always be executed in Addressed mode (Select_flag is reset

to 0 and Address_flag is set to 1).

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Commands codes

M24LR64-R

Figure 52. Stay Quiet frame exchange between VCD and M24LR64-R

Stay Quiet

request

VCD

SOF

EOF

M24LR64-R

Timing

26.3

Read Single Block

On receiving the Read Single Block command, the M24LR64-R reads the requested block

and sends back its 32-bit value in the response. The Protocol_extention_flag should be set

to 1 for the M24LR64-R to operate correctly. If the Protocol_extention_flag is at 0, the

M24LR64-R answers with an error code. The Option_flag is supported.

Table 37. Read Single Block request format

Request Request_ Read Single

Block

number

Request

EOF

UID⁽¹⁾

CRC16

SOF

flags

Block

8 bits

20h

64 bits

16 bits

1. Gray means that the field is optional.

Request parameters:

•

Option_flag

UID (optional)

Block number

Table 38. Read Single Block response format when Error_flag is NOT set

Sector

Response

SOF

Response

EOF

Response_flags

security

Data

CRC16

status⁽¹⁾

8 bits

32 bits

16 bits

1. Gray means that the field is optional.

Response parameters:

•

Sector security status if Option_flag is set (see Table 39: Sector security status)

4 bytes of block data

Table 39. Sector security status

b₇

b₆

b₅

b₄

b₃

b₂

b₁

b₀

0: Current sector not locked

1: Current sector locked

Reserved for future

use. All at 0

password

control bits

Read / Write

protection bits

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Commands codes

Table 40. Read Single Block response format when Error_flag is set

Response Response_

Response

EOF

Error code

CRC16

SOF

flags

8 bits

16 bits

Response parameter:

Error code as Error_flag is set

•

–

03h: the option is not supported

0Fh: error with no information given

10h: the specified block is not available

15h: the specified block is read-protected

Figure 53. Read Single Block frame exchange between VCD and M24LR64-R

Read Single Block

VCD

SOF

EOF

request

Read Single Block

response

M24LR64-R

<-t₁-> SOF

EOF

26.4

Write Single Block

On receiving the Write Single Block command, the M24LR64-R writes the data contained in

the request to the requested block and reports whether the write operation was successful

in the response. The Protocol_extention_flag should be set to 1 for the M24LR64-R to

operate correctly. If the Protocol_extention_flag is at 0, the M24LR64-R answers with an

error code. The Option_flag is supported.

During the RF write cycle W , there should be no modulation (neither 100% nor 10%).

t

Otherwise, the M24LR64-R may not program correctly the data into the memory. The W

t

time is equal to t

+ 18 × 302 µs.

1nom

Table 41. Write Single Block request format

Write

Single

Block

Request Request_

Block

number

Request

EOF

UID⁽¹⁾

Data

CRC16

SOF

flags

8 bits

21h

64 bits

16 bits

32 bits

16 bits

1. Gray means that the field is optional.

Request parameters:

•

UID (optional)

Block number

Data

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M24LR64-R

Table 42. Write Single Block response format when Error_flag is NOT set

Response SOF Response_flags

8 bits

CRC16

Response EOF

16 bits

Response parameter:

No parameter. The response is send back after the writing cycle.

•

Table 43. Write Single Block response format when Error_flag is set

Response Response_

Response

EOF

Error code

CRC16

SOF

flags

8 bits

16 bits

Response parameter:

Error code as Error_flag is set:

•

–

03h: the option is not supported

0Fh: error with no information given

10h: the specified block is not available

12h: the specified block is locked and its contents cannot be changed.

13h: the specified block was not successfully programmed

Figure 54. Write Single Block frame exchange between VCD and M24LR64-R

Write Single

Block request

VCD

SOF

EOF

Write Single

Block response

Write sequence when

error

M24LR64-R

<-t₁-> SOF

EOF

Write Single

EOF

M24LR64-R

<------------------- W_t---------------> SOF

Block response

26.5

Read Multiple Block

When receiving the Read Multiple Block command, the M24LR64-R reads the selected

blocks and sends back their value in multiples of 32 bits in the response. The blocks are

numbered from '00h to '7FFh' in the request and the value is minus one (–1) in the field. For

example, if the “number of blocks” field contains the value 06h, 7 blocks are read. The

maximum number of blocks is fixed at 32 assuming that they are all located in the same

sector. If the number of blocks overlaps sectors, the M24LR64-R returns an error code.

The Protocol_extention_flag should be set to 1 for the M24LR64-R to operate correctly. If

the Protocol_extention_flag is at 0, the M24LR64-R answers with an error code.

The Option_flag is supported.

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Commands codes

Table 44. Read Multiple Block request format

Read

Multiple

Block

First

block

number

Request Request_

Number

of blocks

Request

CRC16

UID⁽¹⁾

SOF

flags

EOF

8 bits

23h

64 bits

16 bits

8 bits

16 bits

1. Gray means that the field is optional.

Request parameters:

•

Option_flag

UID (optional)

First block number

Number of blocks

Table 45. Read Multiple Block response format when Error_flag is NOT set

Sector

Response Response_

Response

EOF

security

Data

CRC16

SOF

flags

status⁽¹⁾

8 bits

8 bits⁽²⁾

32 bits⁽²⁾

16 bits

1. Gray means that the field is optional.

2. Repeated as needed.

Response parameters:

•

Sector security status if Option_flag is set (see Table 46: Sector security status)

N blocks of data

Table 46. Sector security status

b₇

b₆

b₅

b₄

b₃

b₂

b₁

b₀

Reserved for future

use. All at 0

password

control bits

Read / Write

protection bits

0: Current sector not locked

1: Current sector locked

Table 47. Read Multiple Block response format when Error_flag is set

Response SOF Response_flags

Error code

CRC16

Response EOF

8 bits

16 bits

Response parameter:

Error code as Error_flag is set:

•

–

03h: the option is not supported

0Fh: error with no information given

10h: the specified block is not available

15h: the specified block is read-protected

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Commands codes

M24LR64-R

Figure 55. Read Multiple Block frame exchange between VCD and M24LR64-R

Read Multiple

Block request

VCD

SOF

EOF

Read Multiple

Block response

M24LR64-R

<-t₁-> SOF

EOF

26.6

Select

When receiving the Select command:

•

if the UID is equal to its own UID, the M24LR64-R enters or stays in the Selected state

and sends a response.

•

if the UID does not match its own, the selected M24LR64-R returns to the Ready state

and does not send a response.

The M24LR64-R answers an error code only if the UID is equal to its own UID. If not, no

response is generated. If an error occurs, the M24LR64-R remains in its current state.

Table 48. Select request format

Request Request_

Request

EOF

Select

UID

CRC16

SOF

flags

8 bits

25h

64 bits

16 bits

Request parameter:

UID

•

Table 49. Select Block response format when Error_flag is NOT set

Response

SOF

Response

EOF

Response_flags

CRC16

8 bits

16 bits

Response parameter:

No parameter.

•

Table 50. Select response format when Error_flag is set

Response Response_

Response

EOF

Error code

CRC16

SOF

flags

8 bits

16 bits

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Commands codes

Response parameter:

Error code as Error_flag is set:

•

–

03h: the option is not supported

0Fh: error with no information given

Figure 56. Select frame exchange between VCD and M24LR64-R

Select

request

VCD

SOF

EOF

Select

response

M24LR64-R

<-t₁-> SOF

EOF

26.7

Reset to Ready

On receiving a Reset to Ready command, the M24LR64-R returns to the Ready state if no

error occurs. In the Addressed mode, the M24LR64-R answers an error code only if the UID

is equal to its own UID. If not, no response is generated.

Table 51. Reset to Ready request format

Request Request_ Reset to

Request

EOF

UID⁽¹⁾

CRC16

SOF

flags

Ready

8 bits

26h

64 bits

16 bits

1. Gray means that the field is optional.

Request parameter:

•

UID (optional)

Table 52. Reset to Ready response format when Error_flag is NOT set

Response

SOF

Response

EOF

Response_flags

CRC16

8 bits

16 bits

Response parameter:

No parameter

•

Table 53. Reset to ready response format when Error_flag is set

Response

EOF

Response_flags

Error code

CRC16

SOF

8 bits

16 bits

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Response parameter:

Error code as Error_flag is set:

•

–

03h: the option is not supported

0Fh: error with no information given

Figure 57. Reset to Ready frame exchange between VCD and M24LR64-R

Reset to

VCD

SOF

Ready

EOF

request

Reset to

Ready

M24LR64-R

<-t₁-> SOF

EOF

response

26.8

Write AFI

On receiving the Write AFI request, the M24LR64-R programs the 8-bit AFI value to its

memory. The Option_flag is supported.

During the RF write cycle W , there should be no modulation (neither 100% nor 10%).

t

Otherwise, the M24LR64-R may not write correctly the AFI value into the memory. The W

t

time is equal to t

+ 18 × 302 µs.

1nom

Table 54. Write AFI request format

UID⁽¹⁾

Request Request Write

Request

EOF

AFI

CRC16

SOF

_flags

AFI

8 bits

27h

64 bits

8 bits

16 bits

1. Gray means that the field is optional.

Request parameter:

•

UID (optional)

AFI

Table 55. Write AFI response format when Error_flag is NOT set

Response

SOF

Response

EOF

Response_flags

CRC16

8 bits

16 bits

Response parameter:

No parameter.

•

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Table 56. Write AFI response format when Error_flag is set

Response Response_

Response

EOF

Error code

CRC16

SOF

flags

8 bits

16 bits

Response parameter:

Error code as Error_flag is set

•

–

03h: the option is not supported

0Fh: error with no information given

12h: the specified block is locked and its contents cannot be changed.

13h: the specified block was not successfully programmed

Figure 58. Write AFI frame exchange between VCD and M24LR64-R

Write AFI

request

VCD

SOF

EOF

Write AFI

response

Write sequence

when error

M24LR64-R

<-t₁-> SOF

EOF

Write AFI

EOF

M24LR64-R

<------------------ W_t--------------> SOF

response

26.9

Lock AFI

On receiving the Lock AFI request, the M24LR64-R locks the AFI value permanently. The

Option_flag is supported.

During the RF write cycle W , there should be no modulation (neither 100% nor 10%).

t

Otherwise, the M24LR64-R may not Lock correctly the AFI value in memory. The W time is

t

equal to t

+ 18 × 302 µs.

1nom

Table 57. Lock AFI request format

UID⁽¹⁾

Request Request_ Lock

Request

EOF

CRC16

SOF

flags

AFI

8 bits

28h

64 bits

16 bits

1. Gray means that the field is optional.

Request parameter:

•

UID (optional)

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Table 58. Lock AFI response format when Error_flag is NOT set

Response

SOF

Response

EOF

Response_flags

CRC16

8 bits

16 bits

Response parameter:

No parameter

•

Table 59. Lock AFI response format when Error_flag is set

Response Response_

Response

EOF

Error code

CRC16

SOF

flags

8 bits

16 bits

Response parameter:

Error code as Error_flag is set

•

–

03h: the option is not supported

0Fh: error with no information given

11h: the specified block is already locked and thus cannot be locked again

14h: the specified block was not successfully locked

Figure 59. Lock AFI frame exchange between VCD and M24LR64-R

LockAFI

request

VCD

SOF

EOF

Lock AFI

response

Lock sequence

when error

M24LR64-R

<-t₁-> SOF

EOF

Lock AFI

response

M24LR64-R

<----------------- W_t-------------> SOF

EOF

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26.10

Write DSFID

On receiving the Write DSFID request, the M24LR64-R programs the 8-bit DSFID value to

its memory. The Option_flag is supported.

During the RF write cycle W , there should be no modulation (neither 100% nor 10%).

t

Otherwise, the M24LR64-R may not write correctly the DSFID value in memory. The W time

t

is equal to t

+ 18 × 302 µs.

1nom

Table 60. Write DSFID request format

Request Request_ Write

Request

EOF

UID⁽¹⁾

DSFID

CRC16

SOF

flags

DSFID

8 bits

29h

64 bits

8 bits

16 bits

1. Gray means that the field is optional.

Request parameter:

•

UID (optional)

DSFID

Table 61. Write DSFID response format when Error_flag is NOT set

Response

SOF

Response

EOF

Response_flags

CRC16

8 bits

16 bits

Response parameter:

No parameter

•

Table 62. Write DSFID response format when Error_flag is set

Response

EOF

Response_flags

Error code

CRC16

SOF

8 bits

16 bits

Response parameter:

Error code as Error_flag is set

•

–

03h: the option is not supported

0Fh: error with no information given

12h: the specified block is locked and its contents cannot be changed.

13h: the specified block was not successfully programmed

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Figure 60. Write DSFID frame exchange between VCD and M24LR64-R

Write DSFID

request

VCD

SOF

EOF

Write DSFID

response

Write sequence

when error

M24LR64-R

<-t₁-> SOF

EOF

Write DSFID

EOF

M24LR64-R

<---------------- W_t------------> SOF

response

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26.11

Lock DSFID

On receiving the Lock DSFID request, the M24LR64-R locks the DSFID value permanently.

The Option_flag is supported.

During the RF write cycle W , there should be no modulation (neither 100% nor 10%).

t

Otherwise, the M24LR64-R may not lock correctly the DSFID value in memory. The W time

t

is equal to t

+ 18 × 302 µs.

1nom

Table 63. Lock DSFID request format

Request Request_ Lock

Request

EOF

UID⁽¹⁾

CRC16

SOF

flags

DSFID

8 bits

2Ah

64 bits

16 bits

1. Gray means that the field is optional.

Request parameter:

•

UID (optional)

Table 64. Lock DSFID response format when Error_flag is NOT set

Response

SOF

Response

EOF

Response_flags

CRC16

8 bits

16 bits

Response parameter:

No parameter.

•

Table 65. Lock DSFID response format when Error_flag is set

Response

EOF

Response_flags

Error code

CRC16

SOF

8 bits

16 bits

Response parameter:

Error code as Error_flag is set:

•

–

03h: the option is not supported

0Fh: error with no information given

11h: the specified block is already locked and thus cannot be locked again

14h: the specified block was not successfully locked

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Figure 61. Lock DSFID frame exchange between VCD and M24LR64-R

LockDSFID

request

VCD

SOF

EOF

Lock DSFID

response

Lock sequence

when error

M24LR64-R

<-t₁-> SOF

EOF

Lock

M24LR64-R

<----------------- W_t-------------> SOF

DSFID

EOF

response

26.12

Get System Info

When receiving the Get System Info command, the M24LR64-R sends back its information

data in the response.The Option_flag is supported and must be reset to 0. The Get System

Info can be issued in both Addressed and Non Addressed modes.

The Protocol_extention_flag should be set to 1 for the M24LR64-R to operate correctly. If

the Protocol_extention_flag is at 0, the M24LR64-R answers with an error code.

Table 66. Get System Info request format

Request Request Get System

Request

EOF

UID⁽¹⁾

CRC16

SOF

_flags

Info

8 bits

2Bh

64 bits

16 bits

1. Gray means that the field is optional.

Request parameter:

•

UID (optional)

Table 67. Get System Info response format when Error_flag is NOT set

Response Response Information

Memory

Size reference

IC

Response

EOF

UID DSFID AFI

CRC16

SOF

_flags

flags

00h

0Fh

64 bits 8 bits 8 bits 0307FFh 2Ch

16 bits

Response parameters:

•

Information flags set to 0Fh. DSFID, AFI, Memory Size and IC reference fields are

present

•

UID code on 64 bits

DSFID value

AFI value

Memory size. The M24LR64-R provides 2048 blocks (07FFh) of 4 byte (03h)

IC reference. Only the 6 MSB are significant.

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Table 68. Get System Info response format when Error_flag is set

Response

SOF

Response

EOF

Response_flags Error code

01h 8 bits

CRC16

16 bits

Response parameter:

Error code as Error_flag is set:

•

–

03h: Option not supported

0Fh: other error

Figure 62. Get System Info frame exchange between VCD and M24LR64-R

Get System Info

VCD

SOF

EOF

request

M24LR64-R

<-t₁-> SOF Get System Info response EOF

26.13

Get Multiple Block Security Status

When receiving the Get Multiple Block Security Status command, the M24LR64-R sends

back the sector security status. The blocks are numbered from '00h to '07FFh' in the request

and the value is minus one (–1) in the field. For example, a value of '06' in the “Number of

blocks” field requests to return the security status of 7 blocks.

The Protocol_extention_flag should be set to 1 for the M24LR64-R to operate correctly. If

the Protocol_extention_flag is at 0, the M24LR64-R answers with an error code.

During the M24LR64-R response, if the internal block address counter reaches 07FFh, it

rolls over to 0000h and the Sector Security Status bytes for that location are sent back to the

reader.

Table 69. Get Multiple Block Security Status request format

Get

Multiple

Block

Security

Status

First

block

number blocks

Number

of CRC16

Request Request

Request

EOF

UID⁽¹⁾

SOF

_flags

8 bits

2Ch

64 bits

16 bits

16 bits 16 bits

1. Gray means that the field is optional.

Request parameter:

•

UID (optional)

First block number

Number of blocks

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Table 70. Get Multiple Block Security Status response format when Error_flag is NOT

set

Response

SOF

Response_

flags

Sector security

status

Response

EOF

CRC16

8 bits

8 bits⁽¹⁾

16 bits

1. Repeated as needed.

Response parameters:

•

Sector security status (see Table 71: Sector security status)

Table 71. Sector security status

b₇

b₆

b₅

b₄

b₃

b₂

b₁

b₀

0: Current sector not locked

1: Current sector locked

Reserved for future use. All password control

Read / Write

protection bits

at 0 bits

Table 72. Get Multiple Block Security Status response format when Error_flag is set

Response

SOF

Response_

flags

Response

EOF

Error code

CRC16

8 bits

16 bits

Response parameter:

Error code as Error_flag is set:

•

–

03h: the option is not supported

0Fh: error with no information given

10h: the specified block is not available

Figure 63. Get Multiple Block Security Status frame exchange between VCD and

M24LR64-R

Get Multiple Block

Security Status

VCD

SOF

EOF

Get Multiple Block

Security Status

M24LR64-R

<-t₁-> SOF

EOF

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26.14

Write-sector Password

On receiving the Write-sector Password command, the M24LR64-R uses the data

contained in the request to write the password and reports whether the operation was

successful in the response. The Option_flag is supported.

During the RF write cycle time, W , there must be no modulation at all (neither 100% nor

t

10%). Otherwise, the M24LR64-R may not correctly program the data into the memory. The

W time is equal to t

+ 18 × 302 µs. After a successful write, the new value of the

t

1nom

selected password is automatically activated. It is not required to present the new password

value until M24LR64-R power-down.

Table 73. Write-sector Password request format

Write-

Request Request

ICMfg

code

Passwor

Request

EOF

sector

UID⁽¹⁾

Data

CRC16

SOF

_flags

d number

Password

8 bits

B1h

02h

64 bits

8 bits

32 bits

16 bits

1. Gray means that the field is optional.

Request parameter:

•

UID (optional)

Password number (01h = Pswd1, 02h = Pswd2, 03h = Pswd3, other = Error)

Data

Table 74. Write-sector Password response format when Error_flag is NOT set

Response

SOF

Response

EOF

Response_flags

CRC16

8 bits

16 bits

Response parameter:

32-bit password value. The response is sent back after the write cycle.

•

Table 75. Write-sector Password response format when Error_flag is set

Response Response_

Response

EOF

Error code

CRC16

SOF

flags

8 bits

16 bits

Response parameter:

Error code as Error_flag is set:

•

–

02h: the command is not recognized, for example: a format error occurred

03h: the option is not supported

0Fh: error with no information given

10h: the specified block is not available

12h: the specified block is locked and its contents cannot be changed.

13h: the specified block was not successfully programmed

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Figure 64. Write-sector Password frame exchange between VCD and M24LR64-R

Write-

sector

Password

request

VCD

SOF

EOF

Write-sector

Password

response

Write sequence

when error

M24LR64-R

<-t₁-> SOF

EOF

Write-

sector

Password

M24LR64-R

<----------------- W_t-------------> SOF

EOF

response

26.15

Lock-sector Password

On receiving the Lock-sector Password command, the M24LR64-R sets the access rights

and permanently locks the selected sector. The Option_flag is supported.

A sector is selected by giving the address of one of its blocks in the Lock-sector Password

request (Sector number field). For example, addresses 0 to 31 are used to select sector 0

and addresses 32 to 63 are used to select sector 1. Care must be taken when issuing the

Lock-sector Password command as all the blocks belonging to the same sector are

automatically locked by a single command.

The Protocol_extention_flag should be set to 1 for the M24LR64-R to operate correctly. If

the Protocol_extention_flag is at 0, the M24LR64-R answers with an error code.

During the RF write cycle W , there should be no modulation (neither 100% nor 10%)

t

otherwise, the M24LR64-R may not correctly lock the memory block.

The W time is equal to t

+ 18 × 302 µs.

t

1nom

Table 76. Lock-sector Password request format

Lock-

sector

Password code

IC

Mfg

Sector

security CRC16

status

Request Request

Sector

number

Request

EOF

UID⁽¹⁾

SOF

_flags

8 bits

B2h 02h

64 bits

16 bits

8 bits

16 bits

1. Gray means that the field is optional.

Request parameters:

•

(optional) UID

Sector number

Sector security status (refer to Table 77)

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Table 77. Sector security status

b₇

0

b₆

0

b₅

b₄

b₃

b₂

b₁

b₀

1

Read / Write protection

bits

0

password control bits

Table 78. Lock-sector Password response format when Error_flag is NOT set

Response

SOF

Response

EOF

Response_flags

CRC16

8 bits

16 bits

Response parameter:

No parameter.

•

Table 79. Lock-sector Password response format when Error_flag is set

Response

SOF

Response_

flags

Response

EOF

Error code

CRC16

8 bits

16 bits

Response parameter:

Error code as Error_flag is set:

•

–

02h: the command is not recognized, for example: a format error occurred

03h: the option is not supported

0Fh: error with no information given

10h: the specified block is not available

11h: the specified block is already locked and thus cannot be locked again

14h: the specified block was not successfully locked

Figure 65. Lock-sector Password frame exchange between VCD and M24LR64-R

Lock-sector

VCD

SOF Password EOF

request

Lock-sector

Password

response

Lock sequence

when error

M24LR64-R

<-t₁-> SOF

EOF

Lock-sector

M24LR64-R

<---------------- W_t------------> SOF Password EOF

response

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26.16

Present-sector Password

On receiving the Present-sector Password command, the M24LR64-R compares the

requested password with the data contained in the request and reports whether the

operation has been successful in the response. The Option_flag is supported.

During the comparison cycle equal to W , there should be no modulation (neither 100% nor

t

10%) otherwise, the M24LR64-R the Password value may not be correctly compared.

The W time is equal to t

+ 18 × 302 µs.

t

1nom

After a successful command, the access to all the memory blocks linked to the password is

changed as described in Section 4.1: M24LR64-R RF block security.

Table 80. Present-sector Password request format

Present-

sector

Password code

IC

Mfg

Request Request

Passwor

d number

Request

EOF

UID⁽¹⁾

Data

CRC16

SOF

_flags

8 bits

B3h 02h

64 bits

8 bits

32 bits

16 bits

1. Gray means that the field is optional.

Request parameter:

•

UID (optional)

Password Number (0x01 = Pswd1, 0x02 = Pswd2, 0x03 = Pswd3, other = Error)

Data

Table 81. Present-sector Password response format when Error_flag is NOT set

Response

SOF

Response

EOF

Response_flags

CRC16

8 bits

16 bits

Response parameter:

No parameter. The response is send back after the write cycle.

•

Table 82. Present-sector Password response format when Error_flag is set

Response

SOF

Response_

flags

Response

EOF

Error code

CRC16

8 bits

16 bits

Response parameter:

Error code as Error_flag is set:

•

–

02h: the command is not recognized, for example: a format error occurred

03h: the option is not supported

0Fh: error with no information given

10h: the specified block is not available

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Figure 66. Present-sector Password frame exchange between VCD and M24LR64-R

Present-

sector

Password

request

VCD

SOF

EOF

Present-

sector

Password

response

sequence when

error

M24LR64-R

<-t₁-> SOF

EOF

Present-

sector

Password

M24LR64-R

<---------------- W_t------------> SOF

EOF

response

26.17

Fast Read Single Block

On receiving the Fast Read Single Block command, the M24LR64-R reads the requested

block and sends back its 32-bit value in the response. The Option_flag is supported. The

data rate of the response is multiplied by 2.

The Protocol_extention_flag should be set to 1 for the M24LR64-R to operate correctly. If

the Protocol_extention_flag is at 0, the M24LR64-R answers with an error code.

Table 83. Fast Read Single Block request format

FastRead

Request Request_

ICMfg

code

Block

Request

EOF

Single

Block

UID⁽¹⁾

CRC16

SOF

flags

number

8 bits

C0h

02h

64 bits

16 bits

1. Gray means that the field is optional.

Request parameters:

•

Option_flag

UID (optional)

Block number

Table 84. Fast Read Single Block response format when Error_flag is NOT set

Sector

Response Response

Response

EOF

security

Data

CRC16

SOF

_flags

status⁽¹⁾

8 bits

32 bits

16 bits

1. Gray means that the field is optional.

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Response parameters:

•

Sector security status if Option_flag is set (see Table 85)

4 bytes of block data

Table 85. Sector security status

b₇

b₆

b₅

b₄

b₃

b₂

b₁

b₀

0: Current sector not locked

1: Current sector locked

Reserved for future used. All password control

Read / Write

protection bits

at 0 bits

Table 86. Fast Read Single Block response format when Error_flag is set

Response

SOF

Response_

flags

Response

EOF

Error code

CRC16

8 bits

16 bits

Response parameter:

Error code as Error_flag is set:

•

–

02h: the command is not recognized, for example: a format error occurred

03h: the option is not supported

0Fh: error with no information given

10h: the specified block is not available

15h: the specified block is read protected

Figure 67. Fast Read Single Block frame exchange between VCD and M24LR64-R

Fast Read Single

Block request

VCD

SOF

EOF

Fast Read Single

Block response

M24LR64-R

<-t₁-> SOF

EOF

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26.18

Fast Inventory Initiated

Before receiving the Fast Inventory Initiated command, the M24LR64-R must have received

an Initiate or a Fast Initiate command in order to set the Initiate_ flag. If not, the M24LR64-R

does not answer to the Fast Inventory Initiated command.

On receiving the Fast Inventory Initiated request, the M24LR64-R runs the anticollision

sequence. The Inventory_flag must be set to 1. The meaning of flags 5 to 8 is shown in

Table 26: Request flags 5 to 8 when Bit 3 = 1. The data rate of the response is multiplied

by 2.

The request contains:

•

the flags,

the Inventory command code

the AFI if the AFI flag is set

the mask length

the mask value

the CRC

The M24LR64-R does not generate any answer in case of error.

Table 87. Fast Inventory Initiated request format

Fast

Request Request

IC Mfg Optional Mask

Request

EOF

Inventory

Initiated

Mask value

CRC16

SOF

_flags

code

AFI

length

8 bits

C1h

02h

8 bits 8 bits

0 - 64 bits

16 bits

The Response contains:

•

the flags

the Unique ID

Table 88. Fast Inventory Initiated response format

Response Response

Response

EOF

DSFID

UID

CRC16

16 bits

SOF

_flags

8 bits

64 bits

During an Inventory process, if the VCD does not receive an RF M24LR64-R response, it

waits a time t before sending an EOF to switch to the next slot. t starts from the rising edge

3

of the request EOF sent by the VCD.

•

If the VCD sends a 100% modulated EOF, the minimum value of t is:

3

t min = 4384/f (323.3 µs) + t

3

C

SOF

•

If the VCD sends a 10% modulated EOF, the minimum value of t is:

3

t min = 4384/f (323.3 µs) + t

3

C

NRT

where:

•

t

is the time required by the M24LR64-R to transmit an SOF to the VCD

is the nominal response time of the M24LR64-R

SOF

NRT

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t

and t

are dependent on the M24LR64-R-to-VCD data rate and subcarrier

SOF

NRT

modulation mode.

26.19

Fast Initiate

On receiving the Fast Initiate command, the M24LR64-R will set the internal Initiate_flag

and send back a response only if it is in the Ready state. The command has to be issued in

the Non Addressed mode only (Select_flag is reset to 0 and Address_flag is reset to 0). If an

error occurs, the M24LR64-R does not generate any answer. The Initiate_flag is reset after

a power off of the M24LR64-R. The data rate of the response is multiplied by 2.

The request contains:

•

No data

Table 89. Fast Initiate request format

Request

SOF

Fast

Initiate

IC Mfg

Code

Request

EOF

Request_flags

CRC16

8 bits

C2h

02h

16 bits

The response contains:

•

the flags

the Unique ID

Table 90. Fast Initiate response format

Response Response

Response

EOF

DSFID

UID

CRC16

SOF

_flags

8 bits

64 bits

16 bits

Figure 68. Fast Initiate frame exchange between VCD and M24LR64-R

VCD

SOF Fast Initiate request EOF

Fast Initiate

response

M24LR64-R

<-t₁-> SOF

EOF

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26.20

Fast Read Multiple Block

On receiving the Fast Read Multiple Block command, the M24LR64-R reads the selected

blocks and sends back their value in multiples of 32 bits in the response. The blocks are

numbered from '00h to '7FFh' in the request and the value is minus one (–1) in the field. For

example, if the “number of blocks” field contains the value 06h, 7 blocks are read. The

maximum number of blocks is fixed to 32 assuming that they are all located in the same

sector. If the number of blocks overlaps sectors, the M24LR64-R returns an error code.

The Protocol_extention_flag should be set to 1 for the M24LR64-R to operate correctly. If

the Protocol_extention_flag is at 0, the M24LR64-R answers with an error code.

The Option_flag is supported. The data rate of the response is multiplied by 2.

Table 91. Fast Read Multiple Block request format

Fast

First

block

number blocks

Number

of

Request Request_

Read

Multiple code

Block

ICMfg

Request

EOF

UID⁽¹⁾

CRC16

SOF

flags

8 bits

C3h

02h

64 bits

16 bits 8 bits

16 bits

1. Gray means that the field is optional.

Request parameters:

•

Option_flag

UID (Optional)

First block number

Number of blocks

Table 92. Fast Read Multiple Block response format when Error_flag is NOT set

Sector

Response Response_

Response

EOF

security

Data

CRC16

SOF

flags

status⁽¹⁾

8 bits

8 bits⁽²⁾

32 bits⁽²⁾

16 bits

1. Gray means that the field is optional.

2. Repeated as needed.

Response parameters:

•

Sector security status if Option_flag is set (see Table 93: Sector security status if

Option_flag is set)

•

N block of data

Table 93. Sector security status if Option_flag is set

b₇

b₆

b₅

b₄

b₃

b₂

b₁

b₀

Reserved for future use.

All at 0

password

control bits

Read / Write 0: Current sector not locked

protection bits 1: Current sector locked

DocID15170 Rev 16

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Commands codes

M24LR64-R

Table 94. Fast Read Multiple Block response format when Error_flag is set

Response SOF Response_flags

8 bits

Error code

CRC16

Response EOF

8 bits

16 bits

Response parameter:

Error code as Error_flag is set:

•

–

0Fh: other error

10h: block address not available

Figure 69. Fast Read Multiple Block frame exchange between VCD and M24LR64-R

Fast Read

VCD

SOF Multiple Block EOF

request

Fast Read

<-t₁-> SOF Multiple Block EOF

response

M24LR64-R

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DocID15170 Rev 16

M24LR64-R

Commands codes

26.21

Inventory Initiated

Before receiving the Inventory Initiated command, the M24LR64-R must have received an

Initiate or a Fast Initiate command in order to set the Initiate_ flag. If not, the M24LR64-R

does not answer to the Inventory Initiated command.

On receiving the Inventory Initiated request, the M24LR64-R runs the anticollision

sequence. The Inventory_flag must be set to 1. The meaning of flags 5 to 8 is given in

Table 26: Request flags 5 to 8 when Bit 3 = 1.

The request contains:

•

the flags,

the Inventory Command code

the AFI if the AFI flag is set

the mask length

the mask value

the CRC

The M24LR64-R does not generate any answer in case of error.

Table 95. Inventory Initiated request format

IC

Request Request Inventory

Optional Mask

Request

EOF

Mfg

Mask value

CRC16

SOF

_flags

Initiated

AFI

length

code

8 bits

D1h

02h

8 bits

0 - 64 bits

16 bits

The response contains:

•

the flags

the Unique ID

Table 96. Inventory Initiated response format

Response Response

Response

EOF

DSFID

UID

CRC16

16 bits

SOF

_flags

8 bits

64 bits

During an Inventory process, if the VCD does not receive an RF M24LR64-R response, it

waits a time t before sending an EOF to switch to the next slot. t starts from the rising edge

3

of the request EOF sent by the VCD.

•

If the VCD sends a 100% modulated EOF, the minimum value of t is:

3

t min = 4384/f (323.3 µs) + t

3

C

SOF

•

If the VCD sends a 10% modulated EOF, the minimum value of t is:

3

t min = 4384/f (323.3 µs) + t

3

C

NRT

where:

•

t

is the time required by the M24LR64-R to transmit an SOF to the VCD

is the nominal response time of the M24LR64-R

SOF

NRT

t

and t

are dependent on the M24LR64-R-to-VCD data rate and subcarrier

SOF

NRT

modulation mode.

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Commands codes

M24LR64-R

26.22

Initiate

On receiving the Initiate command, the M24LR64-R will set the internal Initiate_flag and

send back a response only if it is in the ready state. The command has to be issued in the

Non Addressed mode only (Select_flag is reset to 0 and Address_flag is reset to 0). If an

error occurs, the M24LR64-R does not generate any answer. The Initiate_flag is reset after

a power off of the M24LR64-R.

The request contains:

•

No data

Table 97. Initiate request format

IC Mfg

Request

SOF

Request

EOF

Request_flags

Initiate

CRC16

code

8 bits

D2h

02h

16 bits

The response contains:

•

the flags

the Unique ID

Table 98. Initiate Initiated response format

Response Response

Response

EOF

DSFID

UID

CRC16

SOF

_flags

8 bits

64 bits

16 bits

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DocID15170 Rev 16

M24LR64-R

Commands codes

Figure 70. Initiate frame exchange between VCD and M24LR64-R

Initiate

request

VCD

SOF

EOF

Initiate

response

M24LR64-R

<-t₁-> SOF

EOF

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Maximum rating

M24LR64-R

27

Maximum rating

Stressing the device above the rating listed in the absolute maximum ratings table may

cause permanent damage to the device. These are stress ratings only and operation of the

device at these or any other conditions above those indicated in the operating sections of

this specification is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability. Refer also to the STMicroelectronics SURE

Program and other relevant quality documents.

Table 99. Absolute maximum ratings

Symbol

Parameter

Min.

Max.

Unit

T_A

Ambient operating temperature

–40

15

85

25

°C

T_STG

h_STG, t_STG

,

Sawn wafer on UV

tape

6⁽¹⁾

months

Storage conditions

kept in its original packing

form

UFDFPN8 (MLP8),

SO8, TSSOP8

T_STG

Storage temperature

–65

150

°C

Lead temperature during

soldering

UFDFPN8 (MLP8),

SO8, TSSOP8

T_LEAD

see note ⁽²⁾

V_IO

I²C input or output range

I²C supply voltage

–0.50

6.0

V

V_CC

RF input voltage between AC0

and AC1

V_MAX

–7

7

V

AC0, AC1

–800

800

Electrostatic discharge voltage

(human body model)⁽³⁾

Other pads

–3000

3000

V_ESD

V

Electrostatic discharge voltage on

antenna⁽⁴⁾

AC0, AC1

–3000

–100

3000

100

Electrostatic discharge voltage (Machine model)

1. Counted from ST shipment date.

2. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK^®

7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)

2002/95/EU.

3. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω)

4. Compliant with the IEC 61000-4-2 method. M24LR64-R is mounted on ST’s reference antenna ANT1-

M24LR-A.

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M24LR64-R

I C DC and AC parameters

2

28

I C DC and AC parameters

This section summarizes the operating and measurement conditions, and the DC and AC

2

characteristics of the device in I C mode. The parameters in the DC and AC characteristic

tables that follow are derived from tests performed under the measurement conditions

summarized in the relevant tables. Designers should check that the operating conditions in

their circuit match the measurement conditions when relying on the quoted parameters.

2

Table 100. I C operating conditions

Symbol

Parameter

Min.

Max.

Unit

V_CC

T_A

Supply voltage

Ambient operating temperature

1.8

5.5

85

V

–40

°C

Table 101. AC test measurement conditions

Parameter Min.

Symbol

Max.

Unit

C_L

Load capacitance

100

pF

ns

V

Input rise and fall times

Input levels

50

-

0.2V_CCto 0.8V_CC

0.3V_CCto 0.7V_CC

Input and output timing reference levels

V

Figure 71. AC test measurement I/O waveform

Input Levels

Input and Output

Timing Reference Levels

0.8V

CC

0.7V

CC

0.3V

CC

0.2V

CC

ai00825b

Table 102. Input parameters

Parameter

Input capacitance (SDA)

Symbol

Min.

Max.

Unit

C_IN

-

8

6

pF

ns

Input capacitance (other pins)

(1)

t_NS

Pulse width ignored (Input filter on SCL and SDA)

80

1. Characterized only.

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2

I C DC and AC parameters

M24LR64-R

2

Table 103. I C DC characteristics

Symbol

Parameter

Test condition

Min.

Max.

Unit

Input leakage current

(SCL, SDA, E1, E0)

V_IN= V_SSor V_CC

device in Standby mode

I_LI

-

± 2

µA

SDA in Hi-Z, external voltage

applied on SDA: VSS or VCC

I_LO

Output leakage current

-

µA

V_CC= 1.8 V, f_c= 400 kHz

(rise/fall time < 50 ns)

100

200

500

V

_CC= 2.5 V, f_c= 400 kHz

(rise/fall time < 50 ns)

I_CC

Supply current (Read)⁽¹⁾

V_CC= 5.5 V, f_c= 400 kHz

(rise/fall time < 50 ns)

During t_W, V_CC= 1.8 V

During t_W, V_CC= 2.5 V

During t_W, V_CC= 5.5 V

-

300⁽²⁾

400⁽²⁾

700⁽²⁾

I_CC0

Supply current (Write)⁽¹⁾

Standby supply current

µA

V

V_IN= V_SSor V_CC

V_CC= 1.8 V

-

30

40

V_IN= V_SSor V_CC

I_CC1

V_CC= 2.5 V

V_IN= V_SSor V_CC

V_CC= 5.5 V

V_CC= 1.8 V

V_CC= 2.5 V

V_CC= 5.5 V

V_CC= 1.8 V

–0.45 0.25V_CC

Input low voltage (SDA,

SCL)

V_IL

–0.45

0.3V_CC

0.75V_CCV_CC+1

0.7V_CCV_CC+1

Input high voltage (SDA,

SCL)

V_IH

V_CC= 2.5 V

V

V_CC= 5.5 V

I_OL= 2.1 mA, V_CC= 1.8 V or

I_OL= 3 mA, V_CC= 5.5 V

V_OL

Output low voltage

-

0.4

1. SCL, SDA according to AC input waveform Figure 71. E0, E1 connected to Ground or V_CC

2. Characterized value, not tested in production.

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M24LR64-R

I C DC and AC parameters

2

Table 104. I C AC characteristics

Test conditions specified in Table 100

Symbol

Alt.

Parameter

Min.

Max.

Unit

f_C

f_SCLClock frequency

-

400

kHz

ns

ms

t_CHCL

t_CLCH

t_HIGHClock pulse width high

t_LOWClock pulse width low

600

1300

20

-

(1)

t_XH1XH2

t_R

t_F

Input signal rise time

Input signal fall time

SDA (out) fall time

300

(1)

t_XL1XL2

t_DL1DL2

t_DXCX

20

300

20

100

t_SU:DATData in set up time

t_HD:DATData in hold time

100

0

-

t_CLDX

-

t_CLQX

t_DH

t_AA

Data out hold time

100

600

-

(2)(3)

t_CLQV

t_CHDX

t_DLCL

t_CHDH

t_DHDL

t_W

Clock low to next data valid (access time)

900

(4)

t_SU:STAStart condition set up time

t_HD:STAStart condition hold time

t_SU:STOStop condition set up time

-

t_BUFTime between Stop condition and next Start condition 1300

I²C write time

-

5

1. Values recommended by the I²C-bus Fast-Mode specification.

2. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or

rising edge of SDA.

3. t_CLQVis the time (from the falling edge of SCL) required by the SDA bus line to reach 0.8V_CCin a

compatible way with the I²C specification (which specifies t_SU:DAT(min) = 100 ns), assuming that the R_bus

× C_bustime constant is less than 500 ns (as specified in Figure 4).

4. For a reStart condition, or following a write cycle.

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2

I C DC and AC parameters

M24LR64-R

2

Figure 72. I C AC waveforms

tXL1XL2

tXH1XH2

tCHCL

tCLCH

SCL

tDLCL

tXL1XL2

SDA In

tCHDX

Start

condition

tCLDX

tDXCX

SDA

Change

tXH1XH2

tCHDH tDHDL

Start

SDA

Input

Stop

condition

SCL

SDA In

tW

Write cycle

tCHDH

tCHDX

Stop

condition

Start

condition

tCHCL

SCL

tCLQV

tCLQX

Data valid

tDL1DL2

Data valid

SDA Out

AI00795e

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M24LR64-R

RF electrical parameters

29

RF electrical parameters

This section summarizes the operating and measurement conditions, and the DC and AC

characteristics of the device in RF mode. The parameters in the DC and AC Characteristic

tables that follow are derived from tests performed under the Measurement Conditions

summarized in the relevant tables. Designers should check that the operating conditions in

their circuit match the measurement conditions when relying on the quoted parameters.

(1) (2)

Table 105. RF characteristics

Symbol

Parameter

Condition

Min.

Typ.

Max.

Unit

f_CC

External RF signal frequency

-

13.553 13.56 13.567 MHz

Operating field according

to ISO

H_ISO

T_A= 0 °C to 50 °C

150

-

5000

3500

mA/m

Operating field in extended

temperature range

H_Extended

T_A= –40 °C to 85 °C

10% carrier modulation

index^{(3) (4)}

150 mA/m > H_ISO > 1000 mA/m

15

-

30

MI_CARRIER

%

H_ISO > 1000 mA/m

-

10

MI=(A-B)/(A+B)

t

_RFR, t_RFF10% rise and fall time

0.5

3.0

µs

10% minimum pulse width

for bit

t_RFSBL

-

7.1

-

9.44

MI_CARRIER100% carrier modulation index MI=(A-B)/(A+B)

95

-

100

3.5

%

t_RFR, t_RFF100% rise and fall time

-

0.5

µs

100% minimum pulse width

t_RFSBL

for bit

-

7.1

-

9.44

1

µs

Minimum time from carrier

t_{MIN CD}

From H-field min

0.1

ms

generation to first data

f_SH

f_SL

Subcarrier frequency high

Subcarrier frequency low

F_CC/32

F_CC/28

-

423.75

484.28

-

kHz

Time for M24LR64-R

response

t₁

t₂

4224/F_S

-

318.6 320.9 323.3

µs

Time between commands

309

-

311.5

5.75

314

-

RF write time (including

internal Verify)

W_t

ms

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RF electrical parameters

M24LR64-R

(1) (2)

Table 105. RF characteristics

Condition

(continued)

Min.

Symbol

Parameter

Typ.

Max.

Unit

Internal tuning capacitor in

C_TUN

f = 13.56 MHz

ISO10373-7

24.8

10

27.5

30.2

pF

SO8⁽⁵⁾

Backscattered level as defined

by ISO test

V_BACK

-

mV

Inventory and Read operations

Write operations

-

1.9

2.3

2.6

Vpeak

Minimum operating voltage

between AC0 and AC1⁽⁶⁾

V_MIN

1. T_A= –40 to 85 °C.

2. All timing measurements were performed between 0 °C and 50 °C on a reference antenna with the following

characteristics:

External size: 75 mm x 48 mm

Number of turns: 5

Width of conductor: 0.5 mm

Space between 2 conductors: 0.3 mm

Value of the tuning capacitor in SO8: 27.5 pF (M24LR64-R)

Value of the coil: 5 µH

Tuning frequency: 13.56 MHz.

3. Characterized only, not 100% tested

4. 15% (or more) carrier modulation index offers a better signal/noise ratio and therefore a wider operating range with a better

noise immunity

5. Characterised only, at room temperature only, measured at V_AC0-AC1= 0.5 V peak.

6. Characterized only, at room temperature only.

Table 106. Operating conditions

Symbol

Parameter

Min.

Max.

Unit

T_A

Ambient operating temperature

–40

85

°C

Figure 73 shows an ASK modulated signal, from the VCD to the M24LR64-R. The test

condition for the AC/DC parameters are:

•

Close coupling condition with tester antenna (1 mm)

M24LR64-R performance measured at the tag antenna

Figure 73. M24LR64-R synchronous timing, transmit and receive

t

RFF

A

B

t

RFR

f

CC

t

RFSBL

t

MAX

t

MIN CD

AI06680

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M24LR64-R

Package mechanical data

30

Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

®

ECOPACK packages, depending on their level of environmental compliance. ECOPACK

specifications, grade definitions and product status are available at: www.st.com.

®

ECOPACK is an ST trademark.

Figure 74. SO8N – 8-lead plastic small outline, 150 mils body width, package outline

h x 45°

A2

A

c

ccc

b

e

0.25 mm

GAUGE PLANE

D

k

8

E1

E

L

1

A1

L1

SO-A

1. Drawing is not to scale.

Table 107. SO8N – 8-lead plastic small outline, 150 mils body width, package data

millimeters

Min.

inches⁽¹⁾

Symbol

Typ.

Max.

Typ.

Min.

Max.

A

A1

A2

b

1.75

0.25

0.0689

0.0098

0.10

1.25

0.28

0.17

0.0039

0.0492

0.0110

0.0067

0.48

0.23

0.10

5.00

6.20

4.00

–

0.0189

0.0091

0.0039

0.1969

0.2441

0.1575

–

c

ccc

D

4.90

6.00

3.90

1.27

4.80

5.80

3.80

–

0.1929

0.2362

0.1535

0.0500

0.1890

0.2283

0.1496

–

E

E1

e

h

0.25

0°

0.50

8°

k

0°

8°

L

0.40

1.27

0.0157

0.0500

L1

1.04

0.0410

1. Values in inches are converted from mm and rounded to 4 decimal digits.

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Package mechanical data

M24LR64-R

Figure 75. UFDFPN8 (MLP8) – Ultra thin fine pitch dual flat package no lead 2 x 3 mm,

package outline

MB

e

MC

e

b

D

L1

L3

Pin 1

E2

K

E

E2

K

L

A

D2

eee

A1

ZW_MEe

1. Drawing is not to scale.

Table 108. UFDFPN8 (MLP8) – Ultra thin fine pitch dual flat package no lead 2 x 3 mm,

package mechanical data

Millimeters

Min.

Inches ⁽¹⁾

Symbol

Typ.

Max.

Typ.

Min.

Max.

A

0.55

0.02

0.25

2

0.45

0

0.60

0.05

0.30

2.10

1.70

1.60

3.10

0.30

1.60

−

0.0217

0.0008

0.0098

0.0787

0.0630

−

0.0177

0

0.0236

0.0020

0.0118

0.0827

0.0669

0.0630

0.1220

0.0118

0.0630

−

A1

b

0.20

1.90

1.50

1.20

2.90

0.10

1.20

−

0.0079

0.0748

0.0591

0.0472

0.1142

0.0039

0.0472

−

D

D2 (MB)

1.60

−

D2 (MC)

E

3

0.1181

0.0079

−

E2 (MB)

0.2

−

E2 (MC)

e

K

0.50

−

0.0197

−

0.30

−

0.0118

−

L

−

0.50

0.15

−

0.0197

0.0059

−

L1

−

L3

−

0.30

0.08

−

0.0118

0.0031

eee ⁽²⁾

1. Values in inches are converted from mm and rounded to 4 decimal digits.

2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from

measuring.

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DocID15170 Rev 16

M24LR64-R

Package mechanical data

Figure 76. TSSOP8 – 8-lead thin shrink small outline, package outline

D

8

1

5

4

c

E1

E

a

A1

L

A

A2

L1

CP

b

e

TSSOP8AM

1. Drawing is not to scale.

Table 109. TSSOP8 – 8-lead thin shrink small outline, package mechanical data

millimeters

Min.

inches⁽¹⁾

Symbol

Typ.

Max.

Typ.

Min.

Max.

A

A1

A2

b

1.2

0.15

1.05

0.3

0.2

0.1

3.1

-

0.0472

0.0059

0.0413

0.0118

0.0079

0.0039

0.122

-

0.05

0.8

0.002

0.0315

0.0075

0.0035

1

0.0394

0.19

0.09

c

CP

D

3

0.65

6.4

4.4

0.6

1

2.9

-

0.1181

0.0256

0.252

0.1142

-

e

E

6.2

4.3

0.45

6.6

4.5

0.75

0.2441

0.1693

0.0177

0.2598

0.1772

0.0295

E1

L

0.1732

0.0236

0.0394

L1

a

0°

8°

0°

8°

N

8

1. Values in inches are converted from mm and rounded to 4 decimal digits.

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Part numbering

M24LR64-R

31

Part numbering

Table 110. Ordering information scheme for packaged devices

Example:

M24LR64-R

MN

6

T

/2

Device type

M24LR = dynamic NFC/RFID tag IC

64 = memory size in Kbit

Operating voltage

R = V_CC= 1.8 to 5.5 V

Package

MN = SO8N (150 mils width)

MC = UFDFPN8 (MLP8)

DW = TSSOP8

Device grade

6 = industrial: device tested with standard

test flow over –40 to 85 °C

Option

T = Tape and reel packing

Capacitance

/2 = 27.5 pF

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M24LR64-R

Part numbering

Table 111. Ordering information scheme for bare die devices

M24LR64-R

Example:

S

1

8

5

/2

Device type

M24LR = dynamic NFC/RFID tag IC

64 = memory size in Kbit

Operating voltage

R = V_CC= 1.8 to 5.5 V

Packing

S = Sawn wafer (inkless) in UV tape

Z = Sawn wafer (inked) in UV tape

Wafer orientation

1 = see Note:

Wafer size in inches

8 = 8-inch wafer (see Note:)

Wafer thickness

5 = 140 µm (see Note:)

Capacitance

/2 = 27.5 pF

Note:

Refer to technical note TN0185 for details on the die delivery form.

For a list of available options (speed, package, etc.) or for further information on any aspect

of this device, please contact your nearest ST sales office.

DocID15170 Rev 16

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Anticollision algorithm (informative)

M24LR64-R

Appendix A Anticollision algorithm (informative)

The following pseudocode describes how anticollision could be implemented on the VCD,

using recursivity.

A.1

Algorithm for pulsed slots

function push (mask, address); pushes on private stack

function pop (mask, address); pops from private stack

function pulse_next_pause; generates a power pulse

function store(M24LR64-R_UID); stores M24LR64-R_UID

function poll_loop (sub_address_size as integer)

pop (mask, address)

mask = address & mask; generates new mask

; send the request

mode = anticollision

send_Request (Request_cmd, mode, mask length, mask value)

for sub_address = 0 to (2^sub_address_size - 1)

pulse_next_pause

if no_collision_is_detected ; M24LR64-R is inventoried

then

store (M24LR64-R_UID)

else ; remember a collision was detected

push(mask,address)

endif

next sub_address

if stack_not_empty ; if some collisions have been detected and

then

poll_loop (sub_address_size); recursively to process the

last stored collision

; not yet processed, the function calls itself

endif

end poll_loop

main_cycle:

mask = null

address = null

push (mask, address)

poll_loop(sub_address_size)

end_main_cycle

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CRC (informative)

Appendix B CRC (informative)

B.1

CRC error detection method

The cyclic redundancy check (CRC) is calculated on all data contained in a message, from

the start of the flags through to the end of Data. The CRC is used from VCD to M24LR64-R

and from M24LR64-R to VCD.

Table 112. CRC definition

CRC definition

CRC type

Length

Polynomial

Direction

Preset

Residue

ISO/IEC 13239 16 bits

X

¹⁶+ X¹²+ X⁵+ 1 = 8408h

Backward

FFFFh

F0B8h

To add extra protection against shifting errors, a further transformation on the calculated

CRC is made. The One’s Complement of the calculated CRC is the value attached to the

message for transmission.

To check received messages the 2 CRC bytes are often also included in the re-calculation,

for ease of use. In this case, the expected value for the generated CRC is the residue

F0B8h.

B.2

CRC calculation example

This example in C language illustrates one method of calculating the CRC on a given set of

bytes comprising a message.

C-example to calculate or check the CRC16 according to ISO/IEC 13239

#define POLYNOMIAL0x8408// x^16 + x^12 + x^5 + 1

#define PRESET_VALUE0xFFFF

#define CHECK_VALUE0xF0B8

#define NUMBER_OF_BYTES4// Example: 4 data bytes

#define CALC_CRC1

#define CHECK_CRC0

void main()

{

unsigned int current_crc_value;

unsigned char array_of_databytes[NUMBER_OF_BYTES + 2] = {1, 2, 3,

4, 0x91, 0x39};

int

number_of_databytes = NUMBER_OF_BYTES;

calculate_or_check_crc;

i, j;

calculate_or_check_crc = CALC_CRC;

// calculate_or_check_crc = CHECK_CRC;// This could be an other

example

if (calculate_or_check_crc == CALC_CRC)

{

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CRC (informative)

M24LR64-R

number_of_databytes = NUMBER_OF_BYTES;

// check CRC

}

else

{

}

number_of_databytes = NUMBER_OF_BYTES + 2;

current_crc_value = PRESET_VALUE;

for (i = 0; i < number_of_databytes; i++)

{

current_crc_value = current_crc_value ^ ((unsigned

int)array_of_databytes[i]);

for (j = 0; j < 8; j++)

{

if (current_crc_value & 0x0001)

{

current_crc_value = (current_crc_value >> 1) ^

POLYNOMIAL;

}

else

{

}

current_crc_value = (current_crc_value >> 1);

}

if (calculate_or_check_crc == CALC_CRC)

{

current_crc_value = ~current_crc_value;

printf ("Generated CRC is 0x%04X\n", current_crc_value);

// current_crc_value is now ready to be appended to the data

stream

// (first LSByte, then MSByte)

}

else

{

// check CRC

if (current_crc_value == CHECK_VALUE)

{

printf ("Checked CRC is ok (0x%04X)\n",

current_crc_value);

}

else

{

printf ("Checked CRC is NOT ok (0x%04X)\n",

current_crc_value);

}

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M24LR64-R

Application family identifier (AFI) (informative)

Appendix C Application family identifier (AFI)

(informative)

The AFI (application family identifier) represents the type of application targeted by the VCD

and is used to extract from all the M24LR64-R present only the M24LR64-R meeting the

required application criteria.

It is programmed by the M24LR64-R issuer (the purchaser of the M24LR64-R). Once

locked, it cannot be modified.

The most significant nibble of the AFI is used to code one specific or all application families,

as defined in Table 113.

The least significant nibble of the AFI is used to code one specific or all application

subfamilies. Subfamily codes different from 0 are proprietary.

(1)

Table 113. AFI coding

AFI

Meaning

Most

significant

nibble

Least

significant

nibble

Examples / Note

VICCs respond from

‘0’

‘X’

'X

‘0’

‘1

‘0’

All families and subfamilies

'All subfamilies of family X

Only the Yth subfamily of family X

Proprietary subfamily Y only

Transport

No applicative preselection

'0

Wide applicative preselection

'‘Y’

-

‘Y’

-

'‘0’, ‘Y’

‘0’, ‘Y’

'‘0’, ‘Y’

‘0’, ‘Y’

Mass transit, Bus, Airline,...

'2

Financial

IEP, Banking, Retail,...

'3

Identification

Access Control,...

'4

Telecommunication

Medical

Public Telephony, GSM,...

‘5’

'6

-

Multimedia

Internet services....

'7

Gaming

-

8

Data Storage

Portable Files,...

'9

Item Management

Express Parcels

Postal Services

Airline Bags

-

'A

'B

'C

'D

'E

‘F’

RFU

1. X = '1' to 'F', Y = '1' to 'F'

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Revision history

M24LR64-R

Revision history

.

Table 114. Document revision history

Revision Changes

Date

Added 8” wafer delivery form and update endurance on cover page.

Updated V_CCoverview and replaced diode by regulator in

Section 2.6: Supply voltage (V_CC).

24-Jun-2010

10

Removed RF address column from Table 6: Sector Security Status

Byte area and Table 14: System parameter sector.

Updated h_STGin Table 99: Absolute maximum ratings.

Added Table 111: Ordering information scheme for bare die devices.

Updated Table 111: Ordering information scheme for bare die

devices.

09-Aug-2010

02-Dec-2010

11

12

Updated ISO references under Features.

Updated Section 2.4: Antenna coil (AC0, AC1), Table 99: Absolute

maximum ratings and Table 105: RF characteristics.

Renamed Section 29 and Table 105.

Deleted Table 106 RF DC Characteristics.

27-Oct-2011

05-Jan-2012

13

14

Updated footnote ⁽²⁾of Table 105: RF characteristics.

Modified Table 10: Password system area on page 24.

Added “Dynamic NFC/RFID tag IC” to the title, Section 1:

Description, and the M24LR definition in Table 110 and Table 111.

13-Jun-2013

15

Replaced UFDFPN8 (MB) drawing by UFDFPN8 (MC) drawing on

page 1.

Added MC drawing to Figure 75: UFDFPN8 (MLP8) – Ultra thin fine

pitch dual flat package no lead 2 x 3 mm, package outline.

25-Jul-2013

16

Added “D2 (MC)” and “E2 (MC)” rows to Table 108: UFDFPN8

(MLP8) – Ultra thin fine pitch dual flat package no lead 2 x 3 mm,

package mechanical data.

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型号：	M24LR64-RZ185/2
厂家：	ST
描述：	64-Kbit Dynamic NFC/RFID tag with password protection 可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟内存集成电路
文件：	总121页 (文件大小：3182K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M24LR64-RZ185/2 [STMICROELECTRONICS]

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