PM6681ATR [STMICROELECTRONICS]

Dual step-down controller with adjustable LDO; 可调LDO的双降压控制器


型号：	PM6681ATR
厂家：	ST
描述：	Dual step-down controller with adjustable LDO 可调LDO的双降压控制器稳压器开关式稳压器或控制器电源电路开关式控制器
文件：	总12页 (文件大小：477K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PM6681A

Dual step-down controller with adjustable LDO

Target Specification

Features

■ 6V to 36V input voltage range

■ Adjustable output voltages

■ 0.9-3.3V LDO adjustable delivers 100mA peak

current

■ 5V LDO delivers 100mA peak current

■ 1.237V 1% reference voltage available

VFQFPN-32 (5mm x 5mm)

■ NO R

current sensing using low side

SENSE

MOSFETs' R

DS(on)

Description

■ Negative current limit

PM6681A is a dual step-down controller

specifically designed to provide extremely high

efficiency conversion, with lossless current

sensing technique. The constant on-time

architecture assures fast load transient response

and the embedded voltage feed-forward provides

nearly constant switching frequency operation. An

embedded integrator control loop compensates

the DC voltage error due to the output ripple.

Pulse skipping technique increases efficiency at

very light load. Moreover a minimum switching

frequency of 33kHz is selectable to avoid audio

noise issues. The PM6681A provides a selectable

switching frequency, allowing three different

values of switching frequencies for the two

switching sections. The output voltages OUT1

and OUT2 can be adjusted from 0.9V to 5V and

from 0.9V to 3.3V respectively. The device

provides also 2 LDOs, 5V fixed and 0.9V-3.3V

adjustable.

■ Soft start internally fixed at 2ms

■ Soft output discharge

■ Latched UVP

■ Not-latched OVP

■ Selectable pulse skipping at light loads

■ Selectable minimum frequency(33kHz) in

pulse skip mode

■ 5mW maximum quiescent power

■ Indipendent power good signals

■ Output voltage ripple compensation

Applications

■ Embedded computer system

■ FPGA system power

■ Industrial applications on 24V

■ High performance and high density DC/DC

modules

Order codes

Part number

Package

VFQFPN-32 (5mm x 5mm)

Packaging

PM6681A

Tube

PM6681ATR

VFQFPN-32 (5mm x 5mm)

Tape and Reel

November 2006

Rev 1

1/12

This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.

www.st.com

Contents

PM6681A

Contents

Simplified application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.1

2.2

Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2/12

PM6681A

Simplified application schematic

Figure 1. Simplified application schematic

L E F S

N V I

1 9

P I S K

2 4

5 O L D

1 8

F E V R

3 2

E N

2 5

V C

3 1

E N

3/12

Pin settings

PM6681A

Pin settings

2.1

Connections

Figure 2. Pin connection (top view)

SKIP

SGND

COMP2

FSEL

BOOT1

HGATE1

PHASE1

CSENSE1

EN2

PM6681A

SHDN

FB2

VIN

LDO

LDO5

V5SW

OUT2

4/12

PM6681A

Pin settings

2.2

Functions

Table 1.

N°

Pin functions

Function

Signal ground. Reference for internal logic circuitry. It must be connected to

the signal ground plan of the power supply. The signal ground plan and the

power ground plan must be connected together in one point near the PGND

pin.

SGND1

COMP2

FSEL

DC voltage error compensation pin for the switching section 2

Frequency selection pin. It provides a selectable switching frequency,

allowing three different values of switching frequencies for the switching

sections.

Enable input for the switching section 2.

– The section 2 is enabled applying a voltage greater than 2.4V to this pin.

– The section 2 is disabled applying a voltage lower than 0.8V.

When the section is disabled the High Side gate driver goes low and Low

Side gate driver goes high. If both EN1 and EN2 pins are low and SHDN pin

is high the device enters in standby mode.

EN2

Shutdown control input.

– The device switch off if the SHDN voltage is lower than the device off

thershold (Shutdown mode)

– The device switch on if the SHDN voltage is greater than the device on

SHDN

FB2

threshold.

The SHDN pin can be connected to the battery through a voltage divider to

program an undervoltage lockout. In shutdown mode, the gate drivers of the

two switching sections are in high impedance (high-Z).

Feedback input for the switching section 2 This pin is connected to a

resistive voltage-divider from OUT2 to PGND to adjust the output voltage

from 0.9V to 3.3V.

Adjustable internal regulator output. It can be set from 0.9V to 3.3V. LDO pin

can provide a 100mA peak current.

LDO

Output voltage sense for the switching section 2.This pin must be directly

connected to the output votage of the switching section.

OUT2

Bootstrap capacitor connection for the switching section 2. It supplies the

high-side gate driver.

BOOT2

HGATE2

PHASE2

High-side gate driver ouput for section 2. This is the floating gate driver

output.

Switch node connection and return path for the high side driver for the

section 2. It is also used as negative current sense input.

Positive current sense input for the switching section 2. This pin must be

connected through a resistor to the drain of the synchronous rectifier to

obtain a positive current limit threshold for the power supply controller.

CSENSE2

LGATE2

PGND

Low-side gate driver output for the section 2.

Power ground. This pin must be connected to the power ground plan of the

power supply.

LGATE1

Low-side gate driver output for the section 1.

5/12

Pin settings

PM6681A

Table 1.

N°

Pin functions (continued)

Function

Feedback input for the adjustable internal linear regulator. This pin is

connected to a resistive voltage-divider from LDO to SGND to adjust the

output voltage from 0.9V to 3.3V.

LDO FB

V5SW

Internal 5V regulator bypass connection.

– If V5SW is connected to OUT5 (or to an external 5V supply) and V5SW is

greater than 4.9V, the LDO5 regulator shuts down and the LDO5 pin is

directly connected to OUT5 through a 3W (max) switch.

If V5SW is connected to GND, the LDO5 linear regulator is always on.

5V internal regulator output. It can provide up to 100mA peak current. LDO5

pin supplies embedded low side gate drivers and an external load.

LDO5

VIN

Device supply voltage input and battery voltage sense. A bypass filter (4Ω

and 4.7mF) between the battery and this pin is recommended.

Positive current sense input for the switching section 1. This pin must be

connected through a resistor to the drain of the synchronous rectifier to

obtain a positive current limit threshold for the power supply controller.

CSENSE1

Switch node connection and return path for the high side driver for the

section 1.It is also used as negative current sense input.

PHASE1

HGATE1

BOOT1

High-side gate driver ouput for section 1. This is the floating gate driver

output.

Bootstrap capacitor connection for the switching section 1. It supplies the

high-side gate driver.

Pulse skipping mode control input.

– If the pin is connected to LDO5 the PWM mode is enabled.

– If the pin is connected to GND, the pulse skip mode is enabled.

– If the pin is connected to VREF the pulse skip mode is enabled but the

switching frequency is kept higher than 33KHz (No-audible puse skip

mode).

SKIP

EN1

Enable input for the switching section 1.

– The section 1 is enabled applying a voltage greater than 2.4V to this pin.

– The section 1 is disabled applying a voltage lower than 0.8V.

When the section is disabled the High Side gate driver goes low and Low

Side gate driver goes high.

Power Good ouput signal for the section 1. This pin is an open drain ouput

and when the ouput of the switching section 1 is out of +/- 10% of its

nominal value.It is pulled down.

PGOOD1

PGOOD2

Power Good ouput signal for the section 2. This pin is an open drain ouput

and when the ouput of the switching section 2 is out of +/- 10% of its

nominal value.It is pulled down.

Feedback input for the switching section 1. This pin is connected to a

resistive voltage-divider from OUT1 to PGND to adjust the output voltage

from 0.9V to 5.5V.

FB1

Output voltage sense for the switching section 1.This pin must be directly

connected to the output votage of the switching section.

OUT1

6/12

PM6681A

Pin settings

Table 1.

N°

Pin functions (continued)

Function

COMP1

VCC

DC voltage error compensation pin for the switching section 1.

Device Supply Voltage pin. It supplies all the internal analog circuitry except

the gate drivers (see LDO5). Connect this pin to LDO5.

Internal 1.237V high accuracy voltage reference. It can deliver 50uA.

Bypass to SGND with a 100nF capacitor to reduce noise.

VREF

7/12

Functional block diagram

PM6681A

Functional block diagram

Figure 3. Functional block diagram

8/12

PM6681A

Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK

packages. These packages have a Lead-free second level interconnect. The category of

second Level Interconnect is marked on the package and on the inner box label, in

compliance with JEDEC Standard JESD97. The maximum ratings related to soldering

conditions are also marked on the inner box label. ECOPACK is an ST trademark.

ECOPACK specifications are available at: www.st.com.

Table 2.

VFQFPN 5x5x1.0 32L Pitch 0.50

Databook (mm)

Typ

Dim.

Min

Max

0.8

0.9

0.02

0.05

0.2

0.18

4.85

0.25

0.3

5.15

See exposed pad variations ⁽²⁾

4.85

0.3

5.15

See exposed pad variations ⁽²⁾

0.5

0.4

0.5

ddd

0.05

Table 3.

Exposed pad variations

⁽¹⁾⁽²⁾D2

Min

2.90

Typ

Max

3.20

Min

Typ

Max

3.20

3.10

2.90

3.10

1. VFQFPN stands for Thermally Enhanced Very thin Fine pitch Quad Flat Package No lead. Very thin:

A = 1.00mm Max.

2. Dimensions D2 & E2 are not in accordance with JEDEC.

9/12

Package mechanical data

Figure 4. Package dimensions

PM6681A

10/12

PM6681A

Revision history

Table 4.

Date

02-Nov-2006

Revision history

Revision

Changes

Initial release

11/12

PM6681A

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12/12

PM6681ATR [STMICROELECTRONICS]

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