STE2002_06 [STMICROELECTRONICS]
81 x 128 single-chip LCD controller/driver; 81 ×128的单芯片LCD控制器/驱动器
| 型号： | STE2002_06 |
| 厂家： | 
ST |
| 描述： | 81 x 128 single-chip LCD controller/driver |
| 文件： | 总61页 (文件大小：509K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STE2002
81 x 128 single-chip LCD controller/driver
– Eight selectable temperature compensation
coefficients
Features
■ 104 x 128 bits Display Data RAM
■ Programmable MUX rate
■ Programmable frame rate
■ X,Y Programmable carriage return
■ Dual partial display mode
■ Row by Row Scrolling
■ Designed for chip-on-glass (COG) applications
■ Low power consumption, suitable for battery
operated systems
■ Logic supply voltage range from 1.7 to 3.6V
■ High voltage generator supply voltage range
from 1.75 to 4.2V
■ Display supply voltage range from 4.5 Vto
■ Automatic data RAM Blanking procedure
14.5V
■ Selectable Input interface:
■ Backward compatibility with STE2001
– I2C Bus Fast and Hs-mode (read and write)
– Parallel Interface (read and write)
– Serial Interface (read and write)
Description
■ Fully Integrated oscillator requires no external
The STE2002 is a low power CMOS LCD
controller driver. Designed to drive a 81 rows by
128 columns graphic display, provides all
necessary functions in a single chip, including on-
chip LCD supply and bias voltages generators,
resulting in a minimum of externals components
and in a very low power consumption. The
STE2002 features three standard interfaces
(Serial, Parallel & I2C) for ease of interfacing with
the host microcontroller.
components
■ CMOS compatible inputs
■ Fully integrated configurable LCD bias voltage
generator with:
– Selectable multiplication factor (up to 6 )
X
– Effective sensing for High Precision Output
Block diagram
ICON
CO to C127
R0 to R80
OSC_IN
TIMING
GENERATOR
COLUMN
DRIVERS
ROW
DRIVERS
OSC
OSC_OUT
CLOCK
BIAS VOLTAGE
GENERATOR
VLCDIN
DATA
SHIFT
LATCHES
REGISTER
VLCDSENSE
VLCDOUT
HIGH VOLTAGE
GENERATOR
104 x 128
RAM
SCROLL
LOGIC
RES
RESET
TEST_1_14
VSSAUX
TEST
VDD1,2
VSS
ICON_MODE
EXT
BSY_FLG
DISPLAY
CONTROL
LOGIC
DATA
REGISTER
INSTRUCTION
REGISTER
SEL1,2
SOUT
SA1
2
I
CBUS
PARALLEL
SERIAL
SAO
SCL
SDA_IN SDA_OUT DB0 to DB7 E
PD/C SCE SDIN SCLK SD/C
R/W
December 2006
Rev 3
1/61
www.st.com
61
Contents
STE2002
Contents
1
2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
2.2
2.3
2.4
2.5
2.6
Supplies voltages and grounds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Internal supply voltage generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Bias levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
LCD voltage generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Temperature coefficient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
4
Display data RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1
4.2
4.3
4.4
4.5
4.6
Reset (RES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Power down (PD = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Memory blanking procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Checker board procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Scrolling function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Dual partial display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5
6
Bus interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1
I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1.1 Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.2
5.3
Serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
6.1
6.2
6.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7
Pad coordinates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
2/61
STE2002
Contents
Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
8
9
10
3/61
Pin description
STE2002
1
Pin description
Table 1.
N°
Pin description
Pad
Type
Function
129-169
282-322
R0 to R80
O
LCD Row Driver Output
ICON
C0 to C127
VSS
323
O
O
ICON Row Driver
1-128
LCD Column Driver Output
236-255
GND Ground pads.
VDD1
188-199 Supply IC Positive Power Supply
VDD2
200-211 Supply Internal Generator Supply Voltages.
261-270 Supply LCD Supply Voltages for the Column and Row Output Drivers.
273-282 Supply Voltage Multiplier Output
VLCDIN
VLCDOUT
Voltage Multiplier Regulation Input. VLCDOUT Sensing for Output Voltage Fine
Tuning
VLCDSENSE
271-272 Supply
180, 231,
VSSAUX
SEL1,2
O
Ground Reference for Selection Pins Configuration
218
184,185
183
I
I
Interface Mode Selection
Extended Instruction Set Selection
Ext pad config
Instruction set selected
EXT
VSS or VSSAUX
VDD1
BASIC
EXTENDED
ICON ROW Management
Icon mode pad config
Icon mode status
ICON_MOD
E
186
I
VSS or VSSAUX
VDD1
DISABLED
ENABLED
SDA_IN
SDA_OUT
SCL
234
232
235
182
181
187
260
230
I
O
I
I2C Bus Data In
I2C Bus Data Out
I2C bus Clock
SA0
I
I2C Slave Address BIT 0
I2C Slave Address BIT 1
External Oscillator Input
Internal/External Oscillator Out
Reset Input. Active Low.
Parallel Interface 8 Bit Data Bus
SA1
I
OSCIN
OSCOUT
RES
I
O
I
DB0 to DB7 220-227
I/O
4/61
STE2002
Pin description
Table 1.
N°
Pin description (continued)
Pad
Type
Function
R/W
E
219
229
228
214
217
216
215
213
I
I
Parallel Interface Read & Write Control Line
Parallel Interface Data Latch Signal.
Parallel Interface Data/Command Selector
Serial Interface Data Input
PD/C
SDIN
SCLK
SCE
SD/C
SOUT
I
I
I
Serial Interface Clock
I
Serial Interface ENABLE. When Low the Incoming Data are Clocked In.
Serial Interface Data/Command Selector
Serial Out
I
O
Active Procedure Flag. Notice if There is an ongoing Internal Operation or an
active reset. Active Low.
BSYFLG
212
O
Test Pads. - A 50kohm pull-down resistor is added on input pis.
Test Num.
Pin Configuration
TEST_1
TEST_2
TEST_3
TEST_4
OPEN
TEST_5
TEST_6
TEST_7
TEST_8
TEST_9
170-179,
256-259
T1 to T14
I/O
VSS / VSSAUX
VSS / VSSAUX
TEST_10
TEST_11
TEST_12
TEST_13
TEST_14
5/61
Pin description
Figure 1.
STE2002
Chip mechanical drawing
MARK_1
COL
0
ROW 35
ROW 39.
STE2002
VLCDOUT
VLCDSENSE
VLCDIN
VLCDOUT
VLCDSENSE
VLCDIN
MARK_3
OSCOUT
TEST_14
TEST_13
TEST_12
TEST_11
VSS
SCL
SDAIN
SDAOUT
VSSAUX
COL 63
COL 64
RES
(0,0)
E
PD/C
D0
Y
D1
D2
D3
D4
D5
D6
X
D7
R/W
VSSAUX
SCLK
SCE
SD/C
SDIN
SDOUT
BSY_FLG
MARK_4
VDD2
VDD1
VDD2
VDD1
OSCIN
ICON_MODE
SEL1
SEL2
EXT_SET
SA0
SA1
VSSAUX
TEST_10
TEST_9
TEST_8
TEST_7
TEST_6
TEST_5
TEST_4
TEST_3
TEST_2
TEST_1
ROW 80/ICON
ROW 79
COL 127
ROW 76
MARK_2
6/61
STE2002
Pin description
Figure 2.
Improved ALTH & PLESKO driving method
V
LCD
V
2
V
3
∆V (t)
∆V (t)
2
1
ROW 0
R0 (t)
V
V
4
5
V
SS
V
LCD
V
V
2
3
ROW 1
R1 (t)
V
V
4
5
V
SS
V
LCD
V
V
2
3
COL 0
C0 (t)
V
V
4
5
V
SS
V
LCD
V
V
2
3
COL 1
C1 (t)
V
V
4
5
V
SS
SS
SS
V
LCD
- V
- V
V
3
V
LCD
- V
2
V - V
4 5
V (t)
state1
0V
0V
V
3
- V
SS
V - V
SS 5
V
V
- V
LCD
4
V
LCD
- V
- V
SS
- V
LCD
SS
V
3
SS
V
LCD
- V
2
V
4
- V
5
V (t)
state2
0V
0V
V
3
- V
SS
V
SS
- V
5
V
V
- V
LCD
4
- V
LCD
SS
.......
.......
0
..... 64
1
2
3
4
5
6
7
8
9
..... 64
0
1
2
3
4
5
6
7
8
9
FRAME n
FRAME n + 1
D00IN1154
∆V (t) = C1(t) - R0(t)
1
∆V (t) = C1(t) - R1(t)
2
7/61
Circuit description
STE2002
2
Circuit description
2.1
Supplies voltages and grounds
VDD2 is supply voltages to the internal voltage generator (see below). If the internal voltage
generator is not used, this should be connected to VDD1 pad. VDD1 supplies the rest of the
IC. VDD1 supply voltage could be different form VDD2
.
2.2
Internal supply voltage generator
The IC has a fully integrated (no external capacitors required) charge pump for the Liquid
Crystal Display supply voltage generation. The multiplying factor can be programmed to be:
Auto, X6, X5, X4, X3, X2, using the ’set CP Multiplication’ Command. If Auto is set, the
multiplying factor is automatically selected to have the lowest current consumption in every
condition. This make possible to have an input voltage that changes over time and a
constant VLCD voltage. The output voltage (VLCDOUT) is tightly controlled through the
V
LCDSENSE pad. For this voltage, eight different temperature coefficients (TC, rate of change
with temperature) can be programmed using the bits TC1 and TC0 and T2,T1 & T0. This will
ensure no contrast degradation over the LCD operating range. Using the internal charge
pump, the VLCDIN and VLCDOUT pads must be connected together. An external supply could
be connected to VLCDIN to supply the LCD without using the internal generator. In such
event the VLDCOUT and VLCDSENSE must be connected to GND and the internal voltage
generator must be programmed to zero (PRS = [0;0], Vop = 0 - Reset condition).
2.3
2.4
Oscillator
A fully integrated oscillator (requires no external components) is present to provide the clock
for the Display System. When used the OSC pad must be connected to VDD1 pad. An
external oscillator could be used and fed into the OSC pin. An oscillator out is provided on
the OSCOUT Pad to cascade two or more drivers
Bias levels
To properly drive the LCD, six (Including VLCD and VSS) different voltage (Bias) levels are
generated. The ratios among these levels and VLCD, should be selected according to the
MUX ratio (m). They are established to be (Fig. 4):
n + 3
n + 4
n + 2
n + 4
2
n + 4
1
n + 4
------------
------------
------------
------------
VLCD
,
VLCD
,
VLCD
,
VLCD
,
VLCD,VSS
8/61
STE2002
Circuit description
Figure 3.
Bias level generator
VLCD
R
n + 3
n + 4
·VLCD
R
nR
R
n + 2
n + 4
·VLCD
2
·VLCD
n + 4
1
·VLCD
n + 4
R
VSS
D00IN1150
thus providing an 1/(n+4) ratio, with n calculated from:
=
m –
For m = 81, n = 6 and an 1/10 ratio is set.
For m = 65, n =5 and an 1/9 ratio is set.
The STE2002 provides three bits (BS0, BS1, BS2) for programming the desired Bias Ratio
as shown below:
Table 2.
Bias ratio programming
BS2
BS1
BS0
n
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
7
6
5
4
3
2
1
0
The following table Bias Level for m = 65 and m = 81 are provided:
Table 3.
Bias level
Symbol
m = 65 (1/9)
m = 81 (1/10)
V1
V2
V3
V4
V5
V6
VLCD
8/9*VLCD
7/9*VLCD
2/9*V VLCD
1/9 *VLCD
VSS
VLCD
9/10*VLCD
8/10*VLCD
2/10*VLCD
1/10*VLCD
VSS
9/61
Circuit description
STE2002
2.5
LCD voltage generation
The LCD Voltage at reference temperature (To = 27°C) can be set using the VOP register
content according to the following formula:
V
LCD(T=To) = VLCDo = (Ai+VOP · B)
(i=0,1,2)
with the following values:
Table 4.
LCD voltage values
Symbol
Value
Unit
Note
Ao
A1
A2
B
2.95
6.83
V
V
PRS = [0;0]
PRS = [0;1]
PRS = [1;0]
10.71
0.0303
27
V
V
To
°C
Note that the three PRS values produce three adjacent ranges for VLCD. If the VOP register
and PRS bits are set to zero the internal voltage generator is switched off.
The proper value for the VLCD is a function of the Liquid Crystal Threshold Voltage (Vth)
and of the Multiplexing Rate. A general expression for this is:
1 + m
--------------------------------------
V
=
⋅ V
LCD
th
1
⎛
⎞
2 ⋅ 1 – --------
⎝
⎠
m
For MUX Rate m = 65 the ideal VLCD is:
LCD(to) = 6.85 · Vth
then:
V
(6.85 ⋅ V – A )
th
= --------------------------------------------
i
V
op
0.03
10/61
STE2002
Circuit description
2.6
Temperature coefficient
As the viscosity, and therefore the contrast, of the LCD are subject to change with
temperature, there's the need to vary the LCD Voltage with temperature. The STE2002
provides the possibility to change the VLCD in a linear fashion against temperature with
eight different Temperature Coefficient selectable through the T2, T1 and T0 bits. Only four
of them are available with basic instruction set (TC1 & TC0 Bits).
Table 5.
Name
Temperature coefficients
TC1
TC0
Value
Unit
TC0
TC2
TC3
TC6
0
0
1
1
0
1
0
1
-0.0· 10-3
-0.7 · 10-3
-1.05· 10-3
-2.1 · 10-3
1/ °C
1/°C
1/°C
1/°C
Table 6.
Temperature coefficients
Name
TC2
TC1
TC0
Value
Unit
TC0
TC1
TC2
TC3
TC4
TC5
TC6
TC7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
-0.0· 10-3
-0.35 · 10-3
-0.7 · 10-3
-1.05· 10-3
-1.4 · 10-3
-1.75· 10-3
-2.1 · 10-3
-2.3· 10-3
1/ °C
1/°C
1/°C
1/°C
1/°C
1/°C
1/°C
1/°C
Figure 4.
LCD voltage
LCD
V
B
2
A
1
A
0
A + B
0
A
00h 01h 02h 03h 04h 05h …. 7Ch 7Dh 7Eh 7Fh 00h 01h 02h 03h 04h 05h …. 7Ch 7Dh 7Eh 7Fh 00h 01h 02h 03h 04h 05h …. 7Ch 7Dh 7Eh 7Fh
O
V
PRS = [0;0]
PRS = [0;1]
PRS = [1;0]
Finally, the VLCD voltage at a given (T) temperature can be calculated as:
VLCD(T) = VLCDo · [1 + (T-To) · TC]
11/61
Display data RAM
STE2002
3
Display data RAM
The STE2002, provides an 104X128 bits Static RAM to store Display data. This is organized
into 13 (Bank0 to Bank12) banks with 128 Bytes. One of these banks (128 bits wide) can be
used for Icons. RAM access is accomplished in either one of the Bus Interfaces provided
(see below). Allowed addresses are X0 to X127 (Horizontal) and Y0 to Y12 (Vertical).
When writing to RAM, four addressing mode are provided:
• Normal Horizontal (MX=0 and V=0), having the column with address X= 0 located on the
left of the memory map. The X pointer is increased after each byte written. After the last
column address (X=X-Carriage), Y address pointer is set to jump to the following bank and
X restarts from X=0. (Fig. 6)
• Normal Vertical (MX=0 and V=1), having the column with address X= 0 located on the left
of the memory map. The Y pointer is increased after each byte written. After the last Y bank
address (Y=Y-Carriage), X address pointer is set to jump to next column and Y restarts from
Y=0 (Fig. 7).
• Mirrored Horizontal (MX=1 and V=0), having the column with address X= 0 located on the
right of the memory map. The X pointer is increased after each byte written. After the last
column address (X=X-Carriage), Y address pointer is set to jump to the next bank and X
restarts from X=0 (fig. 8).
• Mirrored Vertical (MX=1 and V=1), having the column with address X= 0 located on the
right of the memory map. The Y pointer is increased after each byte written. After the last Y
bank address (Y=Y-Carriage), the X pointer is set to jump to next column and Y restarts
from Y=0 (fig. 9).
After the last allowed address (X;Y)=(X-Carriage; Y-Carriage), the address pointers always
jump to the cell with address (X;Y) = (0;0) (Fi. 10, 11, 12 & 13).
Data bytes in the memory could have the MSB either on top (D0 = 0, Fig.14) or on the
bottom (D0=1, Fig. 15).
The STE2002 provides also means to alter the normal output addressing. A mirroring of the
Display along the X axis is enabled setting to a logic one MY bit.This function doesn't affect
the content of the memory RAM. It is only related to the visualization process.
When ICON MODE=1 the Icon Row is not mirrored with MY and is not scrolled. When ICON
Mode=0 the Icon Row is like the other graphic lines and is mirrored and scrolled.
Four are the multiplex ratio available when the partial display mode is disabled (MUX 33,
MUX 49, MUX 65 and MUX 81).
Only a subset of writable rows are output on Row drivers.
When Y-Carriage<MUX/8, if Mux 65 is selected only the first 65 memory rows are
visualized, if Mux 49 is selected only the first 49 memory rows are visualized, if Mux 33 is
selected only the first 33 memory rows are visualized. All unused Row and Column drivers
must be left floating.
When Y-Carriage<MUX/8, the icon Bank is located to BANK 10 in MUX 81 Mode, to
BANK8 in MUX 65 Mode, to BANK 6 in MUX 49 Mode and to BANK 4 in MUX 33 Mode.
When Y-Carriage>MUX/8 lines only 33, 49, 65 or 81 lines are visualized but it is possible to
select which lines of DDRAM are connected on the output drivers. The DDRAM rows to
visualized can be selected in the 0-Y-Carriage*8 range using the scrolling function.
12/61
STE2002
Display data RAM
When Y-Carriage>MUX lines, the icon row is moved in DDRAM to the first row of the Y-
CARRIAGE Return BANK even if it is always connected on the same output Driver.
When MY=0, the icon Row is output on R80 in mux 81 mode, on R72 in MUX 65, on R64 in
MUX49 and on R56 in MUX 33.
When MY=1, and ICON MODE=1, the icon Row is output on R80 in mux 81 mode, on R72
in MUX 65, on R64 in MUX49 and on R56 in MUX 33.
When MY=1, and ICON MODE=0, the icon Row is output on R0 whatever is the MUX Rate.
When ICON MODE =1, the Memory ICON Row content is output on ICON Pad.
If Not Used ICON Pad must be left floating.
Figure 5.
Automatic data RAM writing sequence with V=0 and Data RAM Normal
Format (MX=0)(a)
0
1
2
3
124 125 126 127
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
0
1
2
3
4
5
6
7
8
9
BANK 10
BANK 11
BANK 12
Figure 6.
Automatic data RAM writing sequence with V=1 and Data RAM Normal
Format (MX=0)(a)
0
1
2
3
124 125 126 127
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
0
1
2
3
4
5
6
7
8
9
BANK 10
BANK 11
BANK 12
Figure 7.
Automatic data RAM writing sequence with V=0 and Data RAM Mirrored
Format (MX=1(a)
127 126 125 124
3
2
1
0
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
0
1
2
3
4
5
6
7
8
9
BANK 10
BANK 11
BANK 12
a. X Carriage=127; Y-Carriage = 12
13/61
Display data RAM
Figure 8.
STE2002
Automatic data RAM writing sequence with V=1 and Data RAM mirrored
format (MX=1)(a)
127 126 125 124
3
2
1
0
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
0
1
2
3
4
5
6
7
8
9
BANK 10
BANK 11
BANK 12
Figure 9.
Automatic data RAM writing sequence with X-Y carriage return
(V=0; MX=0)
X CARR
0
1
2
3
124 125 126 127
BANK
BANK
BANK
0
1
2
Y CARR
BANK 11
BANK 12
Figure 10. Automatic data RAM writing sequence with X-Y carriage return
(V=1; MX=0)
X CARR
0
1
2
3
124 125 126 127
BANK
BANK
BANK
0
1
2
Y CARR
BANK 11
BANK 12
Figure 11. Automatic data RAM writing sequence with X-Y carriage return (V=0;
MX=1)
X CARR
127 126 125 124
3
2
1
0
BANK
BANK
BANK
0
1
2
Y CARR
BANK 11
BANK 12
14/61
STE2002
Display data RAM
Figure 12. Automatic data RAM writing sequence with X-Y carriage return
(V=1; MX=1)
X CARR
127 126 125 124
3
2
1
0
BANK
BANK
BANK
0
1
2
Y CARR
BANK 11
BANK 12
Figure 13. Data RAM Byte organization with D0 = 0
MSB
0
1
2
3
124 125 126 127
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
0
1
2
3
4
5
6
7
8
9
LSB
BANK 10
BANK 11
BANK 12
Figure 14. Data RAM Byte organization with D0 = 1
LSB
0
1
2
3
124 125 126 127
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
BANK
0
1
2
3
4
5
6
7
8
9
MSB
BANK 10
BANK 11
BANK 12
Figure 15. Memory rows vs. row drivers mapping with MY=0, MUX81, icon mode=0,1
ROW DRIVER
ROW DRIVER
PHYSICAL MEMORY ROW
ICON MODE=1
ICON MODE=0
0
1
2
3
124 125 126 127
ROW 0
R 0
R 1
R 2
R 3
R 0
R 1
R 2
R 3
ROW 1
ROW 2
ROW 3
Y-CARRIAGE
R 79
R 80
R 79
R 80
ROW 79
ROW 80
ICON ROW
ICON
15/61
Display data RAM
STE2002
Figure 16. Memory rows vs. row drivers mapping with MY=0, MUX 81, scroll pointer = +3, icon
mode=1
ROW DRIVER
PHYSICAL MEMORY ROW
ICON MODE=1
0
1
2
3
124 125 126 127
ROW 0
ROW 1
R 0
R 1
R 2
R 3
ROW 2
ROW 3
Y-CARRIAGE
R 76
R 77
R 78
R 79
R 80
ROW 79
ROW 80
ICON ROW
ICON
Figure 17. Memory rows vs. row drivers mapping with MY=0, MUX 81, scroll
pointer=+3, icon mode=0
ROW DRIVER
PHYSICAL MEMORY ROW
ICON MODE=0
0
1
2
3
124 125 126 127
ROW 0
R 0
R 1
R 2
R 3
ROW 1
ROW 2
ROW 3
Y-CARRIAGE
R 76
R 77
R 78
R 79
R 80
ROW 79
ROW 80
ICON ROW
ICON
Figure 18. Memory rows vs. row drivers mapping with MUX 65 Y-CARRIAGE<=8
scroll pointer=0, icon mode=1
PHYSICAL MEMORY ROW
ROW DRIVER
0
1
2
3
124 125 126 127
ROW 0
ROW 1
R 0
R 30
R 31
ROW 31
ROW 32
N.C.
N.C.
R 40
Y-CARRIAGE
ICON ROW
R 71
R 72
ROW 63
ROW 64
R 79
R 80
ROW 96
ICON
16/61
STE2002
Display data RAM
Figure 19. Memory rows vs. row drivers mapping with MUX65, Y-CARRIAGE>8,
scroll pointer=0, icon mode=1
PHYSICAL MEMORY ROW
ROW DRIVER
0
1
2
3
124 125 126 127
ROW 0
R 0
ROW 31
ROW 32
R 31
R 32
N.C.
R 40
ROW 63
R 71
R 72
ICON ROW
ROW 75
ROW 76
Y-CARRIAGE
N.C.
R 79
R 80
ROW 96
ICON
Figure 20. Memory rows vs. row drivers mapping with MUX65, Y-CARRIAGE>8,
scroll pointer=3, icon mode=1,
PHYSICAL MEMORY ROW
ROW DRIVER
0
1
2
3
124 125 126 127
ROW 0
R 0
ROW 1
ROW 2
R 30
R 31
ROW 33
ROW 34
N.C.
R 40
R 71
R 72
ROW 66
ICON ROW
ROW 75
ROW 76
Y-CARRIAGE
N.C.
R 79
R 80
ROW 96
ICON
Figure 21. Memory Rows vs. Row drivers mapping with MY=1, MUX81, icon mode
0,1 scroll pointer=0
ROW DRIVER
ICON MODE=1
ROW DRIVER
ICON MODE=0
PHYSICAL MEMORY ROW
0
1
2
3
124 125 126 127
ROW 0
R 79
R 78
R 80
R 79
ROW 1
ROW 2
ROW 3
Y-CARRIAGE
R 2
R 1
R 3
R 2
R 1
R 0
ROW 79
ROW 80
R 0
ICON ROW
R 80
ICON
ICON
17/61
Display data RAM
Figure 22. Memory rows vs. row drivers mapping with MY=1, MUX81,
STE2002
scroll offset = +3, icon mode =0
ROW DRIVER
ICON MODE=0
PHYSICAL MEMORY ROW
0
1
2
3
124 125 126 127
ROW 0
R 80
R 78
R 79
R 77
R 76
ROW 1
ROW 2
ROW 3
Y-CARRIAGE
ROW 79
ROW 80
R 1
R 0
ICON ROW
ICON
Figure 23. Memory rows vs. row drivers mapping with MY=1, MUX81,
scroll offset= +3, icon mode =1
ROW DRIVER
SCROLL OFFSET +3
PHYSICAL MEMORY ROW
ICON MODE=1
0
1
2
3
124 125 126 127
ROW 0
R 79
R 78
R 77
ROW 1
ROW 2
R 76
ROW 3
Y-CARRIAGE
R 1
R 0
R 80
ROW 79
ROW 80
ICON ROW
ICON
Figure 24. Row drivers vs. LCD panel interconnection in MUX81 mode
ICON
81x128
MUX 81 Mode
COLUMN DRIVERS
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
R57
R58
R59
R60
R61
R62
R63
R64
R65
R66
R67
R68
R69
R70
R71
R72
R73
R74
R75
ICON
R
R
R
R
R
R
R
R
R
R
0
1
2
3
4
5
6
7
8
9
ROW DRIVERS
ROW DRIVERS
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
R31
R32
R33
R34
STE2002
LR0012
18/61
STE2002
Display data RAM
Figure 25. Row drivers vs. LCD panel interconnection in MUX65 mode
ICON
65x128
MUX 65 Mode
COLUMN DRIVERS
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
R57
R58
R59
R60
R61
R62
R63
R64
R65
R66
R67
R68
R69
R70
R71
R72
R73
R74
R75
ICON
R
R
R
R
R
R
R
R
R
R
0
1
2
3
4
5
6
7
8
9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
R31
R32
R33
R34
ROW DRIVERS
ROW DRIVERS
STE2002
LR0014
Figure 26. Row drivers vs. LCD panel interconnection in MUX49 mode
ICON
49x128
MUX 49 Mode
COLUMN DRIVERS
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
R57
R58
R59
R60
R61
R62
R63
R64
R65
R66
R67
R68
R69
R70
R71
R72
R73
R74
R75
ICON
R
R
R
R
R
R
R
R
R
R
0
1
2
3
4
5
6
7
8
9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
R31
R32
R33
R34
ROW DRIVERS
ROW DRIVERS
STE2002
LR0013
19/61
Display data RAM
Figure 27. Row drivers vs. LCD panel interconnection in MUX33 mode
STE2002
ICON
33x128
MUX 33Mode
COLUMN DRIVERS
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
R54
R55
R56
R57
R58
R59
R60
R61
R62
R63
R64
R65
R66
R67
R68
R69
R70
R71
R72
R73
R74
R75
ICON
R
R
R
R
R
R
R
R
R
R
0
1
2
3
4
5
6
7
8
9
ROW DRIVERS
ROW DRIVERS
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
R31
R32
R33
R34
STE2002
LR0106
20/61
STE2002
Instruction set
4
Instruction set
Two different instructions formats are provided:
- With D/C set to LOW
commands are sent to the Control circuitry.
- With D/C set to HIGH
the Data RAM is addressed.
Two different instruction set are embedded: the STE2001-like instruction set and the
extended instruction set. To select the STE2001-like instruction set the EXT pad has to be
connected to a logic LOW (connect to VSS). To select the extended instruction the EXT pad
has to be connected to a logic HIGH (connect to VDD1).
The instructions have the syntax summarized in Table 10, (basic-set) and Table 11
(extended set).
4.1
Reset (RES)
At power-on, all internal registers are configured with the default value. The RAM content is
not defined. A Reset pulse on RES pad (active low) re-initialize the internal registers content
(see Table 10, Table 11, Table 12). Applying a reset pulse, every on-going communication
with the host controller is interrupted. After the power-on, the Software Reset instruction can
be used to re-load the reset configuration into the internal registers
The default configurations is: .
- Horizontal addressing (V = 0)
- Normal instruction set (H[1:0] = 0)
- Normal display (MX = MY = 0)
- Display blank (E = D = 0)
- Multiplexing Ratio (M[1:0]=0)
- Frame Rate (FR[1:0]=”75Hz”)
- Power Down (PD = 1)
- Dual Partial Display Disabled (PE=0)
- Address counter X[6: 0] = 0 and Y[4: 0] = 0 - VOP=0
- Temperature coefficient (TC[1: 0] = 0)
- Bias system (BS[2: 0] = 0)
A MEMORY BLANK instruction can be executed to clear the RAM content.
4.2
Power down (PD = 1)
When at Power Down, all LCD outputs are kept at VSS (display off). Bias generator and
V
LCD generator are OFF (VLCDOUT output is discharged to VSS, and then is possible to
disconnect VLCDOUT). The internal Oscillator is in off state. An external clock can be
provided. The RAM contents is not cleared.
21/61
Instruction set
STE2002
4.3
Memory blanking procedure
This instruction allows to fill the memory with "blank" patterns, in order to delete patterns
randomly generated in memory when starting up the device. This instruction substitutes
(128X13) single "write" instructions. It is possible to program "Memory Blanking Procedure"
only under the following conditions:
- PD bit
= 0
The end of the procedure will be notified on the BSY_FLG pad going HIGH (while LOW the
procedure is running). Any instruction programmed with BSY_FLG LOW will be ignored that
is, no instruction can be programmed for a period equivalent to 128X13 internal write cycles
(128X13X1/fclock). The start of Memory blanking procedure will be between one and two
fclock cycles from the last active edge (E rising edge for the parallel interface, last SCLK
rising edge for the Serial interface, last SCL rising edge for the I2C interface).
4.4
Checker board procedure
This instruction allows to fill the memory with "checker-board" pattern. It is mainly intended
to developers, who can now simply obtain complex module test configuration by means of a
single instruction. It is possible to program "Checker Board Procedure" only under the
following conditions:
–
PD bit = 0
The end of the procedure will be notified on the BSY_FLG pad going HIGH, while LOW the
procedure is running. Any instruction programmed with BSY_FLG LOW will be ignored, that
is, no instruction can be programmed for a period equivalent to 128X13 internal write cycles
(128X13X1/fclock). The start of Memory blanking procedure will be between one and two
fclock cycles from the last active edge (E rising edge for the parallel interface, last SCLK
rising edge for the Serial interface, last SCL rising edge for the I2C interface).
4.5
Scrolling function
The STE2002 can scroll the graphics display in units of raster-rows. The scrolling function is
achieved changing the correspondence between the rows of the logical memory map and
the output row drivers. The scroll function doesn't affect the data ram content. It is only
related to the visualization process. The information output on the drivers is related to the
row reading sequence (the 1st row read is output on R0, the 2nd on R1 and so on). Scrolling
means reading the matrix starting from a row that is sequentially increased or decreased.
After every scrolling command the offset between the memory address and the memory
scanning pointer is increased or decreased by one. The offset range changes in accordance
with MUX Rate. After 80th/81th scrolling commands in MUX 81 mode, or after the 64th/65th
scrolling commands in mux 65 mode, or after 48nd/49rd scrolling command in MUX 49
mode, or after 32nd/33rd scrolling command in MUX 33 mode, the offset between the
memory address and the memory scanning pointer is again zero (Cyclic Scrolling).
A Reset Scrolling Pointer instruction can be executed to force to zero the offset between the
memory address and the memory scanning pointer
The Icon Row is not scrolled if ICON MODE =1. If ICON MODE=0 the last row is like a
general purpose row and it is scrolled as other rows.
If the DIR Bit is set to a logic zero the offset register is increased by one and the raster is
scrolled from top down. If the DIR Bit is set to a logic one the offset register is decreased by
one and the raster is scrolled from bottom-up.
22/61
STE2002
Instruction set
Table 7.
Mux rate
Scrolling function
Offset
Icon row driver with
MY=0
Icon mode
Description
range
MUX 33
MUX 33
MUX 49
MUX 49
MUX 65
MUX 65
MUX 81
MUX 81
1
0
1
0
1
0
1
0
0-31
0-32
0-47
0-48
0-63
0-64
0-79
0-80
ICON ROW NOT SCROOLED
33 LINE GRAPHIC MATRIX
ICON ROW NOT SCROOLED
49 LINE GRAPHIC MATRIX
ICON ROW NOT SCROOLED
65 LINE GRAPHIC MATRIX
ICON ROW NOT SCROOLED
81 LINE GRAPHIC MATRIX
R56
R56
R64
R64
R72
R72
R80
R80
4.6
Dual partial display
If the PE Bit is set to a logic one the dual partial display mode is enabled.
Eight partial display modes are available. The offset of the two partial display zones is row
by row programmable. The Icon row is accessed last in each partial display frame.
Two sets of register for the HV-generator parameters are provided (PRS[1:0], Vop[6:0],
BS[2:0], CP[2:0].). This allows switching from normal mode to partial display mode applying
one instruction. The HV generator is automatically re configured using the parameters
related to the enabled mode. The parameters of the two sets of registers with the same
function are located in the same position of the instruction set. The registers related to the
normal mode are accessible when normal mode (PE=0) is selected, the others are
accessible when the partial display mode is enabled (PE=1). To Setup PRS[1:0], Vop[6:0],
BS[2:0], CP[2:0] values the instruction flow proposed in Fig.46 must be followed. To setup
Partial Display Sectors Start Address and Partial Display Mode no particular instruction flow
has to be followed.
Table 8.
Dual partial display
PD2 PD1 PD0
Section 1
Section2
Reset state
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
8
8 + Icon Row
0 + Icon Row
8 + Icon Row
16 + Icon Row
0 + Icon Row
16 + Icon Row
8 + Icon Row
16 + Icon Row
8
0
000
16
8
16
16
23/61
Bus interfaces
STE2002
5
Bus interfaces
To provide the widest flexibility and ease of use the STE2002 features three different
methods for interfacing the host Controller. To select the desired interface the SEL1 and
SEL2 pads need to be connected to a logic LOW (connect to GND) or a logic HIGH (connect
to VDD). All the I/O pins of the unused interfaces must be connected to GND.
All interfaces are working while the STE2002 is in Power Down
.
Table 9.
Bus interface
SEL2
SEL1
Interface
Note
Read and Write; Fast
and High Speed Mode
0
0
I2C
0
1
1
1
0
1
Serial
Read and Write
Read and Write
Not Used
Parallel
2
5.1
I C interface
The I2C interface is a fully complying I2C bus specification, selectable to work in both Fast
(400kHz Clock) and High Speed Mode (3.4MHz).
This bus is intended for communication between different Ics. It consists of two lines: one bi-
directional for data signals (SDA) and one for clock signals (SCL). Both the SDA and SCL
lines must be connected to a positive supply voltage via an active or passive pull-up.
The following protocol has been defined:
- Data transfer may be initiated only when the bus is not busy.
- During data transfer, the data line must remain stable whenever the clock line is high.
Changes in the data line while the clock line is high will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
BUS not busy: Both data and clock lines remain High.
Start Data Transfer: A change in the state of the data line, from High to Low, while the clock
is High, define the START condition.
Stop Data Transfer: A Change in the state of the data line, from low to High, while the clock
signal is High, defines the STOP condition.
Data Valid: The state of the data line represents valid data when after a start condition, the
data line is stable for the duration of the High period of the clock signal. The data on the line
may be changed during the Low period of the clock signal. There is one clock pulse per bit
of data.
Each data transfer is initiated with a start condition and terminated with a stop condition.
The number of data bytes transferred between the start and the stop conditions is not
limited. The information is transmitted byte-wide and each receiver acknowledges with the
ninth bit.
24/61
STE2002
Bus interfaces
By definition, a device that gives out a message is called "transmitter", the receiving device
that gets the signals is called "receiver". The device that controls the message is called
"master". The devices that are controlled by the master are called "slaves"
Acknowledge. Each byte of eight bits is followed by one acknowledge bit. This
acknowledge bit is a low level put on the bus by the receiver, whereas the master generates
an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also, a master receiver must generate an acknowledge after the reception of
each byte that has been clocked out of the slave transmitter. The device that acknowledges
has to pull down the SDA_IN line during the acknowledge clock pulse. Of course, setup and
hold time must be taken into account. A master receiver must signal an end-of-data to the
slave transmitter by not generating an acknowledge on the last byte that has been clocked
out of the slave. In this case, the transmitter must leave the data line High to enable the
master to generate the STOP condition.
Connecting SDA_IN and SDA_OUT together the SDA line become the standard data line.
Having the acknowledge output (SDAOUT) separated from the serial data line is
advantageous in Chip-On-Glass (COG) applications. In COG applications where the track
resistance from the SDAOUT pad to the system SDA line can be significant, a potential
divider is generated by the bus pull-up resistor and the Indium Tin Oxide (ITO) track
resistance. It is possible that during the acknowledge cycle the STE2002 will not be able to
create a valid logic 0 level. By splitting the SDA input from the output the device could be
used in a mode that ignores the acknowledge bit. In COG applications where the
acknowledge cycle is required, it is necessary to minimize the track resistance from the
SDACK pad to the system SDA line to guarantee a valid LOW level.
To be compliant with the I2C-bus Hs-mode specification the STE2002 is able to detect the
special sequence "S00001xxx". After this sequence no acknowledge pulse is generated.
Since no internal modification are applied to work in Hs-mode, the device is able to work in
Hs-mode without detecting the master code.
Figure 28. Bit transfer and START,STOP conditions definition
DATA LINE
STABLE
DATA VALID
CLOCK
DATA
START
CHANGE OF
STOP
CONDITION
DATA ALLOWED
CONDITION
D00IN1151
2
Figure 29. Acknowledgment on the I C-bus
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
SCLK FROM
MASTER
1
2
8
9
DATA OUTPUT
BY TRANSMITTER
MSB
LSB
DATA OUTPUT
BY RECEIVER
D00IN1152
25/61
Bus interfaces
STE2002
5.1.1
Communication protocol
The STE2002 is an I2C slave. The access to the device is bi-directional since data write and
status read are allowed.
Four are the device addresses available for the device. All have in common the first 5 bits
(01111). The two least significant bit of the slave address are set by connecting the SA0 and
SA1 inputs to a logic 0 or to a logic 1.
To start the communication between the bus master and the slave LCD driver, the master
must initiate a START condition. Following this, the master sends an 8-bit byte, shown in Fig.
30, on the SDA bus line (Most significant bit first). This consists of the 7-bit Device select
Code, and the 1-bit Read/Write Designator (R/W).
All slaves with the corresponding address acknowledge in parallel, all the others will ignore
the I2C-bus transfer.
Writing mode
If the R/W bit is set to logic 0 the STE2002 is set to be a receiver. After the slaves
acknowledge one or more command word follows to define the status of the device.
A command word is composed by two bytes. The first is a control byte which defines the Co
and D/C values, the second is a data byte (fig 31). The Co bit is the command MSB and
defines if after this command will follow one data byte and an other command word or if will
follow a stream of data (Co = 1 Command word, Co = 0 Stream of data). The D/C bit defines
whether the data byte is a command or RAM data (D/C = 1 RAM Data, D/C = 0 Command).
If Co =1 and D/C = 0 the incoming data byte is decoded as a command, and if Co =1 and
D/C =1, the following data byte will be stored in the data RAM at the location specified by the
data pointer.
Every byte of a command word must be acknowledged by all addressed units.
After the last control byte, if D/C is set to a logic 1 the incoming data bytes are stored inside
the STE2002 Display RAM starting at the address specified by the data pointer. The data
pointer is automatically updated after every byte written and in the end points to the last
RAM location written.
Every byte must be acknowledged by all addressed units.
Reading mode
If the R/W bit is set to logic 1 the chip will output data immediately after the slave address. If
the D/C bit sent during the last write access, is set to a logic 0, the byte read is the status
byte.
26/61
STE2002
Bus interfaces
Figure 30. Communication protocol
WRITE MODE
STE2002 ACK
STE2002 ACK
STE2002 ACK
STE2002 ACK
STE2002 ACK
S S
A A
S
0
1
1
1
1
0
A
1
DC Control Byte
A
DATA Byte
A
0
DC Control Byte
A
DATA Byte
A P
1
0
R/W Co
SLAVE ADDRESS
Co
LAST
CONTROL BYTE
N> 0 BYTE
MSB........LSB
COMMAND WORD
READ MODE
STE2002 ACK
MASTER ACK
P
S S
A A
S S R
C D
o C
S
0
1
1
1
1
1
A
0
1
1
1
1
A A
/
0 0 0 0 0 0 A
1
0
1
0 W
R/W
STE2002
SLAVE ADDRESS
CONTROL BYTE
5.2
Serial interface
The STE2002 serial Interface is a bidirectional link between the display driver and the
application supervisor.
It consists of five lines: two for data signals (SDIN, SOUT), one for clock signals (SCLK), one
for the peripheral enable (SCE) and one for mode selection (SD/C).
The serial interface is active only if the SCE line is set to a logic 0. When SCE line is high the
serial peripheral power consumption is zero. While SCE pin is high the serial interface is
kept in reset.
The STE2002 is always a slave on the bus and receive the communication clock on the
SCLK pin from the master.
Information are exchanged byte-wide. During data transfer, the data line is sampled on the
positive SCLK edge.
SD/C line status indicates whether the byte is a command (SD/C =0) or RAM data (SD/C
=1);it is read on the eighth SCLK clock pulse during every byte transfer.
If SCE stays low after the last bit of a command/data byte, the serial interface expects the
MSB of the next byte at the next SCLK positive edge.
A reset pulse on RES pin interrupts the transmission. No data is written into the data RAM
and all the internal registers are cleared.
If SCE is low after the positive edge of RES, the serial interface is ready to receive data.
Throughout SOUT can be read only the driver I2C slave address. The Command sequence
that allows to read I2C slave address is reported in Fig. 34 & 35. SOUT is in High impedance
in steady state and during data write.
It is possible to short circuit DOUT and SDIN and read I2C address without any additional
lines.
27/61
Bus interfaces
Figure 31. Serial bus protocol - one byte transmission
STE2002
SCE
D/C
SCLK
SDIN
MSB
LSB
D00IN1159
Figure 32. Serial bus protocol - several byte transmission
SCE
D/C
SCLK
SDIN
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
D00IN1160
Figure 33. Serial bus protocol - several byte transmission
SCE
D/C
SCLK
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
Don't
Care
SDIN
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB7
DB6
DB5
D00IN1160
High-Z
High-Z
SOUT
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Command Write
I2C Address Read
28/61
STE2002
Bus interfaces
Figure 34. Reading sequence
READING SEQUENCE
Write a "00000000" Instruction
SOUT Buffer becomes active (Low Impedence)
Source 8 pulses on SCLK and
1
Read the I2C Address or Status Byte On SOUT
SOUT Buffer Configured in High Impedence
END OF READING SEQUENCE
note: 1) these data are not read by the display Diver
2) SDIN and SOUT can be short circuited if the processor can configure
serial output buffers in high impedence during data read
.
LR0078
5.3
Parallel interface
The STE2002 parallel Interface is a bidirectional link between the display driver and the
application supervisor. It consists of eleven lines: eight data lines (from DB7 to DB0) and
three control lines. The control lines are: enable (E) for data latch, PD/C for mode selection
and R/W for reading or writing.
The data lines and the control line values are internally latched on E rising edge (fig. 50).
When the parallel interface is selected, if R/W line is set to “one”, D0-D7 lines are configured
as output drivers (low impedence) and it is possible to read the driver I2C address (Fig. 51)
Table 10. STE2001-like instruction set
D/C
R/W
Instruction
H=0 or H=1
B7 B6 B5 B4 B3 B2
B1
B0
Description
Read I2C Address
(with Serial Interface
only)
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
Power Down
Management; Entry
Mode;
Function Set
MX MY PD
V
H[0]
Read Status Byte
Write Data
0
1
1
0
PD A1 A2
D
E
MX
MY
D1
DO
D0
(I2C interface only)
D7 D6 D5 D4 D3 D2
Writes data to RAM
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Bus interfaces
STE2002
Table 10. STE2001-like instruction set (continued)
D/C
R/W
Instruction
H=0
B7 B6 B5 B4 B3 B2
B1
B0
Description
Starts Memory Blank
Procedure
Memory Blank
Scroll
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
1
DIR
PRS[0]
E
Scrolls by one Row
UP or DOWN
VLCD Range
Setting
VLDC programming
range selection
1
0
Select Display
Configuration
Display Control
Set CP Factor
Set RAM Y
D
S2
0
Charge Pump
Multiplication factor
S1
Y1
X1
S0
Set Horizontal (Y)
RAM Address
Y3 Y2
Y0
Set Vertical (X) RAM
Address
Set RAM X
X6 X5 X4 X3 X2
X0
H=1
Starts Checker Board
Procedure
Checker Board
Multiplex Select
TC Select
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
X
0
0
0
0
1
X
0
0
0
1
0
X
0
0
0
1
1
MUX
TC0
A2
Selects MUX factor
Set Temperature
Coefficient for VLDC
1
TC1
A1
Output Address
Bias Ratios
Reserved
DO
BS2
X
No function
Set desired Bias
Ratios
BS1
X
BS0
X
Not to be used
OP OP OP OP OP
6
VOP register Write
instruction
Set VOP
OP1
OP0
5
4
3
2
30/61
STE2002
Bus interfaces
Description
Table 11. Extended instruction set
D/C R/W
Instruction
B7
B6
B5
B4
B3
B2
B1
B0
H independent instructions
Read I2C Address
(with Serial
Interface only)
NOP
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
Power Down
Management;Entry
Mode; Extended
Instruction Set
Function Set
MX
MY
PD
H[1]
H[0]
Read Status
Byte
0
1
1
0
PD
D7
0
0
D
E
MX
D2
MY
D1
DO
D0
(I2C interface only)
Writes data to RAM
Write Data
D6
D5
D4
D3
H=[0;0] RAM commands
Memory
Blank
Starts Memory
Blank Procedure
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
DIR
PRS[0]
E
Scrolls by one Row
UP or DOWN
Scroll
VLCD Range
Setting
VLDC programming
range selection
0
0
0
0
1
PRS[1]
0
Display
Control
Select Display
Configuration
0
0
0
1
D
Charge Pump
Multiplication factor
Set CP Factor
Set RAM Y
0
0
1
0
S2
Y2
X2
S1
S0
Set Horizontal (Y)
RAM Address
1
0
0
Y3
X3
Y1
Y0
Set Vertical (X)
RAM Address
Set RAM X
X6
X5
X4
X1
X0
H=[0;1]
Checker
Board
Starts Checker
Board Procedure
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
Vertical Addressing
Mode
V
Set Temperature
Coefficient for VLDC
TC Select
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
X
0
0
1
X
0
1
0
X
1
TC1
0
TC0
0
Data Format
Bias Ratios
DO
BS2
X
MSB Position
Set desired Bias
Ratios
BS1
X
BS0
X
Reserved
VOP register Write
instruction
Set VOP
OP6 OP5 OP4 OP3
OP2
OP1
OP0
31/61
Bus interfaces
STE2002
Table 11. Extended instruction set
D/C R/W
Instruction
H=[1;0]
B7
B6
B5
B4
B3
B2
B1
B0
Description
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
Software RESET
Partial Enable
Frame rate Control
Mux Ratio
1
PE
FR1
M[1]
FR0
M[0]
Partial Display
Config
Partial mode
0
0
0
0
0
0
0
0
1
0
1
0
1
0
PD2
PDY2
PDY2
PD1
PDY1
PDY1
PD0
PDY0
PDY0
1
st Sector Start
Address
PDY5 PDY4 PDY
3
2
nd Sector Start
PDY6 PDY5 PDY4 PDY
3
Address
H=[1;1]
Scrolling Pointer
Reset
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
X
X
Not Used
Not Used
X
Set Temperature
Coefficient for VLDC
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
1
T2
X
T1
X
T0
X
X
Not Used
Y-CARRIAGE
RETURN
YC-3 YC-2
YC-1
YC-0
X CARRIAGE
RETURN
0
0
1
XC-6 XC-5 XC-4 XC-3 XC-2
XC-1
XC-0
Table 12. Explanations of symbols
Reset
state
Bit
0
1
DIR Scroll by one down
Scroll by one up
PD Device fully working
Horizontal addressing
MX Normal X axis addressing
Device in power down
Vertical addressing
1
0
0
V
X axis address is mirrored.
MY Image is displayed not vertically mirrored Image is displayed vertically mirrored
0
0
0
0
0
DO MSB on TOP
PE Partial Display disabled
H[0] Select page 0
MUX MUX 65
MSB on BOTTOM
Partial Display enabled
Select page 1
MUX 33
32/61
STE2002
Bus interfaces
Table 13. Page number
H[1]
H[0]
Description
Reset state
0
0
1
1
0
1
0
1
Page 0
Page 1
Page 2
Page 3
Page 0
Table 14. Display mode
D
E
Description
display blank
Reset state
0
0
1
1
0
1
0
1
all display segments on
normal mode
D=0
E=0
inverse video mode
Table 15. Frame rate control
FR[1]
FR[0]
Description
Reset state
0
0
1
1
0
1
0
1
65Hz
70Hz
75Hz
80Hz
75Hz
Table 16. VLCD range selection
PRS[1]
PRS[0]
Description
Reset State
0
0
1
1
0
1
0
1
2.94
6.78
10.62
Not Used
Table 17. Multiplexing ratio
M[1]
M[0]
Description
Reset state
0
0
1
1
0
1
0
1
49
65
01
81
Not Used
33/61
Bus interfaces
STE2002
Table 18. Temperature coefficient
T2
T1
T0
Description
Reset state
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
VLCD temperature Coefficient 0
VLCD temperature Coefficient 1
VLCD temperature Coefficient 2
VLCD temperature Coefficient 3
VLCD temperature Coefficient 4
VLCD temperature Coefficient 5
VLCD temperature Coefficient 6
VLCD temperature Coefficient 7
000
Table 19. TC1 & TC0 temperature coefficients
TC1
TC0
Description
Reset state
0
0
1
1
0
1
0
1
VLCD temperature Coefficient 0
VLCD temperature Coefficient 2
VLCD temperature Coefficient 3
VLCD temperature Coefficient 6
00
Table 20. Charge pump multiplication factor
CP2
CP1
CP0
Description
Reset state
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Multiplication Factor X2
Multiplication Factor X3
Multiplication Factor X4
Multiplication Factor X5
Multiplication Factor X6
NOT USED
000
NOT USED
AUTOMATIC
34/61
STE2002
Bus interfaces
O
Table 21. Bias ratio
BS2
BS1
BS0
Description
Bias Ratio equal to 7
Reset state
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Bias Ratio equal to 6
Bias Ratio equal to 5
Bias Ratio equal to 4
Bias Ratio equal to 3
Bias Ratio equal to 2
Bias Ratio equal to 1
Bias Ratio equal to 0
000
Table 22. Y carriage return register
Y-C[3] Y-C[2] Y-C[1] Y-C[0] Description
Reset state
0
0
0
0
0
0
.
0
0
0
0
1
1
.
0
0
1
1
0
0
.
0
1
0
1
0
1
.
Y-CARRIAGE =1
Y-CARRIAGE =2
Y-CARRIAGE =3
Y-CARRIAGE =4
Y-CARRIAGE =5
1000
1
1
1
0
0
1
1
1
0
0
1
0
Y-CARRIAGE =10
Y-CARRIAGE =11
Y-CARRIAGE =12
Table 23. Partial display configuration
PD2
PD1
PD0
Section 1
Section2
Reset state
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
8
8 + Icon Row
0 + Icon Row
8 + Icon Row
16 + Icon Row
0 + Icon Row
16 + Icon Row
8 + Icon Row
16 + Icon Row
8
0
000
16
8
16
16
35/61
Bus interfaces
Figure 35. Host processor interconnection with I2C interface
STE2002
SCL
SDAIN
SDAOUT
VSSAUX
RES
E
µP
STE2002
PD/C
D0
D1
D2
D3
D4
D5
D6
D7
R/W
VSSAUX
SCLK
SCE
SD/C
SDIN
SDOUT
BSY_FLG
VDD2
VDD1
OSCIN
VDD1 / GND / VSSAUX
ICON_MODE
SEL1
SEL2
GND / VSSAUX
VDD1
EXT_SET
VDD1 / GND / VSSAUX
VDD1 / GND / VSSAUX
SA0
SA1
VSSAUX
TEST_10
TEST_9
TEST_8
TEST_7
TEST_6
TEST_5
TEST_4
TEST_3
TEST_2
TEST_1
Figure 36. Host processor interconnection with serial interface
SCL
SDAIN
SDAOUT
µP
STE2002
VSSAUX
RES
E
PD/C
D0
D1
D2
D3
D4
D5
D6
D7
R/W
VSSAUX
SCLK
SCE
SD/C
SDIN
SDOUT
BSY_FLG
VDD2
VDD1
OSCIN
VDD1 / GND / VSSAUX
ICON_MODE
SEL1
VDD1
GND / VSSAUX
VDD1
SEL2
EXT_SET
VDD1 / GND / VSSAUX
VDD1 / GND / VSSAUX
SA0
SA1
VSSAUX
TEST_10
TEST_9
TEST_8
TEST_7
TEST_6
TEST_5
TEST_4
TEST_3
TEST_2
TEST_1
36/61
STE2002
Bus interfaces
Figure 37. Host processor interconnection with parallel interface
SCL
SDAIN
SDAOUT
µP
STE2002
VSSAUX
RES
E
PD/C
D0
D1
D2
D3
D4
D5
D6
D7
R/W
VSSAUX
SCLK
SCE
SD/C
SDIN
SDOUT
BSY_FLG
VDD2
VDD1
OSCIN
ICON_MODE
SEL1
VDD1 / GND / VSSAUX
GND / VSSAUX
VDD1
SEL2
EXT_SET
VDD1
VDD1 / GND / VSSAUX
VDD1 / GND / VSSAUX
SA0
SA1
VSSAUX
TEST_10
TEST_9
TEST_8
TEST_7
TEST_6
TEST_5
TEST_4
TEST_3
TEST_2
TEST_1
Figure 38. application schematic using an external lcd Voltage Generator
I/O
VDD2
VDD
40
128
41
VDD1
100nF
VSS
81x 128
DISPLAY
VSS2
VSS1
1µF
VLCDSENSE
VLCDOUT
VLCDIN
VLCD
Figure 39. Application schematic using the internal LCD voltage generator and two
separate supplies
I/O
VDD2
VDD2
VDD1
40
128
41
VDD1
100nF
VSS
100nF
81x 128
DISPLAY
VSS2
VSS1
1µF
VLCDSENSE
VLCDOUT
VLCDIN
37/61
Bus interfaces
STE2002
Figure 40. Application schematic using the internal LCD voltage generator and a
single supply
I/O
VDD
VDD2
VDD1
40
128
41
100nF
VSS
81 x 128
DISPLAY
VSS2
VSS1
1µF
VLCDSENSE
VLCDOUT
VLCDIN
38/61
STE2002
Bus interfaces
Figure 41. Power-up sequence
T
vdd
Tw(res) TLogic (res)
VDD2
VDD1
RES
SCE
SCLK
SDIN
SD/C
PD/C
E
R/W
D0 - D7
HOST
D0 - D7
DRIVER
Hi-Z
Hi-Z
SCL
SDAIN
SOUT
SDA OUT
OSCIN
(HOST)
OSC OUT
(DRIVER)
BSY FLG
RESET POWER ON
BOOSTER
OFF
TABLE
INTERNAL
RESET
LR0116
LOADED
39/61
Bus interfaces
Figure 42. Power-OFF sequence
STE2002
T
w(res)
VDD2
VDD1
RES
SCLK
SDIN
SD/C
PD/C
E
SCE
SCl
SDAIN
R/W
D0 - D7
HOST
D0 - D7
DRIVER
Hi-Z
Hi-Z
SOUT
SDA OUT
OSCIN
(HOST)
OSC OUT
(DRIVER)
BSY FLG
RESET
TABLE
LOADED
LR0117
40/61
STE2002
Bus interfaces
Figure 43. Initialization with built-in booster
SETUP NORMAL DISPLAY MODE CONFIGURATION
SET Driver in Power Down(PD=1)
SET Driver in Normal Display Mode (PE=0)
SET PRS[1:0], Vop[6:0], BS[2:0], CP[2:0], FR[1:0],
TC, M[1:0] for Normal Display Operation
Switch "ON" Booster and Display Control Logic
(PD=0)
END OF NORMAL DISPLAY MODE CONFIG.
Figure 44. Dual partial display enabling instruction flow
ENABLE DUAL PARTIAL DISPLAY
SET 1st Sector Start Address
OPTIONAL1
SET 2nd Sector Start Address
SET PE=1
END OF ENABLING DUAL PARTIAL DISPLAY
41/61
Bus interfaces
Figure 45. Dual partial display mode configuration or duty change
STE2002
SETUP PARTIAL DISPLAY CONFIGURATION
SET Driver in Power Down(PD=1)
SET Driver in Partial Display Mode (PE=1)
SET PRS[1:0], Vop[6:0], BS[2:0], CP[2:0]
for Partial Display Operation
SET Partial Display Configuration (PD[2:0])
SET 1st Sector Start Address
OPTIONAL
SET 2nd Sector Start Address
SET Driver in Normal Mode (PE=0)
END OF PARTIAL DISPLAY CONFIG.
Figure 46. Data RAM to display mapping
DISPLAY DATA RAM
bank
0
GLASS
TOP VIEW
bank
1
DISPLAY DATA RAM = "1"
DISPLAY DATA RAM = "0"
bank
2
LCD
bank
3
bank
7
bank
8
ICOR ROW
D00IN1155
42/61
STE2002
Bus interfaces
Table 24. Pin configuration
Test numbers
Pin configuration
TEST_1
TEST_2
OPEN
GND
GND
TEST_3
TEST_4
TEST_5
TEST_6
TEST_7
TEST_8
TEST_9
TEST_10
TEST_11
TEST_12
TEST_13
TEST_14
43/61
Electrical characteristics
STE2002
6
Electrical characteristics
6.1
Absolute maximum ratings
Table 25. Absolute maximum ratings
Symbol
Parameter
Supply voltage range
Value
Unit
VDD1
VDD2
VLCD
ISS
- 0.5 to + 5
- 0.5 to + 7
- 0.5 to + 15
- 50 to +50
-0.5 to VDD2 + 0.5
- 10 to + 10
- 10 to + 10
300
V
V
Supply voltage range
LCD Supply Voltage Range
Supply current
V
mA
V
Vi
Input Voltage (all input pads)
DC Input Current
Iin
mA
mA
mW
mW
°C
°C
Iout
Ptot
Po
DC Output Current
Total Power Dissipation (Tj = 85°C)
Power Dissipation per Output
Operating Junction Temperature(1)
Storage Temperature
30
Tj
-20 to + 120
- 65 to 150
Tstg
1. Device behavior and characterization are measured over this temperature range during internal
qualification of the product. During production testing, however, device performance is measured at a fixed
ambient temperature, typically 25°C.
44/61
STE2002
Electrical characteristics
6.2
DC operation
VDD1 = 1.7 to 3.6 V; VDD2 = 1.75 to 4.2V; Vss1,2 = 0V; VLCD = 4.5 to 14.5 V;
Tamb = 25°C; unless otherwise specified.
Table 26. Electrical characteristics DC operation
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Supply voltages
VDD1
VDD2
Supply voltage(1)
1.7
3.6
4.2
V
V
LCD voltage internally
generated
Supply voltage
1.75
LCD voltage supplied
externally
VLCDIN
LCD supply voltage
LCD supply voltage
4.5
4.5
14.5
14.5
V
V
VLCDOUT
Internally generated(2)
;
VDD1 = 2.8V;
V
LCD = 10V;
15
20
40
200
1
µA
µA
µA
µA
fsclk = 0(3)
I(VDD1
)
)
Supply current
VDD1 = 2.8V;
V
LCD = 10V; fsclk = 1Mhz;
120
(1) (3); OSC_IN=GND;
parallel port
with VOP = 0 and
PRS = [0:0] with external
VLCD
(4)
Voltage generator supply
current
I(VDD2
VDD2= 2.8V;VLCD=10V;
fsclk= 0;
10
25
40
no display load;
5x charge pump (5) (3) (6)
VDD1,VDD2= 2.8V;
VLCD = 10V; 5x charge
pump; fsclk = 0;
80
µA
no display load (5) (3) (6)
I(VDD1,2
)
Total supply current
Power down Mode with
internal or External
VLCD(7)
3
10
15
µA
µA
VDD =2.8V;
External LCD supply
voltage current
I(VLDCIN
)
V
LCD =10V;no display
5
10
load; fsclk = 0 (3)
Logic outputs
High logic level output
voltage
V0H
VOL
IOH=-500µA
IOL=500µA
0.8VDD1
VSS
VDD1
V
V
Low logic level output
voltage
0.2VDD1
45/61
Electrical characteristics
STE2002
Unit
Table 26. Electrical characteristics DC operation
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Logic inputs
VIL
VIH
Iin
Logic LOW voltage level
Logic HIGH voltage level
Input current
VSS
0.7VDD1
-1
0.3VDD1
VDD2
1
V
V
Vin = VSS1 or VDD1
µA
logic inputs/outputs
VIL
Logic LOW voltage level
VSS
0.3VDD1
V
V
Logic HIGH Voltage
Level
VDD1
+0.5V
VIH
0.7VDD1
Column and row driver
Rrow
Rcol
ROW output resistance
VLCD = 10V;
3K
5K
5K
kohm
kohm
Column output
resistance
VLCD = 10V;
10K
Column Bias voltage
accuracy
Vcol
No load
-50
-50
+50
+50
mV
mV
Row Bias voltage
accuracy
Vrow
LCD supply voltage
VDD = 2.8V; VLCD = 10V;
fsclk=0;
LCD supply voltage
accuracy; internally
generated
no display load(5)(3)(6)(8)
VLCD
-2.2
2.2
%
(8) VOP = 61h,
PRS = 2hex
TC0
TC1
TC2
TC3
TC4
TC5
TC6
TC7
-0.0·10-3
-0.35·10-3
-0.7·10-3
-1.05·10-3
-1.4 ·10-3
-1.75·10-3
-2.1·10-3
-2.3·10-3
1/°C
1/°C
1/°C
1/°C
1/°C
1/°C
1/°C
1/°C
Temperature coefficient
1. Data Byte Writing Mode V
≤V
DD2
DD1
2. The maximum possible V
3. When f
voltage that can be generated is dependent on voltage, temperature and (display) load.
LCD
= 0 there is no interface clock.
sclk
4. External V
, the display load current is not transmitted to I
DD
LCD
5. Internal clock
6. Tolerance depends on the temperature; (typically zero at T
temperature range limit.
= 27°C), maximum tolerance values are measured at the
amb
7. Power-down mode. During power-down all static currents are switched-off.
8. For TC0 to TC7
46/61
STE2002
Electrical characteristics
6.3
AC operation
VDD1 = 1.7 to 3.6V; VDD2 = 1.75 to 4.2V; Vss1,2 = 0V; VLCD = 4.5 to 14.5V; Tamb = 25°C;
unless otherwise specified.
Table 27. AC operation
Symbol Parameter
Test condition
Min.
Typ.
Max.
Unit
Internal oscillator (Figure 47)
Internal oscillator
frequency
FOSC
VDD = 2.8V;
61
20
72
83
kHz
kHz
External oscillator
frequency
FEXT
100
FFRAME
Tw(RES)
Frame frequency
fosc or fext = 72 kHz(1)
75
Hz
µs
µs
RES LOW pulse width
Reset pulse rejection
5
1
5
TLOGIC
Internal logic reset time
µs
µs
(RES)
TVDD
VDD1 vs. VDD2 delay
0
I2C Bus interface(4) (Figure 48)
Fast Mode
DC
DC
400
3.4
kHz
High Speed Mode;
Cb=100pF
MHz
(max);VDD1=2
FSCL
SCL clock frequency
High Speed Mode;
Cb=400pF (max);
DC
1.7
MHz
VDD1=2
Fast Mode; VDD1=1.7V
Cb=100pF(2) (3)
400
KHz
ns
Set-up time (repeated)
START condition
TSU;STA
THD;STA
TLOW
160
160
160
60
Hold time (repeated)
START condition
Cb=100pF(2) (3)
Cb=100pF (2) (3)
Cb=100pF(2) (3)
ns
ns
ns
LOW period of the SCLH
clock
HIGH period of the
SCLH clock
THIGH
TSU;DAT
THD;DAT
Data set-up time
Data hold time
Cb=100pF (2) (3)
Cb=100pF (2) (3)
10
40
10
ns
ns
ns
T
Rise time of SCLH signal Cb=100pF (2) (3)
r;CL
Rise time of SCLH signal
after a repeated START
Cb=100pF (2) (3)
T
10
10
ns
ns
rCL1
condition and after an
acknowledge bit
TfCL
Fall time of SCLH signal Cb=100pF (2) (3)
47/61
Electrical characteristics
STE2002
Unit
Table 27. AC operation (continued)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
T
Rise time of SDAH signal Cb=100pF(2) (3) (4)
Fall time of SDAH signal Cb=100pF (2) (3) (4)
Rise time of SDAH signal Cb=400pF(2) (3) (4)
Fall time of SDAH signal Cb=400pF(2) (3) (4)
10
10
20
20
ns
ns
ns
ns
rDA
TfDA
80
T
rDA
TfDA
160
Set-up time for STOP
Cb=100pF(2) (3)
condition
TSU;STO
160
100
ns
pF
Capacitive load for SDAH
and SCLH
Cb
Cb
400
400
Capacitive load for SDAH
+ SDA line and SCLH +
SCL line
pF
Parallel interface (Figure 49, Figure 50)
TCY(EN)
TW(EN)
TSU(A)
TH(A)
Enable Cycle Time
Enable Pulse width
Address Set-up Time
Address Hold Time
Data Set-Up Time
Data Hold Time
150
60
30
40
30
30
ns
ns
ns
ns
ns
ns
VDD1 = 1.7V; Write-(2) (5)
TSU(D)
TH(D)
Data Set-Up Time in
read Mode
TSU(D)
THU(D)
100
ns
ns
Data Hold Time In Read
mode
100
48/61
STE2002
Electrical characteristics
Table 27. AC operation (continued)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
Serial interface (Figure 51)
TCYC
TPWH1
TPWL1
TS2
Clock Cycle SCLK
SCLK pulse width HIGH
SCLK Pulse width LOW
SCE setup time
150
60
60
30
50
50
30
40
30
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TH2
SCE hold time
TPWH2
TS3
SCE minimum high time
SD/C setup time
V
DD1 = 1.7V; Write(2) (5)
TH3
SD/C hold time
TS4
SDIN setup time
TH4
SDIN hold time
TS5
SOUT Access Time
100
100
SOUT Disable Time vs.
SCLK
TH5
ns
ns
SOUT Disable Time vs.
SCE
TH6
100
fos
1. Fframe = --------
960
2. All timing values are valid within the operating supply voltage and ambient temperature ranges and referenced to V and
IL
V
with an input voltage swing of V to V
SS DD
IH
3. Cb is the capacitive load for each bus line.
4. For bus line loads Cb between 100 and 400pF the timing parameters must be linearly interpolated
5. is the filtering Capacitor on VLCDOUTT and T (30%-70%) = 10 ns
C
VLCD
rise
fall
49/61
Electrical characteristics
Figure 47. RESET timing diagram
STE2002
Tw(res)
Tlogic(res)
VDD2
VDD1
RES
INPUTS
I/O
(HOST)
I/O
(DRIVER)
Hi-Z
Hi-Z
INTERFACE
OUTPUT
OSCIN
(HOST)
OSC OUT
(DRIVER)
BSY FLG
RESET
TABLE
LOADED
LR0118
2
Figure 48. I C-bus timings
Sr
Sr P
t
t
rDA
fDA
SDAH
SCLH
t
HD;DAT
t
HD;STA
t
SU;DAT
t
SU;STA
t
fCL
t
t
t
rCL1
rCL
rCL1
(1)
(1)
t
t
t
t
LOW HIGH
HIGH LOW
D00IN1153
=
=
MCS current source pull-up
Rp resistor pull-up
50/61
STE2002
Pad coordinates
Figure 49. Parallel interface write timing
PD/C
t
t
W(en)
SU(A)
t
h(A)
E
t
t
SU(D) HO(D)
t
CY(en)
DB0-DB7
R/W
WRITE
Figure 50. Parallel interface read timing
PD/C
Don't Care
t
t
W(en)
SU(A)
t
h(A)
E
t
HOR(D)
t
SUR(D)
t
CY(en)
DB0-DB7
R/W
READ
Figure 51. Serial interface timing
t
S2
t
H2
t
PWH2
CS
t
S3
t
H3
D/C
t
CYC
t
t
WH1
PWL1
t
S2
SCLK
SDIN
SOUT
t
S4
t
H4
t
H6
t
S5
t
H5
LR0001
7
Pad coordinates
See Table 28: Pad coordinates and Table 29: Alignment marks coordinates.
51/61
Pad coordinates
STE2002
Table 28. Pad coordinates
Name
Pad
X (µm)
Y(µm)
Name
Pad
X (µm)
Y(µm)
C0
C1
1
-3275.0
-3225.0
-3175.0
-3125.0
-3075.0
-3025.0
-2975.0
-2925.0
-2875.0
-2825.0
-2775.0
-2725.0
-2675.0
-2625.0
-2575.0
-2525.0
-2475.0
-2425.0
-2375.0
-2325.0
-2275.0
-2225.0
-2175.0
-2125.0
-2075.0
-2025.0
-1975.0
-1925.0
-1875.0
-1825.0
-1775.0
-1725.0
-1675.0
-1625.0
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
C34
C35
C36
C37
C38
C39
C40
C41
C42
C43
C44
C45
C46
C47
C48
C49
C50
C51
C52
C53
C54
C55
C56
C57
C58
C59
C60
C61
C62
C63
C64
C65
C66
C67
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
-1575.0
-1525.0
-1475.0
-1425.0
-1375.0
-1325.0
-1275.0
-1225.0
-1175.0
-1125.0
-1075.0
-1025.0
-975.0
-925.0
-875.0
-825.0
-775.0
-725.0
-675.0
-625.0
-575.0
-525.0
-475.0
-425.0
-375.0
-325.0
-275.0
-225.0
-175.0
-125.0
+125.0
+175.0
+225.0
+275.0
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
2
C2
3
C3
4
C4
5
C5
6
C6
7
C7
8
C8
9
C9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
52/61
STE2002
Pad coordinates
Table 28. Pad coordinates (continued)
Name
Pad
X (µm)
Y(µm)
Name
Pad
X (µm)
Y(µm)
C68
C69
C70
C71
C72
C73
C74
C75
C76
C77
C78
C79
C80
C81
C82
C83
C84
C85
C86
C87
C88
C89
C90
C91
C92
C93
C94
C95
C96
C97
C98
C99
C100
C101
C102
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
+325.0
+375.0
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
C103
C104
C105
C106
C107
C108
C109
C110
C111
C112
C113
C114
C115
C116
C117
C118
C119
C120
C121
C122
C123
C124
C125
C126
C127
R40
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
+2075.0
+2125.0
+2175.0
+2225.0
+2275.0
+2325.0
+2375.0
+2425.0
+2475.0
+2525.0
+2575.0
+2625.0
+2675.0
+2725.0
+2775.0
+2825.0
+2875.0
+2925.0
+2975.0
+3025.0
+3075.0
+3125.0
+3175.0
+3225.0
+3275.0
+3571.5
+3571.5
+3571.5
+3571.5
+3571.5
+3571.5
+3571.5
+3571.5
+3571.5
+3571.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-946.5
-875.0
-825.0
-775.0
-725.0
-675.0
-625.0
-575.0
-525.0
-475.0
-425.0
+425.0
+475.0
+525.0
+575.0
+625.0
+675.0
+725.0
+775.0
+825.0
+875.0
+925.0
+975.0
+1025.0
+1075.0
+1125.0
+1175.0
+1225.0
+1275.0
+1325.0
+1375.0
+1425.0
+1475.0
+1525.0
+1575.0
+1625.0
+1675.0
+1725.0
+1775.0
+1825.0
+1875.0
+1925.0
+1975.0
+2025.0
R41
R42
R43
R44
R45
R46
R47
R48
R49
53/61
Pad coordinates
STE2002
Table 28. Pad coordinates (continued)
Name
Pad
X (µm)
Y(µm)
Name
Pad
X (µm)
Y(µm)
R50
R51
R52
R53
R54
R55
R56
R57
R58
R59
R60
R61
R62
R63
R64
R65
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
+3571.5
+3571.5
+3571.5
+3571.5
+3571.5
+3571.5
+3571.5
+3571.5
+3571.5
+3571.5
+3571.5
+3571.5
+3571.5
+3571.5
+3571.5
+3571.5
-375.0
-325.0
-275.0
-225.0
-175.0
-125.0
-75.0
TEST_4
TEST_5
TEST_6
TEST_7
TEST_8
TEST_9
TEST_10
VSSAUX
SA1
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
+2675.0
+2625.0
+2575.0
+2525.0
+2475.0
+2425.0
+2375.0
+2225.0
+2175.0
+2125.0
+2075.0
+2025.0
+1975.0
+1925.0
+1875.0
+1825.0
+946.5
+946.5
+946.5
+946.5
+946.5
+946.5
+946.5
+946.5
+946.5
+946.5
+946.5
+946.5
+946.5
+946.5
+946.5
+946.5
-25.0
+25.0
+75.0
SA0
+125.0
+175.0
+225.0
+275.0
+325.0
+375.0
EXT
SEL2
SEL1
ICON_MODE
OSC_IN
VDD1_1
R66
155
+3571.5
+425.0
VDD1_2
189
+1825.0
+839.5
R67
R68
R69
R70
R71
R72
R73
R74
R75
R76
R77
156
157
158
159
160
161
162
163
164
165
166
+3571.5
+3571.5
+3571.5
+3571.5
+3571.5
+3571.5
+3571.5
+3571.5
+3571.5
+3275.0
+3225.0
+475.0
+525.0
+575.0
+625.0
+675.0
+725.0
+775.0
+825.0
+875.0
+946.5
+946.5
VDD1_3
VDD1_4
VDD1_5
VDD1_6
VDD1_7
VDD1_8
VDD1_9
VDD1_10
VDD1_11
VDD1_12
VDD2_1
190
191
192
193
194
195
196
197
198
199
200
+1775.0
+1775.0
+1725.0
+1725.0
+1675.0
+1675.0
+1625.0
+1625.0
+1575.0
+1575.0
+1525.0
+946.5
+839.5
+946.5
+839.5
+946.5
+839.5
+946.5
+839.5
+946.5
+839.5
+946.5
R78
167
+3175.0
+946.5
VDD2_2
201
+1525.0
+839.5
R79
168
169
170
171
172
+3125.0
+3075.0
+2825.0
+2775.0
+2725.0
+946.5
+946.5
+946.5
+946.5
+946.5
VDD2_3
VDD2_4
VDD2_5
VDD2_6
VDD2_7
202
203
204
205
206
+1475.0
+1475.0
+1425.0
+1425.0
+1375.0
+946.5
+839.5
+946.5
+839.5
+946.5
R80/ICON
TEST_1
TEST_2
TEST_3
54/61
STE2002
Pad coordinates
Table 28. Pad coordinates (continued)
Name
Pad
X (µm)
Y(µm)
Name
Pad
X (µm)
Y(µm)
VDD2_8
VDD2_9
VDD2_10
VDD2_11
VDD2_12
BUSY_FLAG
SDOUT
SDIN
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
+1375.0
+1325.0
+1325.0
+1275.0
+1275.0
+1125.0
+975.0
+925.0
+875.0
+825.0
+775.0
+625.0
+575.0
+525.0
+475.0
+839.5
+946.5
+839.5
+946.5
+839.5
+946.5
+946.5
+946.5
+946.5
+946.5
+946.5
+946.5
+946.5
+946.5
+946.5
VSS_6
VSS_7
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
-1075.0
-1125.0
-1125.0
-1175.0
-1175.0
-1225.0
-1225.0
-1275.0
-1275.0
-1325.0
-1325.0
-1375.0
-1375.0
-1425.0
-1425.0
+839.5
+946.5
+839.5
+946.5
+839.5
+946.5
+839.5
+946.5
+839.5
+946.5
+839.5
+946.5
+839.5
+946.5
+839.5
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
SD/C
SCE
SCLK
VSSAUX
R/W
D7
D6
D5
D4
D3
222
223
224
+425.0
+375.0
+325.0
+946.5
+946.5
+946.5
TEST_11
TEST_12
TEST_13
256
257
258
-1475.0
-1525.0
-1575.0
+946.5
+946.5
+946.5
D2
D1
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
+275.0
+225.0
+175.0
+125.0
+75.0
+946.5
+946.5
+946.5
+946.5
+946.5
+946.5
+946.5
+946.5
+946.5
+946.5
+946.5
+946.5
+839.5
+946.5
+839.5
+946.5
TEST_14
OSC_OUT
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
-1625.0
-2175.0
-2325.0
-2325.0
-2375.0
-2375.0
-2425.0
-2425.0
-2475.0
-2475.0
-2525.0
-2525.0
-2575.0
-2575.0
-2625.0
-2625.0
+946.5
+946.5
+946.5
+839.5
+946.5
+839.5
+946.5
+839.5
+946.5
+839.5
+946.5
+839.5
+946.5
+839.5
+946.5
+839.5
D0
VLCDIN_1
PD/C
VLCDIN_2
E
VLCDIN_3
RES
-75.0
VLCDIN_4
VSSAUX
SDA_OUT
SDA_OUT
SDA_IN
SCL
-225.0
-275.0
-325.0
-375.0
-425.0
-975.0
-975.0
-1025.0
-1025.0
-1075.0
VLCDIN_5
VLCDIN_6
VLCDIN_7
VLCDIN_8
VLCDIN_9
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VLCDIN_10
VLCDSENSE_1
VLCDSENSE_2
VLCDOUT_1
VLCDOUT_2
55/61
Pad coordinates
STE2002
Table 28. Pad coordinates (continued)
Name
Pad
X (µm)
Y(µm)
Name
Pad
X (µm)
Y(µm)
VLCDOUT_3
VLCDOUT_4
VLCDOUT_5
VLCDOUT_6
VLCDOUT_7
VLCDOUT_8
VLCDOUT_9
275
276
277
278
279
280
281
-2675.0
-2675.0
-2725.0
-2725.0
-2775.0
-2775.0
-2825.0
+946.5
+839.5
+946.5
+839.5
+946.5
+839.5
+946.5
R13
R12
R11
R10
R9
309
310
311
312
313
314
315
-3571.5
-3571.5
-3571.5
-3571.5
-3571.5
-3571.5
-3571.5
-175.0
-225.0
-275.0
-325.0
-375.0
-425.0
-475.0
R8
R7
VLCDOUT_10
R39
282
283
-2825.0
-3075.0
+839.5
+946.5
R6
316
-3571.5
-525.0
-575.0
R5
317
-3571.5
R38
R37
R36
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
R25
R24
R23
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
-3125.0
-3175.0
-3225.0
-3275.0
-3571.5
-3571.5
-3571.5
-3571.5
-3571.5
-3571.5
-3571.5
-3571.5
-3571.5
-3571.5
-3571.5
-3571.5
+946.5
+946.5
+946.5
+946.5
+875.0
+825.0
+775.0
+725.0
+675.0
+625.0
+575.0
+525.0
+475.0
+425.0
+375.0
+325.0
R4
R3
318
319
320
321
322
323
-3571.5
-3571.5
-3571.5
-3571.5
-3571.5
-3571.5
-625.0
-675.0
-725.0
-775.0
-825.0
-875.0
R2
R1
R0
ICON
R22
300
-3571.5
+275.0
R21
R20
R19
R18
301
302
303
304
-3571.5
-3571.5
-3571.5
-3571.5
+225.0
+175.0
+125.0
+75.0
R17
305
-3571.5
+25.0
R16
R15
306
-3571.5
-25.0
-75.0
307
-3571.5
56/61
STE2002
Pad coordinates
Marks
Table 29. Alignment marks coordinates
X
Y
-3574.5
+3574.5
-2250
-949.5
-949.5
+949.5
+949.5
mark1
mark2
mark3
mark4
+1200
Figure 52. Alignment marks dimensions
39 µm
94 µm
57/61
Mechanical data
STE2002
8
Mechanical data
Table 30. Bumps
Bump number
Dimensions
1-187
212-235
256-260
283-323
Bumps on single row size
Bumps on two rows size
30µm x 98 µm x 17.5
188-211
236-255
261-282
30µm x 87 µm x 17.5
Pad size
1-323
1-323
1-323
43µm x 107µm
50µm
Pad pitch
Spacing between bumps
20µm
Table 31. Die mechanical dimensions
Die size
2.07mm x 7.32mm
Wafers thickness
500µm
Figure 53. Die orientation in tray
DIE IDENTIFICATION
Mark 3
Mark 4
Mark 2
STE2002
Mark 1
58/61
STE2002
Mechanical data
Figure 54. Tray information
A
A
Array Size = 13 x5 (65) Units
59/61
Ordering information
STE2002
9
Ordering information
Table 32. Order codes
Part numbers
Type
STE2002DIE1
STE2002DIE2
Bumped wafers
Bumped dice on waffle pack
10
Revision history
Table 33. Document revision history
Date
Revision
Changes
15-Sep-2002
1
Initial release.
Updated suppy current values, LCD supply voltage accuracy, Internal
Oscillator frequency range
15-Sep- 2005
12-Dec-2006
2
3
Reviewed the Junction operating temperature range in Table 25:
Absolute maximum ratings and added a footnote.
60/61
STE2002
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