STLC5444FN [STMICROELECTRONICS]
QUAD FEEDER POWER SUPPLY; QUAD馈线电源
| 型号： | STLC5444FN |
| 厂家： | 
ST |
| 描述： | QUAD FEEDER POWER SUPPLY |
| 文件： | 总17页 (文件大小：142K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STLC5444
QUAD FEEDER POWER SUPPLY
SUPPLIES POWER FOR UP TO FOUR DIGI-
TAL TELEPHONELINES
CONFORMS TO THE CCITT RECOMMEN-
DATIONS FOR POWER FEED AT THE S OR
T REFERENCE POINTS
SUPPORTS POINT-TO-POINT AND POINT
TO MULTIPOINT CONFIGURATIONS
EACH OF THE FOUR LINES IS INDIVIDU-
ALLY CONTROLLED
HIGH-VOLTAGE BCD TECHNOLOGY SUP-
PORTING UP TO -130V
DIP24
PLCC44
AUTOMATIC THERMAL SHUTDOWN
ORDERING NUMBERS: STLC5444B1 (DIP24)
STLC5444FN (PLCC44)
STATUS CONDITION DETECTION (BY MI-
CROPROCESSOR) FOR EACH LINE:
– Lowoutput voltage
– Openloop
– Current overload
– Thermal overload
DIP24 PIN CONNECTION (Top view)
– Normal line condition
PROGRAMMABLE CURRENT LIMITING
OUTPUT CURRENT UP TO 120mA
DESCRIPTION
The ISDN Quad Feeder Power Supply (IQFPS)
provides a power source for up to four line inter-
faces. The power source to the device is a local
battery or a centralized regulated power supply.
It can operate in point-to-point and point-to-mul-
tipoint configurations as far as S interface is con-
cerned.
By the device microprocessor interface, each
powered line is individually controlled and moni-
tored.
Therefore, overloads and faults are easy to detect
and localize even in a large system.
D1
D0
1
24
23
22
21
20
19
18
17
16
15
14
13
D2
2
D3
INT
3
A0
BGND
VCC
ILIM
N.C.
VBB
N.C.
S0
4
DGND
ALE
WR
5
6
7
CS
8
RD
The status conditions detected by the device on
each line that may be read by the microprocessor
are :
9
RESET
S3
10
11
12
low output voltage
openloop
current overload
thermal overload
normal line conditions
S1
RSRVD
S2
VBB
D94TL102
A hardware current limiting programmable feature
is available.
1/17
December 1997
STLC5444
PLCC44 PIN CONNECTION (Top view)
6
5
4
3
2
1
44 43 42 41 40
VBB
N.C.
BGND
N.C.
VCC
ILIM
7
39
38
37
36
35
34
33
32
31
30
29
VBB
N.C.
N.C.
DGND
ALE
N.C.
WR
8
9
10
11
12
13
14
15
16
17
N.C.
N.C.
VBB
N.C.
VBB
CS
RD
RESET
VBB
18 19 20 21 22 23 24 25 26 27 28
D94TL103
BLOCK DIAGRAM
THERMAL
OVERLOAD
STATUS GROUP BUS
STATUS
DETECTOR
MUX
LINE ENABLE REGISTER BUS
S DRIVERS
DISABLE
LINE
STATUS
BUS
ADDRESS
BUS 0/2
S
O/3
LINE
S0
DRIVERS
S1
INPUT BUS D3/D0
INDIRECT
S2
ADDRESS
REGISTER
ENABLE
REGISTER
S3
VBB(12)
BIT 3
INT EN
IAR EN
LER EN
BGND
DGND
VCC
µP
INTERFACE
VOLTAGE
REFERENCE
OUTPUT
BUS D3/D0
VBB(8)
D94TL104B
ALE
A0
CS D3/D0 RD
WR
INT RESET
ILIM
2/17
STLC5444
PIN DESCRIPTION
No
Name
No
DIP
Function
PLCC
D1
1
1
Bit 1 of the tri state I/O data bus
No connection
NC
2,4,8,10,
13,14,
16,18,
20,23,
25,26,
28,34,
37,38,44
7,9
D0
INT
VBB
3
5
2
3
Bit 0 of the tri state I/O data bus
Active low interrupt output for the µP (open drain)
6,7
8,12
Battery supply line (negative battery‘s terminal)
15,17
22,29,
39,40
BGND
VCC
ILIM
S0
9
4
Battery ground line
11
12
19
21
24
–
5
+5V supply line
6
Current limit programming
10
11
13
14
15
16
17
18
19
20
21
22
23
24
Output of the power switch controller 0
Output of the power switch controller 1
Output of the power switch controller 2
Reserved pin: it must be left floating
Output of the power switch controller 3
Active high reset input
S1
S2
RSRVD
S3
27
30
31
32
33
35
36
41
42
43
RESET
RD
Active low read input
CS
Active low chip select input
Active low write input
WR
ALE
DGND
A0
Active high address latch enable
Digital ground
Address bit for R/W operations on the data bus
Bit 3 of the I/O tri state data bus
Bit 2 of the I/O tri state data bus
D3
D2
FUNCTIONAL DESCRIPTION
ADDRESS LINE (Input)
BGND - Ground Battery
CS - Chip Select (Input; Active Low)
A0 selects source and destination locations for
read and write operations on the data bus. A0
must be valid on the falling edge of ALE or during
RD and WR if ALE is tied High.
CS must be Low to enable the read or write op-
erations of the device. Data transfer occurs over
the D3-D0 lines.
D3-D0 - DATA BUS (Input/Output; Three-State)
ALE - Address Latch Enable (Input; Active
High)
The four bidirectional data bus lines are to ex-
change information with a microprocessor. D0 is
the least significant bit and D3 is the most signifi-
cant bit. A High on the data bus corresponds to a
logical 1. These lines act as input when WR and
CS are active and as output when RD and CS are
active. When CS is inactive, the D3-D0 pins are
placed in a high-impedancestate.
ALE is an input control pulse used to strobe the
address on the A0 line into the address latch.
This signal is active High to admit the input ad-
dress. The address is latched on the High-Low
transition of ALE. While ALE is High, the address
latch is transparent. For an unmultiplexed micro-
processor bus, ALE must be tied High.
3/17
STLC5444
transferredto D3-D0.
FUNCTIONAL DESCRIPTION (continued)
DGND - Ground Digital
RESET - Reset (Input; Active High)
RESET initialize the registers in the device, leav-
ing the drivers switched off.
ILIM - Current Limit Programming (Input)
ILIM programs the current limit of the Output driv-
ers using an external resistor connected between
ILIM and VBB. The ILIM pin is 1.25V more posi-
tive than VBB. The current limit is 5mA plus 1000
times the current in the external resistor. The pro-
grammed current limit applies to each driver.
S3-S0 - Drivers(Output)
S3-S0 each supply power to one line. The outputs
can sink up to 120 mA each. The voltage at the
line is connectedto VBB through a DMOS switch.
INT - Interrupt (Output; Open-Collector, Active
Low)
VBB - Battery Voltage (input)
INT augments the Microprocessor Interface by
generating an interrupt when a Current Overload
Detector (COD) occurs. INT is active whenever
any bits in the COD register are active. INT is not
latched; when the COD register is zero, INT goes
inactive (High). INT will also go inactive if the
IQFPS automatically disables the S-output driver
that caused the interrupt (due to Thermal Over-
load), or if the microprocessor disables that line
via the Line Enable Register (LER). COD inter-
rupts can be masked via the Indirect Address
Register (IAR); RESET always disables the INT
pin.
VBB is the internal negative supply voltage. VBB
must always be connected to the most negative
supply voltage. The MPI Registers will not func-
tion properly when the battery power is discon-
nected, that is, when VBB is floating or grounded.
The IQFPS should also be reset if a drastic tran-
sient is applied to VBB.
VCC - +5V Power Supply (Input)
WR - Write (Input; Active Low)
RD - Read (Input; Active Low)
The active Low write signal is conditioned by CS
and transfers information from the data bus to an
internal register selected by A0. If A0 is a logical
1, D3-D0 is written into the Line Enable Register
(LER). If A0 is a logical 0, D3-D0 is written into
the IAR. LER and IAR are the only two writable
registers in the device.
The active Low read signal is conditioned by CS
and transfers internal information to the data bus.
If A0 is a logical 0, logic levels of the Indirect Ad-
dress Register (IAR) and Thermal Shutdown
Status bit will be transferred to D3-D0. If A0 is a
logical 1, the data addressed by the IAR will be
4/17
STLC5444
DC CHARACTERISTICS (VBB = -54V; VCC = 5V; unless otherwise specified)
Symbol
VIH
Parameter
Input Voltage High Level
Input Voltage Low Level
High Level Output Current
Low Level Output Current
High Level Input Current
Low Level Input Current
Output Hi-Z Current High
Output Hi-Z Current Low
VCC supply Current
Test Conditions
Min.
Typ.
Max.
Unit
V
2
VIL
0.8
V
IOH
VOH = 2.4V
400
2
µA
mA
µA
µA
µA
µA
mA
pF
V
IOL
VOL = 0.4V
IIH
VIH = 2V
10
60
10
10
5
IIL
VIL = 0.8V
IOZH
IOZL
ICC
2.4V < VOZ < VCC
0V < VOZ < 0.4V
1.4
10
CL
Logic I/O Capacitance
Saturation Voltage
VSAT
Ron
IBB
IS = 80mA
2
25
6
Output DMOS Saturation Resistivity IS = 80mA
Ω
VBB Supply Current
VBB = -54V, RLIM = 26.6KΩ,
Output Disabled
3.2
mA
I
Delta Limit Current vs.
Theoretical Programmed Value
ISLIM
RLIM = 26.6K , VBB = -96V
10%
±
∆
Ω
SLIM
RLIM = 10.9KΩ, VBB = -54V
VLVD
Low Voltage Detector Threshold
S3 - S0 output active
2.7
75
3
3
3.3
90
V
%
(relative to VBB
)
ISOL
Current Overload Detector
Threshold (as % of ISLIM
)
ISOC
ISZ
Open Loop Detector Threshold
1.5
4
mA
Si Leakage Current to ground @
Si disabled
VBB = -110V
100
A
µ
HLVD
HOLD
HCOD
Low Voltage Detector Hysteresis
Open Loop Detector Hysteresis
18
0.6
2.4
200
1.6
4.0
mV
mA
mA
Current Overload Detector
Hysteresis
H1
H2
130 C Thermal Detector
Hysteresis
10
10
80
C
°
°
160°C Thermal Detector
Hysteresis
°C
µs
TH1
Thermal Overload Recovery
Time H1
5/17
STLC5444
SWITCHING CHARACTERISTICS (VBB = -54V;VCC = 5V; unlessotherwise specified)
MICROPROCESSOR READ/WRITE TIMING NON MULTIPLEXED MODE (for references see figure 1a
and 2b).
Symbol
tRLRH
tRHRL
Parameter
Min.
260
200
220
Max.
Unit
ns
ns
ns
RD, CS pulse width
RD, recovery time
Tamb: 0 to 70°C
T
amb: -40 to 0°C and +70°C to +85°C
tRLDA
tRHDZ
RD, CS low to data available
RD or CS high to data Z
260
130
160
ns
ns
ns
Tamb: 0 to 70°C
amb: -40 to 0°C and +70°C to +85°C
T
tASRL
tAHRH
tASWL
tAHWH
tADDA
Address setup time to READ active
Address hold time to READ inactive
Address setup time to WRITE active
Addess hold time to WRITE inactive
Address stable to data available
0
0
30
50
360
390
ns
ns
ns
ns
ns
ns
Tamb: 0 to 70°C
T
amb: -40 to 0°C and +70°C to +85°C
tWLWH
tWHWL
tDAWH
tWHDZ
WR or CS pulse width
Write recovery time
Data setup time
200
200
100
20
40
ns
ns
ns
ns
ns
Data hold time
Tamb: 0 to 70°C
amb: -40 to 0°C and +70°C to +85°C
T
tRES
Reset Pulse with
200
ns
Note: AC timingsare tested at 0.8V and 2V with input levels of 0.4V and 2.4V.
SWITCHING CHARACTERISTICS (VBB = -54V;VCC = 5V; unlessotherwise specified)
MICROPROCESSOR READ/WRITE TIMING MULTIPLEXED MODE (for references see figure 1 and 2).
Symbol
tRLRH
tRHRL
Parameter
Min.
260
200
220
Max.
Unit
ns
ns
ns
RD, CS pulse width
RD, recovery time
Tamb: 0 to 70°C
T
amb: -40 to 0°C and +70°C to +85°C
tRLDA
tRHDZ
RD, CS low to data available
260
130
160
ns
ns
ns
RD or CS high to data Z
Tamb: 0 to 70°C
amb: -40 to 0°C and +70°C to +85°C
T
tAHAL
tADAL
tADAZ
tAZRL
tAZWL
tADDA
ALE pulse width
100
60
50
0
0
360
390
ns
ns
ns
ns
ns
Address setup time
Address hold time
Address Z to RD low
Address Z to WR Low
Address stable to data available
Tamb: 0 to 70°C
amb: -40 to 0°C and +70°C to +85°C
ns
ns
T
tWLWH
tWHWL
tDAWH
tWHDZ
WR or CS pulse width
Write recovery time
Data setup time
200
200
100
20
40
ns
ns
ns
ns
ns
Data hold time
Tamb: 0 to 70°C
amb: -40 to 0°C and +70°C to +85°C
T
tRES
Reset Pulse with
200
ns
Note: AC timingsare tested at 0.8V and 2V with input levels of 0.4V and 2.4V.
Si Timing (at 10% of final value)
Symbol
tEN
tDIS
Parameter
Si output enable time (from LER)
Si output disable time (from LER or RESET)
Test condition
RLOAD = 3kΩ
Typ.
2
3
Max.
5
6
Unit
µs
µs
6/17
STLC5444
Figure 1: MicroprocessorRead Timing.
t
AHAL
ALE
t
t
ADAZ
ADAL
A
O
t
(Note 1)
CLRL
t
(Note 2)
RHCH
CS
RD
t
AZRL
t
RHRL
t
ADDA
t
RLRH
t
RHDZ
t
RLDA
DATA
Read Data
D94TL108A
Notes:
1 - If tCLRL is negative, tRHRL, tRLRH, tAZRL, and tRLDA are measured from CS rather than RD.
2 - If tRHCH is negative, tRHRL, tRLRH and tRHDZ are measured from CS rather than RD.
When a read from the LER immediately follows a write to the LER a minimum of 1 µs is required between these operations.
Figure 2: MicroprocessorWrite Timing.
t
AHAL
ALE
t
t
ADAZ
ADAL
A
O
t
(Note 2)
WHCH
CS
t
WHWL
t
(Note 1)
CLWL
t
WR
WLWH
t
WHDZ
t
AZWL
t
DAWH
DATA
INT
Write Data
(Note 3)
D94TL109A
Notes:
1 - If tCLWL is negative tWHWL and tWLWH are measured from CS rather than WR.
2 - If tWHCH is negative, tWHWL, tWLWH, tDAWH and tWHDZ are measured from CS rather than WR.
The propagation delay from the writing of the T/I bit to the effect on the INT pin is approximately 1µs for both mask and enable operations.
7/17
STLC5444
Figure 1a: MicroprocessorRead Timing non multiplexed mode.
ALE
t
AHRH
A
O
t
(Note 1)
t
(Note 2)
RHCH
CLRL
CS
RD
t
ASRL
t
RHRL
t
ADDA
t
RLRH
t
RHDZ
t
RLDA
DATA
Read Data
D97TL301A
Notes:
1 - If tCLRL is negative, tRHRL, tRLRH, tAZRL, and tRLDA are measured from CS rather than RD.
2 - If tRHCH is negative, tRHRL, tRLRH and tRHDZ are measured from CS rather than RD.
When a read from the LER immediately follows a write to the LER a minimum of 1 µs is required between these operations.
Figure 2a: MicroprocessorWrite Timing non multiplexed mode.
ALE
t
t
AHWH
ASWL
A
O
t
(Note 2)
WHCH
CS
t
WHWL
t
(Note 1)
CLWL
t
WR
WLWH
t
WHDZ
t
DAWH
DATA
INT
Write Data
(Note 3)
D97TL302A
Notes:
1 - If tCLWL is negative tWHWL and tWLWH are measured from CS rather than WR.
2 - If tWHCH is negative, tWHWL, tWLWH, tDAWH and tWHDZ are measured from CS rather than WR.
The propagation delay from the writing of the T/I bit to the effect on the INT pin is approximately 1µs for both mask and enable operations.
8/17
STLC5444
*) Open Loop Detection
OPERATIVE DESCRIPTION.
Initialization
The open-loop status bit becomes active when
the current on the line drops below a minimum
value.
The device is initialized by the RESET pin. In this
state the analog drivers are switched off, the Indi-
rect Address Register (IAR) is cleared, and the in-
ternally latched address A0 is cleared.
*) Current Overload Detection
The current-overload status bits become active
when the current on the line nears the current
limit. These bits active the INT output if COD in-
terrupts are enabledvia the IAR Register.
Power at Output drivers
The voltage at the Output drivers is approximately
*) Thermal Overload Detection
If the device temperaturereaches 130oC, then
all the line drivers in the current-overloadcondi-
tion will be switched off and the corresponding
bits in the Thermal Overload Register will be
activated. If the device temperatureincreases
to 160oC, all the line drivers will be turned off,
and all the bits in the Thermal Overload Regis-
ter will be activated.
V
BB (more precisely: VBB - VSAT).
Analog Section
The analog section consists of four line drivers,
which are DMOS transistor switches capable of
sinking up to 120 mA each. The power to the driv-
ers is derived from the negative supply voltage
(VBB). The output voltage to each line is slaved to
VBB, and the voltage drop in each driver is ap-
proximately 1.5V.
Line driver protection is provided through the inte-
gration of current limit and over-temperatureshut-
off. The current limit is hardware-programmable
via an external resistor (RLIM) connected be-
tween ILIM and VBB.
The T-bit will also be set, and it can be read
along with the Indirect Address Register (IAR)
to indicate that all the drivers have been turned
off. To initialize any of the bits in the Thermal
OverloadRegister, the microprocessor must
first turn off the line drivers that must not be re-
activateduntil the T-bit in the address register
is cleared by the temperaturedetector in the
device.
The output limit is : 5mA + 1000 x 1.25V/RLIM.
This 1000 x gain makes the ILIM pin susceptible
to external noise, care should be taken to connect
RLIM as close as possible to the component.
MPI Section
The MPI allows the user to access the detectors
defined in the analog section. The line driver’s
status bits are grouped by function. Bits 3-0 of the
detectorscorrespondto lines 3-0, respectively.
The thermal shut-off is internally set at approxi-
mately 160oC.
At this temperatureall the drivers are uncondition-
ally switched off. However, at approximately
130oC, only the drivers that are in the current-
overload conditionwill be turned off.
The status group are :
Low Voltage Detector (LVD)
Open Loop Detector (OLD)
Current Overload Detector (COD)
Thermal Overload Register (TOR)
Status detectors, associated with each of the line
drivers, monitor the load conditions on each line
by comparing an electrical parameter (e.g., cur-
rent and voltage at the line) with reference level.
The output of each detector can be read by the
microprocessor. In addition to these status detec-
tors, the temperature of the device is monitored
via integrated temperature detectors. The detec-
tors respond at approximately 130oC and 160oC,
as defined above, and the 160oC detector can be
monitored by the microprocessor via the MPI. The
status detectors provide the following information
from each of the lines (all detectors have built-in
hysteresis):
The data is not latched in these status groups ex-
cept in the TOR.
Thus, the user should filter (multiple samples) the
received data to ensure its integrity. There are
two other registers in the MPI: the Indirect Ad-
dress Register (IAR), and Line Enable Register
(LER).
The IAR contains 3 bits that address the desired
status group or the LER. The IAR is read along
with the T-bit defined in the analog section. The
microprocessor can read the IAR to check the va-
lidity of the address. A 1us delay is required be-
tween a write to the LER register, followed by a
Read of the same register. Subsequent reads of
the LER do not have this constraint.
*) Low Output Voltage Detection
The low-output-voltagestatus bit becomesac-
tive when the voltage across the output DMOS
transistor exceeds the proper voltage threshold
(VLVD).
9/17
STLC5444
a transparent latch by ALE. The selection of the
status group or the LER is determined by the con-
tent of the IAR.
The LER is used to enable or disable the individ-
ual line drivers. The line drivers will only become
active if the corresponding bit in the TOR is inac-
tive. The LER is a read/write register.
The truth table for the MPI control is shown below
:
The MPI is the interface containing the following
pins :
CS RD WR A0
0
0
0
0
1
1
0
1
0
X
0
1
0
1
X
0
0
1
1
X
Write IAR (T bit is read only)
Read IAR and T bit
Write LER
D3-D0
A0
Bidirectional
Input
Data Bus
Address Line
Address Latch Enable
Read Enable
Write Enable
Chip Select
ALE
RD
Input
Read status groups or LER
No access
Input
WR
Input
CS
Input
INT
Output
Input
COD Interrupt
Reset pin
Indirect Address Register (IAR) and T/I Bit
RESET
The IAR is 3 bits wide and accessible through the
data port, D2-D0. The content of the Indirect Ad-
dress Register (IAR2-IARO) determines the se-
lection of the status groups or the LER. The ther-
mal overload bit T/I is read and written at the
same time as IAR and occupies D3.
The 4-bit bidirectional data bus (D3-D0) is used to
communicate with the registers. Access to the
registers is controlled by CS, RD, WR, ALE, and
A0 as shown below. A read or write cycle must be
preceded by a valid A0. A0 is latched internally in
This register has the following format :
Bit
Symbol
0
1
2
3
IARO
IAR1
IAR2
T/I
Bit 0 of the IAR
Bit 1 of the IAR
Bit 2 of the IAR
T bit: (Read only)
Logical 0: temperature normal (default value)
Logical 1: temperature above 160°C (all drivers shut off)
I bit
: (write only)
Logical 0: INT pin disabled
Logical 1: COD interrupts enabled via INT pin‘
IAR2-IAR0 address the status groups and the LER as shownbelow:
IAR2
IAR1
IAR0
Select
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
LVD
OLD
COD
LEC
RESERVED
RESERVED
LER
TOR
10/17
STLC5444
The contentsand format of the status groups and the LER are as follows :
LVD:
Bit
Logical 1
Logical 0 (default value)
0
1
2
3
O0 low voltage
O1 low voltage
O2 low voltage
O3 low voltage
O0 voltage normal
O1 voltage normal
O2 voltage normal
O3 voltage normal
The Low Voltage Detector (LVD) indicates the voltage level on the output lines, even when the lines are
disabled. The low-voltage condition becomes active (logical 1) if the output reaches the Low Voltage
Threshold(VLVD).
LEC:
Bit
Logical 1
Logical 0
0
1
2
3
SWITCH ON
SWITCH ON
SWITCH ON
SWITCH ON
SWITCH OFF
SWITCH OFF
SWITCH OFF
SWITCH OFF
The Line Enable Command (LEC) indicates the status of the DMOS SWITCH OUTPUT.
OLD:
Bit
Logical 1
Logical 0 (default value)
0
1
2
3
O0 open loop
O1 open loop
O2 open loop
O3 open loop
O0 current normal
O1 current normal
O2 current normal
O3 current normal
The Open Loop Detector (OLD) indicates the open-loop condition on the output lines. The open-loop
condition becomes active (logical 1) if the current on the line drops below the threshold value ISOC.
COD:
Bit
Logical 1
Logical 0 (default value)
0
1
2
3
O0 current overload
O1 current overload
O2 current overload
O3 current overload
O0 current normal
O1 current normal
O2 current normal
O3 current normal
The Current Overload Detector (COD) indicates the current-overload condition on the output lines. The
overload condition becomes active (logical 1) if the output current approaches the value programmed by
an externalresistor between ILIM and VBB.
TOR :
Bit
Logical 1 (default value)
Logical 0
0
1
2
3
O0 operational
O1 operational
O2 operational
O3 operational
O0 off
O1 off
O2 off
O3 off
The Thermal Overload Register (TOR) contains the overload status of the output line drivers. If the de-
vice temperature reaches 130oC, then the output line drivers that are in the current-overload condition
will be switched off. The corresponding bits in the TOR will be set to a logical 0. To initialize any of the
bits in the TOR, the microprocessor must first turn off the output line drivers via the LER. However, the
TOR bits cannot be deactivated if the 160oC detector is active. The µp may re-enable the output drivers
via the LER after the TOR condition is removed. The TOR is a read-onlyregister.
11/17
STLC5444
LER :
Bit
Logical 1
Logical 0 (default value)
0
1
2
3
O0 on
O1 on
O2 on
O3 on
O0 off
O1 off
O2 off
O3 off
The Line Enable Register (LER) is used to enable or disable the individual output line drivers. The output
line will only become active if the correspondingbit in the TOR is set to a logical 1. The LER can be writ-
ten directly and read indirectly.
ABSOLUTE MAXIMUM RATINGS (TA = 0°C to 70°C)
Parameter
Value
-0.4V to VCC
Voltage from Digital Input to DGND
Voltage from VCC to DGND
Voltage from VBB to DGND
100ns Pulse voltage from Si to DGND (See Notes)
Voltage from BGND to DGND
-0.4V to +7V
-130V to +0.4V
-130V to +2V
+0.5V, -3V
Storage Temperature
T = -60°C to +150°C
Note : Si stands for O0, O1, O2 or O3 outputs.
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol1
Min.
Max.
Units
°C
C
°
(*) Ambient Temperature
for standard type
TA
TA
0
-40
70
85
for ext. temperature type
Supply Voltage
VCC
VBB
DGND
BGND
4.75
-115
0
5.25
-38
0
V
V
V
V
-3
+0.5
Programmed Limiting Current
ISLIM
120
mA
Note: The test condition is specified with a diode in series withVBB
.
(*): Specifications in this data sheet are guaranteed by testing from 0°C to +70°C. For extended temperature range types, performance from
–40°C to +85°C is guaranteed by characterization and periodic sampling of production units.
ORDERING TYPES:
STLC5444B1,PDIP24 package: 0 to 70°C Temperature range.
STLC5444FN,PLCC44 package: 0 to 70°C Temperaturerange.
STLC5444B1-X,PDIP24 package:-40 to 85°C Temperature range.
STLC5444FN-X, PLCC44 package: -40 to 85°C Temperature range.
APPLICATION HINT
- if the Vbat pin is not connected, and the other
pins are normally biased, the chip generates
on it an open circuit voltage of +420mV.
- if all the other pins are normally biased and
the -Vbat pin forced at +600mV, a current of
10mA flows into it. At the same time from +5V
a current of 4mA is absorbed (this low current
from +5V simply means that no parasitic
latch-ups are triggered inside the chip). No
deteriorationof the device occurs.
In the Absolute Maximum Ratings table it is speci-
fied that the voltage applied on the -Vbat pin
should never exceed by more than 0.4V the volt-
age applied on the Ground pin.
As long as the external circuitry assures compli-
ance with the above, no more considerations are
needed.
In some cases however it may be not possible to
exclude that conditions may occur (hot insertion,
power supply transients, etc.) where the negative
supply has a transient overshoot above ground
voltage. Then a protection circuitry that clamps
such overshoot can add to the equipment reliabil-
ity. Such protection can be designed taking into
considerations that typically the devices behave
as follows:
- if all the other pins are normally biased, and
the -Vbat pin is forced at +1.5V for a transient
period, no deterioration of the device occurs.
Transient period can be considered any time
interval that lasts for less than 10µs and is not
repeated more than 5000 times during the
device lifetime.
12/17
STLC5444
COUNTER FEEDING
What considerations apply to the STLC5444 in
this case?
Let’suse a genericexample forreference(see Fig. 3)
It is possible that, in some applications,a commu-
nication channel that the STLC5444 feeds, is also
biased at the other end by another feeding de-
vice.
Figure 3: Typical PABX connection.
S
S
U
S
Si
Si
STLC5444
STLC5444
VBB
VBB
NT
PABX
D95TL229
A PABX with S-interfaces may have some of
them connected to Terminal Equipments, and one
to the S-interface of a Nertwork Termination. The
S-interface of the PABX connected to the NT has
one channel of the STLC5444 available for feed-
ing. It will be programmed in the ”OFF” state to
avoid interference with the feeding coming from
the NT (of course the feeding coming from the NT
will not be loaded by this PABX connection).
The following considerations are relevant in the
above example:
1) The VBB of the STLC5444 in the PABX must
be equal or more negative than the feeding
voltage coming from the NT (unless decou-
pling diodes are externallyprovided - see 4)
3) In the channel of the STLC5444 on the PABX
side, the only effect will be on the relevant
LVD bit that will be set to 1 if the feeding volt-
age coming from the NT is 3V more positive
than the local VBB. No interrupts or alarms are
generated.
4) It is good common practice to provide every S-
interface with protection circuitry against tran-
sient overvoltages(see Fig. 4). This includes a
diode in series with each Si pin of the
STLC5444. If this is the case, absolute levels
of local VBB and NT feeding are no concern at
all. (If such diodes are not present, care must
be paid to the power supply of the PABX, and
to the connected circuits. When the PABX
supply is OFF, the NT feeding will find a con-
nection through the relevant channel of the
STLC5444 to the VBB point).
2) The STLC5444 channel of the PABX must be
programmedOFF.
Figure 4: Protectionof the STLC5444against overvoltage.
D2
D3
BGND
BGND
D1
FUSE RESISTORS
S INTERFACE
TPAXX
Si
STLC5444
VBB
BATTERY
D95TL230
13/17
STLC5444
NOTE
Possible effect on the device of a Vbat variation
Be aware that a variation of Vbat during operation, when the switches are on can cause anomalous be-
haviour. To avoid that a turn-off occurs the variation should have a rise time equal or lower than
20V/µs (fig. 5), and a fall time equal or lower than 2.0V/µs (fig.6).
Figure 6: Typical fall time behaviour.
Figure 5: Typical rise time behaviour.
D97TL304
D97TL303
Vbat1
Vbat1
Fail dV/dt > 25V/µs
OK dV/dt < 2.0V/µs
OK dV/dt < 20V/µs
Fail dV/dt > 2.4V/µs
Vbat0
Vbat0
14/17
STLC5444
DIP24 PACKAGE MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
0.23
15.2
TYP.
0.63
0.45
MAX.
MIN.
0.009
0.598
MAX.
a1
b
0.025
0.018
b1
b2
D
E
0.31
0.012
1.27
0.050
32.2
1.268
0.657
16.68
e
2.54
0.100
1.100
e3
F
27.94
14.1
0.555
I
4.445
3.3
0.175
0.130
L
15/17
STLC5444
PLCC44 PACKAGE MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
17.4
16.51
3.65
4.2
TYP.
MAX.
17.65
16.65
3.7
MIN.
0.685
0.650
0.144
0.165
0.102
MAX.
0.695
0.656
0.146
0.180
0.108
A
B
C
D
4.57
2.74
d1
d2
E
2.59
0.68
0.027
14.99
16
0.590
0.630
e
1.27
12.7
0.46
0.71
0.050
0.500
0.018
0.028
e3
F
F1
G
0.101
0.004
M
M1
1.16
1.14
0.046
0.045
16/17
STLC5444
ESD - The SGS-THOMSON Internal Quality Standards set a target of 2 KV that each pin of the device should withstand in a series of tests
based on the Human Body Model (MIL-STD 883 Method 3015): with C = 100pF; R = 1500Ω and performing 3 pulses for each pin versus VCC
and GND.
Device characterization showed that, in front of the SGS-THOMSON Internaly Quality Standards, all pins of STLC5444 withstand at least
1000V.
The above points are not expected to represent a pratical limit for the correct device utilization nor for its reliability in the field. Nonetheless
they must be mentionned in connection with the applicability of the different SURE 6 requirements to STLC5444.
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-
THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.
1997 SGS-THOMSON Microelectronics – Printedin Italy – All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -
Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
17/17
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