STLC5460_技术文档

STLC5460

LINE CARD INTERFACE CONTROLLER

BOARD CONTROLLER FOR UP TO 16 ISDN

LINES OR 16 VOICE SUBSCRIBERS.

TWO SERIAL INTERFACES :

-PCM Four bidirectional multiplexes

-GCI One (or two) at 2 Mb/s.

NON BLOCKING SWITCH FOR 128 CHAN-

NELS (16, 32 OR 64 KB/S BANDWIDTH).

N CONSECUTIVE 64 kb/s CHANNELS FROM

AN INPUT MULTIPLEX CAN BE SWITCHED

AS A SINGLE N X 64 kbit/s CHANNEL TO AN

OUTPUT MULTIPLEX AT 2048 kb/s.

PLCC44

ORDERING NUMBER: STLC5460

TIME SLOT ASSIGNMENT FREELY PRO-

GRAMMABLE FOR EVERY CONNECTED

SUBSCRIBER.

PROGRAMMABLE PCM DATA RATES UP

TO 8192 kb/s.CONSTANT DATA RATE AT 2

Mb/s ON GCI SIDE.

PCM interface :

- Simple and doubleclock frequencyselectable;.

- Programmable clock shift

- Command/IndicateMonitorchannelsvalidated

or not

Microprocessor access to two selected bidirec-

tional channels of GCI and/or PCM.

Multicontrollers for layer 1 functions:

- C/I protocolcontrollerfor up to 16 C/I channels

- Monitor protocol controller for up to 16

Monitor channels.

Standard microprocessor interface with multi-

plexed address/data bus or separate address

data buses.

- Tristatemodecontrolsignals forexternaldrivers.

GCI interface :

- Six bits or fourbits Command/indicatechannel

selectablefor analog or digital equipment

PLCC44 pins PACKAGE

PIN CONNECTION (Topview)

6

5

4

3

2

1 44 43 42 41 40

A1

TSC0

TxD0

TSC1

TxD1

TSC2

TxD2

TSC3

TxD3

PFS

7

39

38

37

36

35

34

33

32

31

30

29

A3

8

DIN0

DIN1

VSS2

VDD2

FSC

9

10

11

12

13

14

15

16

17

DCL

INT

ALE/AS

NCS

PDC

RW/NWR

18 19 20 21 22 23 24 25 26 27 28

D94TL149B

1/54

February 1997

STLC5460

bandwidths, the STLC5460 can handle up to 16

ISDN subscribers with their 2B+D channel struc-

ture in GCI configuration, or up to 16 analog sub-

scribers. Since its interfaces can operate at differ-

ent data rates, the LCIC is an ideal device for

data rate adaptationbetween PCM interface up to

8Mb/s and GCI at 2Mb/s.

The device gives the possibility of checking the

correct communication inside the PBX or Public

Central Office providing :

DESCRIPTION

The Line Card Interface Controller, STLC5460, is

a monolithic switching device for the path control

of up to 128 channels of 16, 32, 64 kbps band-

width. Two consecutive 64 kbps channels may

also be handled as a quasi single 128 kbps chan-

nel. For these channels, the LCIC performs non-

blocking space time switching between two serial

interfaces: the system interface (or PCM inter-

face) and the general component interface (GCI).

PCM interface can be programmed to operate at

different data rates between 2048 and 8192 kbps.

The PCM interface consists of up to four duplex

ports with a tristate indication signal for each out-

put line. The GCI interface can be selected to be

PCM interface at 2Mbit/s.

- independentPCM delay setting

- PCM comparison function

-PseudoRandomSequenceGeneratorandAnalyser.

Moreover, the LCIC is one of the key building

blocks for networks with either central, distributed

or mixed signaling and packet data handling ar-

chitectures associated with ST5451 (HDLC con-

troller).

The device is controlled by a standard 8 bit paral-

lel microprocessor interface with a multiplexed

address-data bus. The device may optionally be

controlled by separate address and data buses.

The LCIC can be programmed to communicate

with GCI compatible devices such as STLC3040

(SLIC), STLC5411 (U interface) and others. The

device manages the layer 1 protocol buffering the

Command/Indicate and Monitor channels for GCI

compatible devices.

Due to its capability to switch channels of different

BLOCK DIAGRAM

DESTINATION REG

(ADDRESS)

COMMAND REG

(DATA)

SOURCE REGISTER

(DATA)

COMMAND MEMORY

194 WORDS OF 14 BITS

COUNTERS

6 bits

COUNTERS

1 bit for 16 tristate

SWITCHING

MEMORY

194 BYTES

(4PCM+2GCI + 2

CHANNEL -INSERTION- =

128+64+2=194)

4 PCM

2 GCI

4 PCM

2 GCI

SPECIAL

SERIAL

PARALLEL

SHIFTING

PARALLEL

SERIAL

SHIFTING

SWITCH AT

16, 32, 64

KB/S

C/I, MON

TRANSMIT

16 INDIPENDENT

CONTROLLERS

EXTRACTION

2 x 64 Kbit

CHANNEL

INSERTION

2 x 64 Kbit

CHANNEL

C/I, MON

RECEIVER

D94TL160A

2/54

STLC5460

PIN DEFINITIONSAND FUNCTIONS

Symbol

VDD1

A0

Pin number

Type (*)

Function

1

2

I

Supply Voltage 5V, 5% .

±

I (**)

Non Multiplexed Mode:

this input interfaces to the system’s address bus to select an internal

register for a read or write access.

Multiplexed Mode:

A0 at VDD, NRDY/NWAIT pin delivers NWAIT

A0 at VSS, NRDY/NWAIT pin delivers NREADY

RxD3

RxD2

RxD1

RxD0

3

4

5

6

I

Receive PCM interface Data : Serial data is received at these lines at

standard TTL or CMOS levels.

A1

7

I (**)

Non Multiplexed Mode:

this input interfaces to the system’s address bus to select an internal

register for a read or write access.

Multiplexed Mode:

A1 at VDD, NCS signal provided by the system is not inverted by the circuit.

A1 at VSS, NCS signal provided by the system is inverted by the circuit.

TSC0

TSC1

TSC2

TSC3

8

OD

O

Tristate control for the PCM interface. These lines are low when the

corresponding TxD outputs are valid.

10

12

14

TxD0

TxD1

TxD2

TxD3

9

Transmit PCM interface Data : Serial data is sent by these lines at standard

TTLor CMOS levels. These pins can be tristated.

11

13

15

PFS

PDC

A2

16

17

18

I

PCM interface frame synchronization pulse.

PCM interface data clock, single or double rate.

I (**)

Non Multiplexed Mode:

this input interfaces to the system’s address bus to select an intenal register

for a read or write access.

Multiplexed Mode:

A2 at VDD, AS/ALE signal providedby the system is not inverted by the circuit

A2 at VSS, AS/ALE signal provided by the system is inverted by the circuit

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

19

20

21

22

23

24

25

26

I/O

Address Data Bus. If the multiplexed address/data µP interface bus mode is

selected these pins transfer data and commands between the P and the

µ

STLC5460.

If a demultiplexed mode is used, these bits interface with the system data

bus.

VSS1

27

28

I

Ground : 0V

DS/NRD

Motorola like mode: Data Strobe

Intel Like Mode: Not Read

The signal indicates a read operation, active low

RW/NWR

NCS

29

30

I

Motorola like mode: Read/Write

Intel Like Mode: Not Write

The signal indicates a Write operation, active low.

Not Chip select. A low on this line selects the STLC5460 for a read/write

operation.

(*): (I) Input

(O) Output

(IO) In/Output

(OD) Open Drain

(**): With Pull up resistance.

3/54

STLC5460

PIN DEFINITIONSAND FUNCTIONS (continued)

Symbol

Pin n PLCC

Type

Function

AS/ALE

31

I

Multiplexed A/D mode:

used to latch the address from ADn

Non Multiplexed A/D Mode:

This pin at VSS indicates Intel like interfaces

This pin at VDD indicates Motorola like interfaces.

INT

DCL

FSC

VDD2

VSS2

DIN1

DIN0

A3

32

33

34

35

36

37

38

39

OD

Interrupt line, active low.

Data clock output.

Frame synchronization output.

Power supply : 5V

Ground.

0

O

I

GCI Data input 1

GCI Data input 0

I (**)

Non Multiplexed Mode:

this input interfaces to the system’s address bus to select an internal

register for a read or write access.

Multiplexed Mode:

A3 at VDD, DS/NRD signal provided by the system is not inverted by the

circuit

A3 at VSS, DS/NRD signal provided by the system isinverted by the circuit

DOUT0

DOUT1

PO

40

41

42

O

GCI Data Output 0

GCI Data Output 1

I (**)

P0 at VSS: variable access mode

P0 at VDD: fixed access mode

NRDY/N

WAIT

43

44

OD

I

If P0 at VSS:

Intel like mode: this pin delivers NRDY

Motorola mode: this pin delivers NWAIT

RES

Reset. A logical high on this input forces the STLC5460 into the reset state

(*): (I) Input

(O) Output

(IO) In/Output

(OD) Open Drain

(**): With Pull up resistance.

Figure 1:

GCI and PCM Interfaces.

PDC

CLOCKS

PFS

RxD0

DCL

FSC

PCM0

PCM1

PCM2

PCM3

TxD0

TSC0

DOUT0

DIN0

MUX0/GCI0

MUX1/GCI1

RxD1

TxD1

TSC1

DOUT1

DIN1

RxD2

TxD2

TSC2

RxD3

TxD3

TSC3

LCIC

MICROPROCESSOR INTERFACE

D94TL159A

4/54

STLC5460

LINE CARD APPLICATIONS

The LCIC is designed to fit both digital and ana-

logue line card architectures.

It supports up to 16 ISDN subscribers or 16 voice

subscribers. The level 1 devices are connected to

ST5451 circuits to perform the D channel han-

dling.

The clock frequency of PDC is equal to once or

twice the data rate, See fig 1 and 2. When operat-

ing at single rate (2048 kb/s) and not at double

clock frequency (4096 kHz), an onchip clock fre-

quency doubler provides a 4098 kHz clock for the

GCI interface (DCL).

The rising edge of PFS signal is used to deter-

mine the first bit of the first time slot of the frame.

The length of PFS pulse is one bit-time at least

and the length between two pulses can be also

one bit time.

After reset, the LCIC reaches synchronism having

received two consecutive correct PFS pulses.

Synchronisation is considered lost by the device if

the PFS signal is not repeated with the correct

repetition rate which has been stored by the cir-

cuit at the beginningof synchronisation research.

Analogue Line Card

In analogue line cards LCIC controls signalling,

voice and data path of 64 kb/s channels.

When used in combination with L3040/L3000N, it

allows to implement an optimised line card archi-

tecture:

the LCIC controls the configuration of L3040 and

exchange signalling with the L3040.

The LSYNC bit in the Interrupt Register indicates

if the component is synchronised or not: a logical

0 indicates the synchronous state, a logical ”1”

shows that the synchronism has been lost.

The relation between the framing signal PFS and

the bit stream is controlled by the contents of

IPOF, OPOF and CPOF registers. These regis-

ters denote the number of bit times the PCM

frame is shifted. Each PCM multiplex can be pro-

grammed with different shifts .

Digital Line Card

In digital line cards LCIC controls the configura-

tion of Level 1 circuits (U or S Interface) by

means of MON channel configuration and per-

forms activation/deactivation by means of Com-

mand/Indicate protocol. LCIC switches the B

channels and can switch the D channels if the

processing is centralised.

Without programming the bit shift function of the

PCM interface, the rising edge of the PFS signal

marks the first bit of input PCM frame and the

first bit of output PCM frame. See Fig 3

FUNCTIONAL DESCRIPTION

PCM INTERFACE

The PCM Interface Registers configure the data

transmitted or received at the PCM port, for one

PCM, the maximum data rate can change de-

pending on the Mode selected:

PCM Mode 0: max rate 2048kb/s with four PCM

ports active

PCM Mode 1: max rate 4096 kb/s with two PCM

ports active

PCM Mode 2: max rate 8192 kb/s with one PCM

ports active.

GCI Interface

The Monitor and the Command/Indicatechannels

may be validated or not, in this second case the

B3 and B4 channels become standard channels

at 64 kb/s.

When validated Command/Indicate channel may

be configured with four bits for digital cards or six

bits for analogue cards.

The clocks (Bit clock and frame clock) are deliv-

ered by the device with double rate clocking or

simple rate clocking.

The ”actual data” rate may be varied in a wide

range without programming.

An automate computes the number of clock per

frame. Hence, the data rate can be stepped in 8,

16 or 32 kb/s in increments in PCM mode 0, 1, 2

respectively.

FSC and DCL are output signals derived from

PFS and PDC which are input signals.

GCI

PCM

DCL clock kHz

PDC Clock (kHz)

Data kb/s

Data rate kb/s

Mode

Simple (*)

2.048

Double

4.096

Simple

Double

2.048

4.096

8.192

Mode 0

Mode 1

Mode 2

2.048

4.096

2.048

4.096

8.192

2.048

8.192

2.048

16.384

(*) as GCI format but with simple clock.

5/54

STLC5460

Figure 1: PCM Interface. Alignment in double clock mode.

Clocks received by the circuit

Mode not delayed:

PFS

PDC

DCL=1

DEL=0

PFSP=0

First bit of the frame

PFS

PDC

DCL=1

DEL=0

PFSP=1

First bit of the frame

Mode delayed:

PFS

PDC

DCL=1

DEL=1

PFSP=0

First bit of the frame

PFS

PDC

DCL=1

DEL=1

PFSP=1

First bit of the frame

6/54

STLC5460

Figure 2: PCM Interface. Alignment in simple clock mode.

Clocks received by the circuit

PFS

PDC

DCL=0

DEL=0

First bit of the frame

PFSP=0

PFS

PDC

DCL=1

DEL=0

PFSP=1

Mode not delayed

First bit of the frame

PFS

DCL=1

DEL=1

PDC

PFS

PFSP=0

DCL=1

DEL=1

PDC

PFSP=1

Mode delayed

7/54

STLC5460

Figure 3: PCM Interface. Clock and Data in/Data out.

PDC

ODL=0

DOUT

GCI like

ODL=1

ISPP=0 DIN

ISPP=1

DIN

GCI like

Double clock DCP =1

PDC

ODL=0

DOUT

DIN

ODL=1

Simple clock DCP=0

8/54

STLC5460

control memory corrisponding to the address indi-

cated by the destination register;

command register:

it contains the code (6 bits to be written or read)

of the control memory.

The content of command register defines the dif-

ferent capabilities: switching at 64 kb/s, 32 kb/s,

16 kb/s, loopback and also extraction/insertion

from the microprocessor interface.

MEMORY STRUCTURE AND SWITCHING

The LCIC contains three memories: Auxiliary

Memory (AM), Data Memory (DM) and Control

Memory (CM).

The Auxiliary Memory consists of one block di-

vided in four parts of 16 words.

This Auxiliary Memory is used for validated data

from Monitor and Command/IndicateRx channels

and to transmit data to Monitor and Com-

mand/IndicateTx channels.

The Data Memory buffers the data input from the

PCM and the GCI interface. It has a capacity of

128 + 64 time slots to buffer 4 PCM frame of 32

time slots and two GCI interfaces. It is written pe-

riodically once every 125 microseconds controlled

by the input counters associated to PCM interface

and to GCI interface. To perform the switching the

loopback function, this memory is read, random,

in accordancewith the control memory

A memory access using the actual command reg-

ister and source register is performed upon every

destination register write access. The processing

of the memory access takes at most 488ns.

MICROPROCESSOR INTERFACE

After Reset, the Microprocessor interface is in

non-multiplexed mode (Address bus and Data

bus must be non-multiplexed):

if ALE pin is hardwired at VSS, the Microproces-

sor interface is Motorola like, Address/Data are

non-multiplexed.

if ALE pin is hardwired at VDD the Microproces-

sor interface is Intel like, Address/Data are non-

multiplexed.

The Control Memory has a capacity of 128 + 64

words of 14 bits: 8 of data and 6 of code. The 14

bits are written random, via microprocessor in-

terface and read cyclically under the control of

the output counters associated to PCM interface

and GCI interface.

For control memory access and different func-

tions, three registers are provided:

After Reset, as soon as two successive edges are

detected on ALE pin (Rising and falling edges) by

the circuit the Microprocessor interface switches

in multiplexed mode (Address bus and Data bus

must be multiplexed). The circuit is set automat-

ically in Motorola like or in Intel like mode.

For the circuit Address bus and Data bus multi-

plexed or not multiplexed, the difference between

Motorola like and Intel like mode is showedin fig. 4.

destination register:

it contains the address of a specific location of

the control memory;

source register :

it contains the data (to be written or read) of the

Figure 4.

9/54

STLC5460

The microprocessor interface type is set via P0

pin as shown hereafter :

When a new primitive has been received twice

identical, on one of the 16 C/I channels, an inter-

rupt is generated,the number of the C/I channel

(4 bits) is written in the Receive C/I status regis-

ter , and the primitive received is in the Auxiliary

Memory, all accessible to the µp

Moreover, the microprocessor can read directly

the 16 primitives that have been received and

stored into the Receive C/I Memory. To read this

memory the µp load in the Source Register the

number of Receive C/I channel it wants, and in

the destinationregister reads the primitive (4 or 6

bits) with a seventh bit which indicates whether

the primitive has been received once or twice

identical. vedi figura read aux mem Receive C/I

channels.

P1 is an outputandit is not used if P0 = 1.

The device selects automatically either Motorola

interface or Intel Interface.

P0

P1

Automatical selection

Intel MUX mode

1

Z

Motorola MUX mode

Intel DEMUX mode

Motorola DEMUX mode

0

If A0 = 1 P1 pin delivers WAIT automatically

If A0 = 0 P1 pin delivers READY automatically

Moreover, for a multiplexed mode µP interface,

A1 to A3 pinsmean :

Monitor Channel Protocol

Sixteen Monitor channels are implemented. To

transmit a message the µp load into destination

register with W/R bit of Command Register at 1

the number of MON channels, and into source

register the message; this byte is transmitted if

BYTE Bit of CommandRegister is at 1.

A1 = 1: CS signal provided by the system is not

inverted by the device

A1 = 0: CS signal provided by the system is in-

verted by the device

A2 = 1: AS signal provided by the system is not

inverted by the device

A2 = 0: AS signal provided by the system is in-

verted by the device

A3 = 1: DS signal provided by the system is not

inverted by the device

A3 = 0: DS signal provided by the system is in-

verted by the device.

This procedure is repeated for each byte of the

message if it is longer than one byte.

When a new byte has been received twice identi-

cal from one of the sixteen Monitor channels

an interrupt is generated, the number of MON

channel (4 bits) is written in Receive Monitor

Status Register and the last byte received is writ-

ten in Receive data Monitor Channel Memory.

The remote transmitter will transmit the next byte

after reading of this register by the local micro-

processor.

C/I AND MON CHANNELS, EXTRA CHANNELS

The Command/indicate and Monitor channelscan

be validatedor not:

if validated, the C/I and MON protocol controllers

operate and it is not possible to use this channels

for switching, if not validated the protocols are in-

hibited and the channels can be used as ex-

trachannels for switching.

INSERTION - EXTRACTION

This function allows to insert data into GCI and

PCM channels and to extract data from GCI and

PCM interface. These data are provided either by

the microprocessor or by an internal Pseudo Ran-

dom SequenceGenerator.

Command/Indicate Protocol

Sixteen C/I channelsare implemented, one bit of

the configuration register MCONF1, indicates the

number of bits of the primitive (four or six bits) for

all the channels.

To transmit a primitive into one of the 16 chan-

nels, the mp loads the primitive (4 or 6 bits) into

source register and the number of the C/I chan-

nel into destination register with W/R bit of com-

mand register at ”0”.

The two more significant bits of the source regis-

ter indicates if the primitive, bit0/5 of the same

register, has not been transmitted yet, transmitted

once, twice or more .

Insertion

Two programmable registers (Insert A and B)

contain the data to insert into two output time

slots continuously. To perform an insertion, four

registers are programmed by the microprocessor:

- in the Insert A and/or B Registers it writes the

data to insert.

- in the Source registers it writes the A and/or B

register address

- in the Destination Register it writes the output

interface, PCM or GCI, and the Time Slot se-

lected.

10/54

STLC5460

are processed by the microprocessor :

- in the Command Register it writes the indica-

tion if insert into 64 kb/s, 32 kb/s or 16 kb/s

channel.

When the data has been inserted, status bit

(INS) of status register is put at logical 1 and an

interrupt is generated.

- Extract A and/or B Registers to read the data

extracted.

- The Sourceregister to indicate the input inter-

face, PCM or GCI, and the Time Slot se-

lected.

When the data is loaded in Extract A or Ex-

tract B Register, the bit EXT of STATUS reg-

ister is put at logical 1,and an interrupt is gen-

erated.

Extraction

Two programmable registers (Extract A and B)

contain the data extracted from two input time

slots. To perform an extraction, three registers

LIST OF REGISTER

Read

Name

MUX Mode

DEMUX Mode

Only

AD5 to AD1

00000

(H)

RBS

X

A3 to A0

0000

RBS

X

IIR

(00)

0

COMP

MCONF1

MCONF2

PCONF

CPOF

IPOF

OPOF

IPSH1

IPSH2

OPSH1

OPSH2

IPASS

OPASS

IMASS

OMASS

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

(01)

(02)

(03)

(04)

(05)

(06)

(07)

(08)

(09)

(0A)

(0B)

(0C)

(0D)

(0E)

(0F)

X

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

1

STATUS

ECR

CMR

SRC

DST

INSA

INSB

EXTA

EXTB

INT

MASK

RMOS

TMOS

RCIS

TEST

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

(11)

(12)

(13)

(14)

(15)

(16)

(17)

(18)

(19)

(1A)

(1B)

(1C)

(1D)

(1E)

(1F)

X

R

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

R

NB in Mux Mode AD7, AD6, AD0 and RDS bits are ignored

11/54

STLC5460

CONFIGURATION REGISTER DESCRIPTION

Initialisationand Identification Register (IIR)

7

0

RBS

RST

T1

T0

V3

V2

V1

V0

After Reset 3F (H)

T1/T0 Test functions

T1

0

T0

0

Description

Normal State

0

1

Command Memory or Auxiliary Auto Reset.

If CM = 1 (Bit of Command Register):

the six lower bits of command Register and the eight bits of Source Register are stored

into each address of command Memory.

If CM = 0 (Bit of Command Register) :

the eight bits of Source Register are stored into each address of Monitor Auxililary

Memory and the six lower bits of Source Register are stored intoCommand/Indicate

Auxilliary Memory.

The 16 C/I and Monitor channels are ready to transmit and to receive data.After

AutoReset, BUSY and T0 goes to ”0”.

1

Auto Test. This function is reserved for manufacturer.

- The Pseudo Random Sequence generator is connected instead of Insert A Register and

Pseudo Random Sequence Analyzer is connected instead of Extract A Register.

- The Command Memory is loaded thanks to a special algorithm in order to switch the

sequence provided by the generator into TSO of PCMO, then the contents of TSO of

PCMO into TS1 of PCMO, then the contents of TS1 of PCMO into TS2 of PCMO and

so on.

Finally, the contents of TS31 of MUX1 are taken into account by the Pseudo Random

Sequence Analyzer.After loading Command Memory, 193 switching are set up in real

time.The analyzer receives the Pseudo Random Sequence from the generator after

switching.

If LP = 1, the loopback is internal.

If LP = 0, an external loopback must be performed. So, Command Memory and Data

Memory can be checked in the same time.

1

Reserved. Initialise CM so that the content of each input Time Slot t of input multiplex m is

switched to output Time Slot t of output multiplex m

RBS

RST

Register Bank Selection.

RBS = 0. The 16 first main registers are selected (0 to 15).

Reset Soft.

the programmableregisters are reset.

V3/V0

these bits are fixed at 0

COMPARISON REGISTER (COMP)

7

0

NEWE

TIM

CP6

CP5

CP4

CP3

CP2

CP1

After Reset 00 (H)

NEWE

TIM

New EXTRACT.

When NEWE = 1, EXT interrupt is generated only if a new word is loaded into

EXTRACT Registers(A or B).

Timer, associated to INS of INT Register and to TIMO/1 of CPOFregister.

TIM = 1 TIM0/1 bits of CPOF register are taken into account

TIM = 0 an interrupt is generatedeach 125 µs.

12/54

STLC5460

CP 6/1

Comparison 6 to 1.

Bit stream of one PCM and bit stream of another PCM are compared at each bit time, if

there is difference, PDIF interrupt is generated.

Comparison between

CP1 = 1

CP2 = 1

CP3 = 1

CP4 = 1

CP5 = 1

CP6 = 1

PCM0 and PCM1

PCM1 and PCM2

PCM2 and PCM3

PCM0 and PCM2

PCM1 and PCM3

PCM0 and PCM3

MULTIPLEX CONFIGURATION 1 REGISTER (MCONF1)

7

0

CIM

MOM

CI4MI

CI4M0

-

GCIM1

GCIM0

After Reset 3F (H)

CIM

Command/IndicateMode.

CIM = 1: the controller ignores the new received primitive if the previous has not been

read by the microprocessor.

CIM = 0: the controller overwrites the previous primitive without condition when it

receives a new primitive.

MOM

Monitor channel Mode

MOM = 1: if bytes are not received twice identical the message is aborted.

MOM = 0: if bytes are not received twice identical the MOM controller doesn’t

acknowledge the received byte (GCI standard).

CI4M1

CI4M0

GCIM1

GCIM0

Command Indicate 4 bits for Multiplex 1.

CI4M1 = 0: commandIndicate primitive has six bits.

CI4M1 = 1: commandIndicate primitive has four bits.

Command Indicate 4 bits for Multiplex 0.

CI4M0 = 0: commandIndicate primitive has six bits.

CI4M0 = 1: commandindicate primitive has four bits.

GCI Multiplex 1.

GCIM1 = 1: the multiplex M1 is GCI, it includes eight GCI channels.

GCIM1 = 0: the multiplex M1 includes 32 TimeSlots. (PCM like channel)

GCI Multiplex 0.

GCIM0 = 1: the Multiplex M0 is GCI, it includes eight GCI channels.

GCIM0 = 0: the multiplex M0 includes 32 TimeSlots. (PCM like channel)

MULTIPLEX CONFIGURATION 2 REGISTER(MCONF2)

7

0

-

M1D

M0D

ISPM

TIMD

MOD

DCKM

After Reset FF (H)

M1D

Multiplex 1 Disable.

M1D = 1. Multiplex 1 output is at high impedance continuously,

multiplex 1 input is forced to ”1”, if it is GCI.

13/54

STLC5460

M0D

Multiplex 0 Disable.

M0D = 1. Multiplex 0 output is at high impedance continuously,

multiplex 0 input is forced to ”1”, if it is GCI.

TIMD

ISPM

Timer Monitor Channel Disabled.

TIMD = 1. The timer1ms is disabledfor each Transmit Monitor Channel.

Input Sampling Multiplex.

ISPM = 0. The input bit is sampled at half bit time.

ISPM = 1. The input bit is sampled at 3/4 bit time.

MOD

Multiplex Open Drain.

MOD = 1. The two multiplex outputs are open drain.

MOD = 0. The two multiplex outputs are at low impedance

DCKM

Double clock for Multiplex.

DCKM = 1. DCL is twice data rate (Ex : if Data Rate = 2048 kb/s,DCL = 4096 kHz).

DCKM = 0. DCL is simple clock.

PCM CONFIGURATION REGISTER (PCONF)

7

0

TSNB

DEL

PFSP

ODL

ISPP

POD

SCKP

After Reset 00 (H)

TSNB

DEL

Time Slot numbering.

TSNB defines the order of TS on the PCM when the data rate is 4 Mb/s or 8 Mb/s

related to the order of TS on the PCM at 2 Mb/s (see table hereafter).

Delayed Mode for each PCM.

DEL = 1. A delay of one clock pulse is applied to the first bit of the frame of each PCM.

DEL = 0. PFS indicates the first bit of the frame for each PCM (if OFFSET and shift are

zero).

PFSP

ODL

PCM Frame SynchronisationSampling.

PFSP = 0. PFS signal is sampled on the fall edge of PDC signal.

PFSP = 1. PFS signal is sampled on the rise edge of PDC signal.

Output Delay.

ODL = 0. The bits are shifted out with zero delay.

ODL = 1. The bits are shifted out with a delay of one half bit time.

ISPP

POD

SCKP

Input Sampling PCM.

ISPP = 0. The input bit is sampled at half bit time.

ISPP = 1. The input bit is sampled at 3/4 bit time.

PCM Open Drain.

POD = 1. The PCM outputs are open drain

POD = 0. The PCM outputs are at low impedance.

Simple clock for PCM.

SCKP = 0. PDC signal is twice data rate. (Ex : if data rate = 2048 kb/s, PDC = 4096

kHz).

SCKP = 1. PDC is simple clock

14/54

STLC5460

TS and PCMn

at 4 Mb/s

TS0

TS1

TS2

TS3

TS30

TS31

TS32

TS62

TS63

with n = 0 or 2

TS at

TS0

TS1

TS15

TS16

TS31

2Mb/s

TSNB = 1

PCM at

2Mb/s

PCMn PCMn+1 PCMn PCMn+1 PCMn PCMn+1 PCMn

PCMn PCMn+1

TS at

TS0

TS1

TS2

TS3

TS30

TS31

TS0

TS30

TS31

2Mb/s

TSNB = 0

PCM at

2Mb/s

PCMn

PCMn+1

TS and PCM0

at 8 Mb/s

TS0

TS1

TS2

TS3

TS4

TS124

TS32

TS62

TS63

TS at

TS0

TS1

TS31

2Mb/s

TSNB = 1

PCM at

2Mb/s

PCM0

PCM1

TS0 to TS31

PCM0

PCM2

PCM3

PCM0

PCM1

PCM2

PCM3

TS and PCM

at 8Mb/s

TS32 to TS63

TS64 to TS95

TS96 to TS127

TS0 to TS31

PCM3

TS at

TS0 to TS31

PCM1

TS0 to TS31

PCM2

2Mb/s

TSNB = 0

PCM at

2Mb/s

COMPLEMENTARY PCM OFFSET REGISTER (CPOF)

7

0

PMD1

PMD0

TIM1

TIM0

OOF1

IOF0

IOF1

IOF0

After Reset 00 (H)

PMD1/0 PCM Mode

PMD1

PMD0

The PCM are at

2048 kbit/s

4096 kbit/s

8192 kbit/s

Not used.

0

1

0

1

0

1

TIM 1/0 these bits are taken into account only if bit TIM of COMP register is at 1; in this case an inter-

rupt is generatedperiodically and TIM 1/0 defines the period

TIM1

TIM0

Period

1ms

0

1

0

1

0

1

8ms

64ms

250ms

OOF1/0

IOF1/0

Output Offset 1/0.

These two bits are associated with OOF2/9 ofOPOF Register.

Input Offset 1/0.

These two bits are associated with IOF2/9 of IPOFRegister.

15/54

STLC5460

INPUT PCM OFFSET REGISTER (IPOF)

7

0

IOF9

IOF8

IOF7

IOF6

IOF5

IOF4

IOF3

IOF2

After Reset 00 (H)

IOF9/2

Input PCM Offset 9 to 2.

Associated with IOF1/0, these ten bits indicate the delay between PFS signal and the

first bit of the frame, for each input

OUTPUT PCM OFFSET REGISTER (OPOF)

7

0

OOF9

OOF8

OOF7

OOF6

IOF5

OOF4

OOF3

OOF2

After Reset 00 (H)

OOF9/2

Output PCM Offset 9 to 2.

Associated with OOF1/0 of complementary offset register, these ten bits indicate the

delay between bit 0 of the frame out going versus bit 0 of the frame incoming.

INPUT PCM SHIFT 1 (IPSH1)

7

0

P1SH2

P1SH1

P1SH0

0

P0SH2

P0SH1

P0SH0

After Reset 00 (H)

P1SH2/0

P0SH2/0

PCM1 Shift 2 to 0.

This number (0 to 7) is added to Input PCM offset to obtain the total shift of the frame of

PCM1.

PCM0 shift 2 to 0.

This number (0 to 7) is added to Input PCM offset to obtain the total shift of the frame of

PCM0.

INPUT PCM SHIFT 2 (IPSH2)

7

0

P3SH2

P3SH1

P3SH0

0

P2SH2

P2SH1

P2SH0

After Reset 00 (H)

P3SH2/0

P2SH2/0

PCM3 Shift 2 to 0.

This number (0 to 7) is added to Input PCM offset to obtain the total shift of the frame of

PCM3.

PCM2 Shift 2 to 0.

This number (0 to 7) is added to Input PCM offset to obtain the total shift of the frame of

PCM2.

OUTPUT PCM SHIFT 1 (OPSH1)

7

0

P1E

P1SH2

P1SH1

P1SH0

P0E

P0SH2

P0SH1

P0SH0

After Reset 00 (H)

P1E

Output PCM1 Enable.

P1E = 0. PCM1 output is at high impedance.

P1E = 1. PCM1 output is enable.

16/54

STLC5460

P1SH2/0

P0E

PCM1 shift 2/0.

This number (0 to 7) is addedto output PCM offset to obtain the total shift of the frame of

PCM1.

Output PCM2 Enable.

P0E = 0. PCM0 output is at high impedance.

P0E = 1. PCM0 output is enabled.

P0SH2/0

PCM0 Shift 2/0.

This number (0 to 7) is added to output PCM offset to obtain the total shiftof the frame of

PCM0.

OUTPUT PCM SHIFT 2 (OPSH2)

7

0

P3E

P3SH2

P3SH1

P3SH0

P2E

P2SH2

P2SH1

P2SH0

After Reset 00 (H)

P3E

Output PCM3 Enable.

P3E = 0. PMC3 output is at high impedance.

P3E = 1. PCM3 output is enabled.

P3SH2/0

P2E

PCM3 Shift 2/0.

This number (0 to 7) is added to output PCM offset to obtain the total shiftof the frame of

PCM3.

Output PCM2 Enable.

P2E = 0. PCM2 output is at high impedance.

P2E = 1. PCM2 output is enabled.

P2SH2/0

PCM2 shift 2/0.

Thisnumber(0to7)isaddedtooutputPCMoffsettoobtainthetotalshiftoftheframeofPCM2

INPUT PCM ASSIGNMENT REGISTER (IPASS)

7

0

IP31

IP30

IP21

1P20

1P11

1P10

1P01

1P00

After Reset E4 (H)

IP31/IP30 IncomingPCM3 Assignment.

IP31

IP30

Incoming PCM3 receives data from

0

1

0

1

0

1

Pin RxD0

Pin RxD1

Pin RxD2

Pin RxD3 (Default value)

IP21/IP20 IncomingPCM2 Assignment.

IP21

IP20

Incoming PCM2 receives data from

0

1

0

1

0

1

Pin RxD0

Pin RxD1

Pin RxD2 (Default value)

Pin RxD3

IP11/IP10 IncomingPCM1 Assignment.

IP11

IP10

Incoming PCM1 receives data from

0

1

0

1

0

1

Pin RxD0

Pin RxD1(Default value)

Pin RxD2

Pin RxD3

17/54

STLC5460

IP01/IP00 IncomingPCM0 Assignment.

IP01

IP00

Incoming PCM2 receives data from

0

1

0

1

0

1

Pin RxD0(Default value)

Pin RxD1

Pin RxD2

Pin RxD3

OUTPUT PIN ASSIGNMENT REGISTER (OPASS)

7

0

OP31

OP30

OP21

OP20

OP11

OP10

OP01

OP00

After Reset E4 (H)

OP31/OP30 OutputPin 3 Assignment.

OP31

OP30

Pin TxD3 receives data from

0

1

0

1

0

1

Outgoing PCM0

Outgoing PCM1

Outgoing PCM2

Outgoing PCM3 (Default Value)

OP21/OP20 OutputPin 2 Assignment.

OP31

OP30

Pin TxD2 receives data from

0

1

0

1

0

1

Outgoing PCM0

Outgoing PCM1

Outgoing PCM2 (Default Value)

Outgoing PCM3

OP11/OP10 OutputPin 1 Assignment.

OP11

OP10

Pin TxD1 receives data from

0

1

0

1

0

1

Outgoing PCM0

Outgoing PCM1 (Default Value)

Outgoing PCM2

Outgoing PCM3

OP01/OP00 OutputPin 0 Assignment.

OP01

OP00

Pin TxD0 receives data from

0

1

0

1

0

1

Outgoing PCM0 (Default Value)

Outgoing PCM1

Outgoing PCM2

Outgoing PCM3

INPUT MULTIPLEX ASSIGNMENT REGISTER (IMASS)

7

0

-

0

IM1

0

IM0

After Reset 04 (H)

IM1

IncomingMultiplex 1 Assignment.

IM1

Incoming Multiplex 1 receives data from

0

1

Pin DIN 0

Pin DIN 1 (Default Value)

18/54

STLC5460

IM0

IncomingMultiplex 0 Assignment.

IM0

Incoming Multiplex 0 receives data from

0

1

Pin DIN 0 (Default Value)

Pin DIN 1

OUTPUT MULTIPLEX ASSIGNMENT REGISTER (OMASS)

7

0

-

0

DO1

0

DO0

After Reset 04 (H)

DO1

DO0

Output 1 Pin Assignment.

DO1

0

1

DOUT 1 pin receives data from

Outgoing Multiplex 0

Outgoing Multiplex 1 (Default value)

Output 0 Pin Assignment.

DO1

0

1

DOUT 0 pin receives data from

Outgoing Multiplex 0 (Default value)

Outgoing Multiplex 1

WORKING REGISTER DESCRIPTION

Command Register (CMR)

7

0

R/W

CM

CR5

CR4

CR3

CR2

CR1

CR0

After Reset 00 (H)

R/W

Read/Write

R/W = 0. Write memory.

Address bits are provided by the Destination Register (DST)

Data bits are provided by the Source Register (SRC)

R/W = 1. Read Memory.

Address bits are provided by the Destination Register (DST)

Data bits will be in Source Register (SRC) when BUSY (Status Register) will go to ”0”.

CM

Command memory.

CM = 1 Access to Command Memory

CM = 0 Access to Auxiliary Memory.

CR 5/0

The meaning of these bits depends on the value of CM and R/W. The description is

given thereafter.

CM = 1

Command Memory

CM = 0

Auxiliary Memory

Command Register Bit 5 to 0

Source Register

Subchannelconfiguration

Command if Write Memory

Status if Read Memory

1 of 192 Input Time Slots or 1 of Byte if MON channel or Primitive

2 Insertion Registers if C/I channel.

DestinationRegister

1 of 192 OutputTime Slots or 1 1 of 16 MON channels

of 2 Extraction Registers or 1 of 16 C/I channels

Following you will find a detailed explanationcase by case of the meaning of all the bits of this register.

19/54

STLC5460

FIRST CASE CM = 1: ACCESS TO COMMAND MEMORY

CM

1

CR5

CH1

CR4

CH0

CR3

SS1

CR2

SS0

CR1

DS1

CR0

DS0

R/W

After Reset 00 (H)

R/W

Read/Write

R/W = 0 (Write). The eight bits of Source Register and the six lower bits of this

Command Register are loaded into the Command Memory (14 bits). The Address bits

are given by the Destination Register (8 bits). Write cycle starts when Destination

Register is loaded by the microprocessor.

R/W = 1 (Read).

The 14 bits of Command memory addressed by the Destination Register are loaded

respectively into Command Register (6 bits) and Source Register (8 bits). Read cycle

starts when Destination Register is loaded by the micro-processor.

CH0/1

Channel Data Rate

CH1

CH0

Description

The output is at high impedance during the time slot selected

16kb/s subchannel is selected

0

1

0

1

0

1

32kb/s subchannel is selected

64kb/s channel is selected

During the time slot selected, the output is at high impedance for the subchannelsnot selected.

SS 0/1

Source Subchannelselected.

Data Rate

16kb/s

SS1

SS0

0

Source channel

Bits 6-7

0

1

0

1

Bits 4-5

0

Bits 2-3

1

Bits 0-1

32kb/s

0

Bits 4 to 5

Bits 0 to 3

1

Bit 7 is trasmitted first.

DS 0/1

Destination Subchannelselected.

Data Rate

16kb/s

SS1

0

SS0

0

Source channel

Bits 6-7

0

1

Bits 4-5

1

0

Bits 2-3

1

Bits 0-1

32kb/s

0

Bits 4 to 5

Bits 0 to 3

0

1

Bit 7 is trasmitted first.

20/54

STLC5460

SECOND CASE CM = 0: ACCESS TO AUXILIARYMEMORY

Microprocessor writes Auxiliary Memory to transmit Primitives for each TX C/I channel and to transmit

Bytes of message for each TX MON channel.

Microprocessor reads Auxiliary memory to recover Primitive received by each RX C/I channel and to re-

cover the message received by each RX MON channel.

TX Command Indicate channel - Selected by Destination Register (DST)

CM

0

CR5

-

CR4

-

CR3

-

CR2

-

CR1

PT1

CR0

PT0

R/W

R/W = 1

Read auxiliarymemory

After writing this register with R/W=1 and when BUSY(status register) has gone to 0, the

bits of the register have the following meaning:

CR5/CR2

PT0/1

Not used

Primitive trasmitted

PT1

0

PT0

0

Status

Primitive has not been transmitted yet

0

1

0

1

Primitive has been transmitted once

Primitive has been transmitted twice

Primitive has been transmitted more than twice.

R/W = 0

Write auxiliary memory.

not used

CR0/CR5

RX Command Indicate channel - Selected by Destination Register (DST)

CM

0

CR5

-

CR4

-

CR3

-

CR2

-

CR1

OVR

CR0

PR

R/W

R/W = 1

Read auxiliarymemory

After writing this register with R/W=1 and when BUSY(status register) has gone to 0, the bits of the

register have the following meaning:

CR5/CR2

OVR

Not used

Overrun

OVR = 1. The previous primitive has not been read by the microprocessor.

PR

Primitive Received.

PR = 1. The primitive has been received once

PR = 0. The primitive has been received twice or more.

The primitive is in Source Register.

R/W = 0

Writing auxiliary memory.

not used

CR0/CR5

21/54

STLC5460

TX Monitor Channel selected by Destination Register.

R/W

0

CM

0

CR5

-

CR4

-

CR3

-

CR2

CR1

CR0

INIT

LAST

BYTE

IR/W = 0

CR5/CR3

LAST

Writing auxiliary memory.

not used

Last Byte.

This bit is associated with BYTE.

If LAST = 1, last byte of the message.

If LAST = 0, current byte

BYTE

INIT

Byte to transmit.

When this bit is at 1, the MON channel defined in SRC Register is initialised and the

Monitor Channel is idle (All ”1”s are transmitted)

R/W

1

CM

0

CR5

-

CR4

T0

CR3

ABT

CR2

CR1

CR0

LAST

BYTE

IDLE

R/W = 1

Read auxiliarymemory

After writing this register with R/W=1 and when BUSY(status register) has gone to 0, the bits of the

register have the following meaning:

TO

Time Out = one millisecond.

This bit goes to 1 when the remote receiver has not acknowledged the byte after 1

millisecond.

ABT

Abort.

ABT = 1 The remote receiver has aborted the message transmitting.

LAST

Last Byte.

This bit is associated with BYTE.

If LAST = 1, last byte of the message.

If LAST = 0, current byte.

BYTE

IDLE

BYTE = 1 Byte transmitting.

BYTE = 0 Byte transmitted and acknowledged by the Remote

Receiver, a new byte can be transmitted.

IDLE = 1 Monitorchannel, A bit, E bit are at ”1”.

RX Monitor channel- Selectedby Destination Register

CM

0

CR5

-

CR4

-

CR3

-

CR2

AB

CR1

CR0

R/W

BYTE

EOM

R/W = 1

Read auxiliarymemory

After writing this register with R/W=1 and when BUSY(status register) has gone to 0, the bits of the

register have the following meaning:

AB

Abort.

AB = 1 The receiver has detected an error during the transmission.

22/54

STLC5460

BYTE

EOM

New byte.

Byte = 1 A new byte is availablein the Source Register

End of Message

EOM = 1 : there is no significant byte in the Source Register. The previous byte which

had been received was the last.

R/W = 0

Write auxiliary memory.

Writing initiates the RX MonitorChannel.

CR0/CR5 not used

SOURCE REGISTER (SRC)

When the bit CM of command register is at one, this register contains the data to be written in the control

memory at the address indicated by the destination Register. It rappresents the address of the data

memory, or of one of the insert register, corresponding to the input data to be switched to the output indi-

cated by the destinationregister.

Following you will find a detailed explanationcase by case of the meaning of all the bits of this register.

First case CM = 1 (Bit of Command Register)

Command Memory is selected.

7

0

PCM

SR6

SR5

SR4

SR3

SR2

SR1

SR0

After Reset 00 (H)

PCM = 1

PCM = 0

The source is PCM Input.

The source is not PCM. The Source is either Multiplex Inputs (GCI) or Insert Registers.

PCM = 1

PCM

1

SR6

N1

SR5

N0

SR4

TS4

SR3

TS3

SR2

TS2

SR1

TS1

SR0

TS0

After Reset 00 (H)

If PCM is at 2 Mb/s

N0/1

PCM Number : 0 to 3

TS0/4

Time Slot Number : 0 to 31

If PCM is at 4 Mb/s

N1

PCM at 4 Mb/s : 0 or 1

TS0/4 and N0

Time slot Number : 0 to 63

N0 = TS5

If PCM is at 8 Mb/s

TS0/4 and N0/1

Time Slot Number : 0 to 127.

N0 = TS5, N1 = TS6.

PCM = 0

If N1 = 0

N0 = 0

The Source is Multiplex Input or Insertion Register.

Multiplexes are selected (GCI or not) then

Multiplex number : 0

23/54

STLC5460

N0 = 1

TS0/4

If N1 = 1

Multiplex number : 1

Time Slot Number : 0 to 31

Insertion Registers are selected.

N0 = 0 and TS0/4 = 0. A InsertionRegister 40 (H) is the source

N0 = 1 and TS0/4 = 1. B InsertionRegister 41(H) is the source .

Second case : CM = 0 (Bit of Command Register)

The auxiliary memory is selected.

If channel is Monitorchannel (see Destination Register), the contents of Source Register are data :

SR7

M8

SR6

M7

SR5

M6

SR4

M5

SR3

M4

SR2

M3

SR1

M2

SR0

M1

It is proposed to initialise at FF, before starting normal operation using initialisation register

T1 = 0 and T0 = 1.

M8 will be transmitted first.

If channel selected by DestinationRegister is Command/Indicate channels, the mean of bits of Source

Register are :

- For TX C/I with R/W = 0 Write auxiliary memory.

SR7

-

SR6

-

SR5

C6

SR4

C5

SR3

C4

SR2

C3

SR1

C2

SR0

C1

It is proposed to initialise at FF, before starting normal operation using initialisation register

T1 = 0 and T0 = 1.

C1/C6

Primitive to transmit : C6 and C5 bits are taken into account depending

on CI4M1 and CI4M0 bits of MCONF Register.C6 (or C4) will be

transmitted first.

- For TX C/I with R/W = 1 Read auxiliary memory.

SR7

PT1

SR6

PT0

SR5

C6

SR4

C5

SR3

C4

SR2

C3

SR1

C2

SR0

C1

PT 1/0

Status of Transmitting primitive.

PT1

0

PT0

Status

0

1

0

1

Primitive has not been transmitted yet

0

Primitive has been transmitted once

Primitive has been transmitted twice

1

Primitive has been transmitted more than twice.

C6 to C1

Primitive being transmitted.

For RX C/I with R/W = 0, write auxiliary memory. This Source Register is not taken into account.

For RX C/I with R/W = 1, read auxiliary memory.

SR7

SR6

PR

SR5

C6

SR4

C5

SR3

C4

SR2

C3

SR1

C2

SR0

C1

OVR

24/54

STLC5460

OVR

PR

Overrun.

When OVR = 1, the previous primitive had not been read by the microprocessor;

the current primitive has been put instead of the previous primitive. The previous primitive has

been lost.

Primitive Received.

PR = 1, the current primitive has been received identical twice or more.

C6 to C1 Primitive received.

DESTINATION REGISTER (DST)

First case CM = 1 (Bit of Command Register). Command Memory is selected.

7

0

PCM

DT6

DT5

DT4

DT3

DT2

DT1

DT0

After Reset 00 (H)

PCM = 1 The destination is PCM output

PCM = 0 The destination is not PCM. The destination is either Multiplex (GCI or not) or Extract

Registers.

PCM = 1

PCM

1

DT6

N1

DT5

N0

DT4

TS4

DT3

TS3

DT2

TS2

DT1

TS1

DT0

TS0

PCM = 1

The destinationis PCM output

If PCM are at 2 Mb/s:

N0/1

PCM number: 0 to 3

TS0/4

Time Slot number 0 to 31.

If PCM are at 4 Mb/s

N1

PCM at 4 Mb/s:0 or 1

TS0/4 and N0

Time Slot number 0 to 63

(N0 = TS5)

If PCM is at 8 Mb/s

TS0/4 and N0/1

Time Slot Number: 0 to 63

N0 = TS5, N1 = TS6.

PCM = 0

If N1 = 0

N0 = 0

The Destinationis Multiplex output or ExtraxtionRegisters.

Multiplexes are selected (GCI or not), then

Multiplex number: 0

N0 = 1

Multiplex number: 1

TS0/1

Time slot Number: 0 to 31

If N1 = 1

Extraction Registers are selected, then

A Extraction Register 40 (H) is the destination

B Extraction Register 41 (H) is the destination

N0 = 0 and TS0/4 = 0

N0 = 1 and TS0/4 = 1

25/54

STLC5460

Second Case CM = 0 (Bit of Command Register).

The auxiliary Memory is selected.

PCM

-

DT6

DT5

TX

DT4

-

DT3

M0

DT2

G2

DT1

G1

DT0

G0

MON

PCM Bit is not significant. The other bits are relevant only if multiplex is GCI (See bits of Multiplex Con-

figurationRegister : GCI M0 and/or GCI M1).

MON

Command/Indicate

MON = 0. The channel is Command/Indicate

MON = 1. Thechannel is MON channel.

TX

Transmitter

TX = 1. The transmit channel is selected.

TX = 0. The receive channel is selected.

M0

Multiplex 0.

M0 = 0. The GCI multiplex 0 is selected.

M0 = 1. The GCI multiplex 1 is selected.

G2/G0

GCI 0/2

One of eight GCI channelsof the multiplex selected (one GCI channel is

constituted by five sub-channels : B1, B2, D, C/I and MON).

If Multiplex is not GCI, the GCI channels are not validated. The 32 Time Slots of the multiplex can be

used for switching.

STATUS REGISTER (STATUS)

7

0

BID

BUSY

PRSR

MONR

MONT

CIR

EXT

INS

After Reset 00 (H)

Each bit of this register is read only, except BID (bit) which can be written and read by the microproces-

sor.

BID

Bi-directional Switching.

BID = 1. two connection paths are established with the same µp instruction.

The µp writes successively into three register: Command Register, Source Register

and the Destination register lastly, when the Destination register has been written a

write command memory starts to set up the connectionrequired by the µp.

The same information is used to establish a symmetrical connection:

Source register and Destination register are swapped, and so are the SS0/1and

DS0/1 bit of Command Register.

BID = 0: one connection path is established.

The µp writes successively into three register: Command register, Source register

and Destination register lastly, when the Destination register has been written a write

command memory start to set up the connectionrequired by the µp.

26/54

STLC5460

BUSY

Busy.

The memories cannot be accessedif thisbit is at ”1”. In this case, a new access of

three memory access registers [Command Register (CMD); source Register (SRC)

and Destination Register (DST)] will be ignored. If the microprocessor has Twait

cycles (working with DTACK or READY), the test BUSY is not necessary.

PRSR

MONR

MONT

Pseudo Random Sequence Recovered.

When the PRS analyser is validated,PRS bit is put to ”one” if the synchronization is

performed.

Monitor Channel Receive.

When this bit is at ”1”, a byte has been received from one or more Monitor channel.

The microprocessor must read the Receive Monitor Status Register (RMS)

Monitor Channel Transmit.

When this bit is at ”1”, one (or more) channel is transmitting a message and is

ready to transmit a new byte of this message.The microprocessor must read the

Transmit Monitor Status Register (TMS).

When this bit is at ”0”, each channel is IDLE, and is ready to transmit a new message.

CIR

EXT

INS

Command/IndicateReceive.

When this bit is at ”1”, a new primitive has been received from one or more

Command/Indicatechannel. The microprocessor can read the Receive

Command/IndicateStatus Register (RCIS).

Extract Status.

This bit is put ot ”1” when a new byte has been written in the extract registers A or/

and B, when it is at ”1” the Extract Registers can be read during 120 microseconds

before changing. The bit is reset after the reading of the STATUS Register.

Insert Status.

When this bit is at ”0”, the Insert Register A or/and B can be written during 120 µs

before the next transmission. After the Insert Registers have been written the bit goes

automatically to ”1”, the bit is put at ”0” after the reading of the status register.

INSERTION A REGISTER (INS A)

7

0

IA7

IA6

IA5

IA4

IA3

IA2

IA1

IA0

After Reset 00 (H)

IA 0/7

This register contains the data to insert during the Time Slot (s) of the output

multiplex(es) indicated by the Command Memory. After transferring INS, interrupt is

generated

INSERTION B REGISTER (INS B)

7

0

IB7

IB6

IB5

IB4

IB3

IB2

IB1

IB0

After Reset 00 (H)

IB 0/7

This register contains the data to insert during the Time Slot(s) of the output

multiplex(es) indicated by the Command Memory. After transferring, INS interrupt is

generated.

27/54

STLC5460

EXTRACTION A REGISTER(EXT A)

7

0

EA7

EA6

EA5

EA4

EA3

EA2

EA1

EA0

After Reset 00 (H)

EA 0/7

This register contains the data extracted during the Time Slot of Input multiplex

indicated by the Command Memory. After loading, EXT interrupt is generated,in

accordance with NEWE bit of Comparison Register

EXTRACTION B REGISTER(EXT B)

7

0

EB7

EB6

EB5

EB4

EB3

EB2

EB1

EB0

After Reset 00 (H)

EB 0/7

This register contains the data extracted during the Time Slot of Input multiplex

indicated by the Command Memory. After loading, EXT interrupt is generatedin

accordance with NEWE bit of ComparisonRegister.

INTERRUPT REGISTER (INT)

7

0

LSYNC

PDIF

PRS

MONR

MONT

CIR

EXT

INS

After Reset 00 (H)

LSYNC

Lost synchronisation.

LSYNC = 0, PFS signal frequencyis correct.

LSYN = 1. PFS signal has not occurredwhen expected,

or if Double clock the number of clock pulses received is odd,

or the data rate of one PCM received is not Modulo 4 bits at 8 Mb/s,

or the data rate of one PCM received is not Modulo 2 bits at 4 Mb/s.

PDIF

PRS

MONR

MONT

CIR

PCM different.

PDIF = 1. If one (or more) comparison (validated by the Comparison Register)

between PCM is different.

Pseudo Random Sequence .

When the PRS analyser is validated (SAV =1), PRS bit is put to ”one” if the

synchronisation is performedor lost (see PRSR bit of Status Register).

Monitor Channel Receive.

When this bit is at ”1”, a byte has been received from the Monitor Channel defined by

Receive Monitor Status Register (or an event)

Monitor Channel Transmit.

When this bit is at ”1”, the MonitorChannel (defined by Transmit Monitor Status

Register) acknowledges the last command required by the microprocessor.

Command IndicateReceive.

When this bit is at ”1”, a new primitive has been received from the Command/Indicate

channel defined by the Receive Command/IndicateStatus Register

EXT

Extract

When this bit goes to ”1”, the Extract RegisterA or/and B can be read during 120

microseconds before changing.

INS

Insert

When this bit goes to ”1”, the content of Insert Register A or/and B has been

transmitted. During 120 microseconds before the next transmission, the

microprocessor can write a new word in accordancewith TIM (Bit of CR Register).

28/54

STLC5460

MASK REGISTER (MASK)

7

0

MLSYNC MPDIF

MPRS

MMONR MMONT

After Reset FF (H)

MCIR

MEXT

MINS

Each interrupt of Interrupt Register can be masked by the mask bit associated if this last is at ”1”.

RECEIVE MONITOR STATUS REGISTER (RMOS)

7

0

EVENT

BYTE

EOM

AB

MO

G2

G1

G0

After Reset 00 (H)

After Reading, Event bit goes to ”0”.

EVENT.

EVENT

EVENT = 1. An event is occurred concerningthe RX Monitor Channel identifiedby

M0, G2, G1, G0.

EVENT = 0. No event occurred concerningthe RX MonitorChannels.

BYTE

EOM

A new byte is available in Auxiliary Memory. The microprocessor can read this byte

End of message.

The previous byte which has been taken into account by the microprocessor was the

last of the message.

AB

ABORT.

ABORT = 1. The message received has been aborted by the transmitter.

M0

GCI Multiplex 0 if MO = 0

GCI Multiplex 1 if MO = 1.

G 0/2

GCI channel 0 to 7 for each multiplex.

TRANSMIT MONITOR STATUS REGISTER (TMOS)

7

0

EVENT

BACK

TO

ABT

MO

G2

G1

G0

After Reset 00 (H)

EVENT

BACK

TO

EVENT = 1.

An event is occurred concerning the TX Monitor Channel identified by

MO, G2, G1, G0.

EVENT = 0.

No event concerningthe TX Monitor Channels.

Byte acknowledged.

BACK = 1. The current byte transmittedhas been acknowledged by the remote

receiver.

NB : when EVENT = 1 and TO = 0 and ABT = 0 and BACK = 0, it means end of

message. A newmessage can be transmitted.

Time Out.

The remote receiver has not acknowledgedthe byte transmitted during 1millisecond

(the Timer is validated in accordancewith TIMD of MultiplexConfiguration2 Register).

ABT

MO

ABORT.

The byte transmitting has been aborted.

GCI Multiplex 0 if MO = 0

GCI Multiplex 1 if MO = 1.

G 0/2

GCI channel 0 to 7 for each multiplex.

29/54

STLC5460

RECEIVE COMMAND/INDICATE STATUS REGISTER (RCIS)

7

0

EVENT

RRP

OVR

0

MO

G2

G1

G0

After Reset 00 (H)

EVENT

RRP

EVENT = 1.

A primitive has been received twice identically. The number of Command/Indicate

channelsis give by MO, G2, G1, G0.

Read Receive Primitive

RRP = 1 the mp has to read the primitive receivedin orderto allow the next on to be

processed.

OVR

MO

OVERRUN

OVR = 1. The previous primitive has not been read by the microprocessor.

If MO = 0, Multiplex 0

if MO = 1, Multiplex 1.

G 0/2

GCI 0 to GCI 7 channel of each multiplex.

TEST REGISTER (TEST)

7

0

FWD

WITG

DCA

SAV

LP

PRSC

DCG

SGV

After Reset 00 (H)

FWD

False Word Detection

FWD = 1, the counter indicates the number of wrong bytes

FWD = 0, the counter indicates the number of wrong bits.

WITG

Word integrity.

WITG = 1. The first bit of the Pseudo Random Sequence(2*11-1) is the firstbit of the

channel (or subchannel)selected in the Time Slot at the beginning of the transmission.

WITG = 0. The first bit of the PRS is transmittedwithout taking into accountthe place

in the Time Slot.

‘

DCA

Double channel for analyser.

DCA = 1. The analyser receives Pseudo Random Sequence from two channels.

DCA = 0. The analyser receives Pseudo Random Sequence from one channel.

SAV

SequenceAnalyser Validation. When this bit goes to ”1”, the Analyser of Pseudo

Random Sequence (2*11-1) is connectedinstead of Extract A Register i f DCA = 0,

instead of Extract A and Extract B registers if DCA = 1. Then the synchronisation is

researched.

When SAV = 0, the analyser is initiated.

NB : When DCA= 0, Insert B register can be used normally.

LP

Loopback.

When LP = 1, the six data streams going out (PCM 0/3 and MUX 0/1) are respectively

connectedinstead of data stream coming from the 6 inputs (PCM 0/3 and MUX 0/1).

The loopbackis transparentor not, dependingon M0D,M1D, P0E, P1E, P2E, P3E

bits of Multiplex and PCM ConfigurationRegisters.

PRSC

Pseudo Random Sequence Corrupted.

When this bit changes from 0 to 1, one PRS bit is corrupted if DCG = 0, two PRS bits

are corrupted if DCG = 1 (one bit in each channel). After transmitting corrupted bit(s),

PRSC changesfrom ”1” to” 0”.

DCG

SGV

Double channel for Generator.

DCG = 1. The generatortransmits Pseudo Random Sequence to two channels.

DCG = 0. The generatortransmits Pseudo Random Sequence to one channel.

SequenceGenerator Validation.

When this bit goes to ”1”, the generator provides Pseudo Random Binary Sequence

2 * 11-1 in accordancewith CCITT RecommendationO.152. The generatoris

30/54

STLC5460

connectedinstead of Insert A Register if DCG = 0, and instead of Insert A and

Insert B Registers if DCG = 1.

When SGV goes to ”1”, the current contents of Command Register (CMD) is taken

into account by the generator.In this case, Command Register means :

7

0

BCH1

BCH0

0

ACH1

ACH0

BCH1/0

Insert B channel 1/0.

If generatortransmits sequence instead of Insert B register, the data

rate for this channel is given by BCH1/0

BCH1

BCH0

0

1

0

1

0

1

8 kb/s

16 kb/s

32 kb/s

64 kb/s

ACH1/0

Insert A channel 1/0

If generatortransmits sequence instead of insert A Register, the data rate for this

channel is given by ACH1/0.

ACH1

ACH0

0

1

0

1

0

1

8 kb/s

16 kb/s

32 kb/s

64 kb/s

If DCG = 1, the data rate of PRS generator is the sum of data rate Insert B

channel and Insert A channel.

If DCG = 0, the data rate of PRS generator is equal to data rate of Insert A channel.

ERROR COUNTER REGISTER (ECR)

7

0

EC7

EC6

EC5

EC4

EC3

EC2

EC1

EC0

After RESET 00 (H).

If the Pseudo Random Sequence Analyser is validated (SAV = 1), this register indicates the number of

errored bits received after the synchronisation of the Pseudo Random Sequence. When Error Counter

Register indicates all ”1”s, the synchronisation is lost. After reading by the microprocessor, ECR is put to

”0”.

31/54

STLC5460

MICROPROCESSOR INTERFACE TIMING

tx

t1

Parameter

Set up time Not Chip Select / DS/NRD

Set up time R/W / NWR / DS/NRD

Hold time Not Chip Select / DS/NRD

Hold time R/W / NWR / DS/NRD

Width AS/ALE

T min

10

0

T max

Unit

ns

t2

t3

t4

0

t5

20

10

t6

Set up time Address/ AS/ALE

Hold time Address / AS/ALE

Data valid after DS/NRD (rising edge) (30 pF)

Hold time Data after DS/NRD (falling edge)

Hold time Data / DS/NRD

t7

t8

40

t9

0

t10

t11

t12

t13

t14

t15

10

30

0

Set up time Data / DS/NRD

Width DS/NRD

NRDY/NWAIT delay DS/NRD

NRDY/NWAIT delay / Data

NRDY/NWAIT delay / DS/NRD

NRDY/NWAIT delay / R/W / NWR

30

32/54

STLC5460

MICROPROCESSOR INTERFACE TIMING

Multiplexed Address/DataMicroprocessorinterface

33/54

STLC5460

MICROPROCESSOR INTERFACE TIMING

Non-multiplexed Address/DataMicroprocessor interface

34/54

STLC5460

MICROPROCESSOR INTERFACE TIMING

VariableCycle Microprocessorinterface

35/54

STLC5460

CLOCK TIMING

Synchronization signals delivered by the system

t2

t5h t5l

t1

PDC

3

4

5

6

7

0

1

t3

t4

PFS

TXD0/3

TS0/3

Bit7

Bit1

Bit3

Bit5

Bit0

Bit4

Bit6

t6

t7 t8

RXD0/3

TDM0/3

Time Slot 31

Time Slot 0

FSC delivered

by the circuit

DEL, ISPP and PFSP bits of PCM Configuration Register are at zero (no delay))

Clocks received by the LCIC

tx

Parameter

Clock Period if f1 = 16384KHz

Clock Period if f1 = 8192KHz

Clock Period if f1 = 4096KHz

T min.

T typ.

T max.

Unit

t1=1/f1

60

120

239

61

122

244

62

124

249

ns

t2

Bit-time if f1 = 16384KHz

Bit-time if f1 = 8192KHz

Bit-time if f1 = 4096KHz

122

244

488

ns

t3

t4

t5

t6

Set up time PFS/PDC

Hold time PFS/PDC

Clock ratio t5h/t5l

20

75

t1-20

12500-t1

125

ns

%

100

PDC to data 50pF

PDC to data 100pF

50

100

ns

t7

t8

Set up time data/DCL

Hold time data/DCL

20

ns

36/54

STLC5460

CLOCK TIMING

TDM synchronization

PDC received by

the LCIC

t1

t2

DCL delivered by

the LCIC

t3

t4

FSC delivered by

the LCIC

t5

t6

Bit0, Time Slot 0

Bit7, Time Slot 31

DOUT 0/1

DIN 0/1

t7 t8

The four Multiplex Configuration Registers are at zero (no delay between FSC and Multiplexes)

Clocks deliveredby the LCIC

tx

Parameter

T min.

T typ.

T max.

Unit

t1

Clock Period if 4096KHz

Clock Period if 2048KHz

Id PDC

244

488

Id PDC

ns

t2

t3

t4

t5

t6

Delay between PDC and DCL (30pF)

Delay between DCL and rising edge FSC (30pF)

Delay between DCL and falling edge FSC (30pF)

Duration FSC

5

30

ns

488

DCL to data 50pF

DCL to data 100pF

50

100

ns

t7

t8

Set up time data/DCL

Hold time data/DCL

20

ns

37/54

STLC5460

DC SPECIFICATION

Absolute Maximum Ratings

Symbol

Parameter

Value

-0.5 to 6.5

-0.5, VDD +0.5

-55, +125

Unit

V

V_DD

5V Power Supply Voltage

Input or Output Voltage

Storage Temperature

V

T_stg

°C

Power Dissipation

Symbol

Parameter

Power Consumption

Test Condition

Min.

Typ.

Max.

Unit

P

V_DD= 5.25V

105

135

mW

RecommendedDC OperatingConditions

Symbol

V_DD

Parameter

5V Power Supply Voltage

Operating Temperature

Min.

4.75

-40

Typ.

Max.

5.25

+85

Unit

mW

°C

T_oper

Note 1: All the following specifications are valid only within these recommended operating conditions.

TTL Input DC Electrical Characteristics

Symbol

V_IL

Parameter

Low Level Input Voltage

High Level Input Voltage

Low Level Input Current

High Lvel Input

Test Condition

Min.

Typ.

Max.

Unit

V

0.8

V_IH

2.0

V

I_IL

V_I= 0V

V_i= V_{DD Max}

1

-1

-50

4

A

µ

I_IH

I_{IH_PULLUP}High level input current for pullup Vi = V_{DD Max}

C_IN

C_OUT

C_I/O

Input Capacitance (see Note 2)

Output Capacitance

f = 1MHz @ 0V

2

4

8

pF

Bidir I/O Capacitance

4

Note 2: Excluding package

CMOS Output DC Electrical Characteristics

Symbol

Parameter

Test Condition

I_OL= 4mA

_OL= 2mA

I_OH= 4mA

_OH= 4mA

Min.

Typ.

Max.

Unit

V_OL

Low Level Output Voltage

0.5

0.4

V

I

V_OH

High Level Output Voltage

V_DD-0.5

V_DD-0.4

V

I

Protection

Symbol

Parameter

Test Condition

C = 100pF, R = 1.5kΩ

Min.

Typ.

Max.

Unit

V_ESD

Electrostatic Protection

2000

V

38/54

STLC5460

APPENDIX

MEMORY ACCESSES

COMMAND MEMORY ACCESSES. CM=1

Write

CommandMemory:

CMD and SRC registers are written if their bits have not the right value.

CMD and SRC registers can be written in any order.

DST register is always written the last

CMD

SRC

DST

1 of 192 input timeslots

1 of 2 insert registers

R CM

Subchannel select

and data rate

1 of 192 output timeslots

1 of 2 extract registers

0

1

6

8

R=0 Write

CM=1 Command

Memory

IN

Command Memory

A

194 words of 14 bits

Read Command Memory in two steps:

First step: register writing

CMD register is written if its bits are not the right value.

SRC registeris not written.

DST registeris always written the last.

CMD

SRC

DST

R

1

CM

1

1 of 192 output timeslots

1 of 2 extract register

bits not used

Register not writte

n

2

8

Command Memory

194 words of 14 bits

OUT

A

OUT

6

8

1 of 192 input timeslots

1 of 2 insert registers

1 of 192 output timeslot

1 of 2 extract registers

R CM selected channel

s

1

and data rate

CMD

SRC

DST

Second step: register reading:

CMD and SRC registers may be read in any order.

DST registeris not changed.

39/54

STLC5460

AUXILIARY MEMORY ACCESSES: CM=0

Write Auxiliary Memory: Transmit command / indicate channels

CMD and SRC registers are written if their bits have not the right value.

CMD and SRC registers can be written in any order.

DST register is always written the last.

CMD

SRC

DST

1 of 16 TX C/I

channels

MON TX

R CM

0 0

Bits not used

Primitive to transmit

0

1

4 or 6

R=0 Write

CM=0 Auxiliary Memory

6

IN

AUXILIARY MEMORY

16 words assigned to

A

8 TX C/I channels of MUX0

&

8 TX C/I channels of MUX1

Read Auxiliary Memory in two steps: Transmit command / indicate channels

First step: register writing:

CMD register is written if its bits are not the right value.

SRC registeris not written.

DST registeris always written the last.

CMD

SRC

DST

MON TX

1 of 16 TX C/I

R CM

bits not used

Register not writte

0

1

channels

0

2

6

n

AUXILIARY MEMORY

16 words assigned to

8 TX C/I channels of MUX0

&

A

8 TX C/I channels of MUX1

OUT

2

4 or 6

channel status & Primitive

which has been transmitted

MON TX

1 of 16 TX C/I

channels

R CM

C/I channel status

CMD

0

1

0

SRC

DST

Second step: register reading:

CMD and SRC registers may be read in any order.

DST register is not changed.

40/54

STLC5460

AUXILIARY MEMORY ACCESSES: CM=0

Write Auxiliary Memory: Receive command / indicate channels

CMD and SRC registers are written if their bits have not the right value.

CMD and SRC registers can be written in any order.

DST register is always written the last.

CMD

Bits not used

SRC

DST

MON TX

1 of 16 TX C/I

channels

R CM

Primitive to initiate

0

4 or 6

6

R=0 Write

CM=0 Auxiliary Memory

N

AUXILIARY MEMORY

A

16 words assigned to

8 RX C/I channels of MUX0

I

&

8 RX C/I channels of MUX1

Read

Receive command / indicate

Auxiliary Memory in two steps:

channels

First step: register writing:

CMD register is written if its bits are not the right value.

SRC registeris not written.

DST registeris always written the last.

CMD

SRC

DST

C

0

1 of 16 TX C/I

channels

R

1

M

MON TX

bits not used

Register not written

0

2

6

AUXILIARY MEMORY

16 words assigned to

8 RX C/I channels of MUX0

&

A

8 RX C/I channels of MUX1

OUT

2

4 or 6

MON TX 1 of 16 TX C/I

channels

R CM

channel status & Primitive

which has been received

channel status

CMD

0

1

0

SRC

DST

Second step: register reading:

CMD and SRC registers may be read in any order.

DST registeris not changed.

41/54

STLC5460

AUXILIARY MEMORY ACCESSES: CM=0

Write Auxiliary Memory: Transmit Monitor channels

CMD and SRC registers are written if their bits have not the right value.

CMD and SRC registers can be written in any order.

DST register is always written the last.

CMD

SRC

DST

R CM

MON TX

1 of 16 TX MON

channels

Command bits

Data to transmit

8

0

1

3

6

R=0 Write

CM=0 Auxiliary Memory

IN

AUXILIARY MEMORY

16 words assigned to

8 TX MON channels of MUX0

&

A

8 TX MON channels of MUX1

Read

Transmit Monitor

channels

Auxiliary Memory in two steps:

First step: register writing:

CMD register is written if its bits are not the right value.

SRC registeris not written.

DST registeris always written the last.

CMD

SRC

DST

C

0

R

1

M

MON TX 1 of 16 TX MON

Register not written

bits not used

1

channels

2

6

AUXILIARY MEMORY

16 words assigned to

8 TX MON channels of MUX0

&

A

8 TX MON channels of MUX1

OUT

5

8

data which has been

transmitted

R CM

MON status

CMD

MON TX 1 of 16 TX MON

channels

1

0

1

SRC

DST

Second step: register reading:

CMD and SRC registers may be read in any order.

DST registeris not changed.

42/54

STLC5460

AUXILIARY MEMORY ACCESSES: CM=0

Write Auxiliary Memory: Receive Monitor channels

CMD and SRC registers are written if their bits have not the right value.

CMD and SRC registers can be written in any order.

DST register is always written the last.

CMD

Not used

SRC

DST

1 of 16 TX MON

channel s

MON TX

R CM

Data to initiate

1

0

8

6

R=0 Write

CM=0 Auxiliary Memory

IN

AUXILIARY MEMORY

16 words assigned t o

8 RX MON channels of MUX 0

&

A

8 RX MON channels of MUX 1

Read Auxiliary Memory in two steps: Receive Monitor channels

First step: register writing:

CMD register is written if its bits are not the right value.

SRC registeris not written.

DST registeris always written the last.

CMD

SRC

DST

CM

0

R

1

1 of 16 TX MON

channels

MON TX

bits not used

Register not written

1

0

2

6

AUXILIARY MEMORY

16 words assigned to

8 RX MON channels of MUX0

&

A

8 RX MON channels of MUX1

OUT

3

8

R CM

data which has been

received

MON TX 1 of 16 TX MON

channels

MON status

CMD

1

0

1

0

SRC

DST

Second step, register reading:

CMD and SRC registers may be read in any order.

DST registeris not changed.

43/54

STLC5460

Table 1: Data Memory Address

Source Register

INPUT

PCM

1

N1

0

N0

0

TS4

TS3

TS2

TS1

TS0

TS 0 to TS 31

PCM 0

PCM 1

0

1

0

TS 0 to TS 31

PCM 2

PCM 3

1

0

TS 0 to TS 31

MUX 0

0

1

MUX 1

1

0

TS 0 to TS 31

0

1

INSERT REG. A

INSERT REG. B

0

Table 2:

ControlMemory Address

Destination Register

INPUT

PCM

1

N1

0

N0

0

TS4

TS3

TS2

TS1

TS0

TS 0 to TS 31

PCM 0

PCM 1

PCM 2

PCM 3

MUX 0

MUX 1

0

1

0

1

0

TS 0 to TS 31

0

1

0

TS 0 to TS 31

0

1

EXTRACT REG. A

EXTRACT REG. B

0

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STLC5460

Table 3: AuxiliaryMemory Addresss

Destination Register

MUX

CHANNEL

-

MON

TX

0

-

M0

G2

G1

G0

RX

0

1

0

1

GCI channel 0 to 7

CI

TX

RX

TX

RX

TX

RX

TX

1

MUX 0

0

MON

CI

-

1

0

1

MUX 1

1

0

MON

1

Table 4: AuxiliaryMemory Data

CHANNEL

Source Register

TX Command Indicate

RX Command Indicate

TX and RX Monitor

-

C6

C5

M5

C4

M4

C3

M3

C2

M2

C1

M1

OVR

M8

PR

M7

M6

C1/6: Primitive

PR: Primitive received

OVR: Overrun

M1/8: Byte

45/54

STLC5460

MEMORY ACCESS ALGORITHM

Figure 4: Controlor Auxiliary Memory Accesses

WRITE MEMORY

READ MEMORY

Read Status Register

Ye s

Yes

BUSY

No

Write Command Register

with R/W=1

w ith R/W=0

Write Source Register

Write Destination Register

E N D

Write Destination Register

Read Status Register

Ye s

BUSY

No

Read Comm and Register

(optional)

Read Source Register

Read Destination Register

(optional)

E N D

46/54

STLC5460

Figure 5: Bidirectional Switching

CHANNELS AT 64kbit/s

Ex 1:

Source Register

1 1 0 0 0 0 1 1

PCM TS 3

0 0 1 0 1 1 0 1

2

Destination Register

MUX 1

TS 13

(or MUX 1 B2 of GCI 3)

Simple switching (BID=0)

The output MUX 1-TS 13 receives the contents of the input PCM 2-TS 3

Bidirectional switching (BID=1)

The output MUX 1-TS 13 receives the contents of the input PCM2-TS 3

AND

The output PCM 2-TS 3 receives the contents of the input MUX 1-TS 13

Ex 2:

Source Register

0 1 0 0 0 0 0 0

Insert Register A

Destination Register

0 0 1 0 1 1 0 1

MUX 1

TS 13

(or MUX 1 B2 of GCI 3)

Simple switching (BID=0)

The output MUX 1-TS 13 receives the contents of the Insert Register A

Bidirectional switching (BID=1)

The output MUX 1-TS 13 receives the contents of the Insert Register A

AND

The Extract Register A receives the contents of the input MUX 1-TS 13

47/54

STLC5460

Figure 6: Bidirectional Switching and Loopback

Ex 3:

Source Register

0 1 0 0 0 0 0 0

Insert Register

A

Destination Register

0 1 0 0 0 0 0 1

Extract Register

B

Simple switching (BID=0)

The Extract Register B receives the contents of the Insert Register A

Bidirectional switching (BID=1)

The Extract Register B receives the contents of the Insert Register A

AND

The Extract Register A receives the contents of the Insert Register B

Ex 4:

Source Register

1 0 1 1 0 1 0 1

PCM TS 21

1 0 1 0 0 1 1 1

PCM 1 TS 7

1

Destination Register

Simple switching (BID=0)

The output PCM 1-TS 7 receives the contents of the input PCM 1-TS 21

This is a loopback

Bidirectional switching (BID=1)

The output PCM 1-TS 7 receives the contents of the input PCM 1-TS21

AND

The output PCM 1-TS 21receivesthe contents of the input PCM 1-TS 7

Two loopbacks are established

48/54

STLC5460

Figure 7: Switching& Broadcast

One source to several destinations

Ex 5:PCM to MUX

Source Register

1 0 1 0 0 0 1 0

PCM 1

TS 2

Destination Register

0 0 1 0 1 1 0 1

MUX 1

TS 13

(or MUX 1 B2 of GCI 3)

Destination Register

0 0 0 1 1 0 0 1

MUX 0

TS 25

(or MUX 0 B2 of GCI 6)

Broadcast

The output MUX 1-TS 13 receives the contents of the input PCM 1-TS 2

AND

The output MUX 0-TS 25 receives the contents of the input PCM 1-TS 2

and so on

Ex 6:Insert Register A to MUX

Source Register

0 1 0 0 0 0 0 0

Insert Register A

Destination Register

0 0 0 1 1 1 0 0

MUX 0

TS 28

(or MUX 0 B1 of GCI 7)

0 0 1 1 0 1 0 1

Destination Register

Broadcast

MUX 1

TS 21

(or MUX 1 B2 of GCI 5)

The output MUX 0-TS 28 receives the contents of the Insert Register A

AND

The output MUX 1-TS 21 receives the contents of the Insert Register A

49/54

STLC5460

Figure 8: Bidirectional Switching Channels at 16kbit/s

Ex7: Channel at 16 kbit/s

Command Register

0 1 0 1 1 0 0 1

R CM CH SS DS

1 1 0 0 0 0 1 1

Source Register

PCM

2

TS 3

Destination Register

0 0 1 0 1 1 0 1

MUX 1

TS 13

(or MUX 1 B2 of GCI 3)

Simple switching (BID=0)

The output MUX 1-TS 13 (bits 4-5) receives the contents of the input PCM 2-TS 3 (bits 2-3)

Bidirectional switching (BID=1)

The output MUX 1-TS 13 (bits 4-5) receives the contents of the input PCM 2-TS 3 (bits 2-3)

AND

the output PCM 2-TS 3 (bits 2-3) receives the contents of the input MUX 1-TS 13 (bits 4-5)

Ex8: Channel at 16 kbit/s (Insert register)

0 1 0 1 0 0 0 1

Command Register

R CM CH SS DS

Source Register

0 1 0 0 0 0 0 0

Insert Register A

Destination Register

0 0 1 0 1 1 0 1

MUX 1

TS 13

(or MUX 1 B2 of GCI 3)

Simple switching (BID=0)

The output MUX 1-TS 13 (bits 4-5) receives the contents of the Insert Register A bits 6-7.

Bidirectional switching (BID=1)

The output MUX 1-TS 13 (bits 4-5) receives the contents of the Insert Register A bits 6-7 AND

the Extract Register A (bits 6-7) receives the contents of the input MUX 1-TS 13 (bits 4-5).

R Read; CM Command Memory; CH Channel; SS Source Subchannel; DS Destination Subcha nnel

50/54

STLC5460

Figure 9: Bidirectional Switching Channels at 32kbit/s

Ex 9: Channels at 32 kbit/s

Command Register

0 1 1 0 0 1 0 0

R CMCH SS DS

1 1 1 1 0 0 1 1

Source Register

PCM 3

0 0 1 1 1 1 0 1

MUX 1 TS 29

(or MUX 1 B2 of GCI 7)

TS 19

Destination Register

Simple switching

(BID=0)

The output MUX 1-TS 29 (bits 4 to 7) receivesthe contents of the input PCM 3-TS19 (bits 0 to 3)

Bidirectional switching

(BID=1)

The output MUX 1-TS 29 (bits 4 to 7) receives the contents of the input PCM 3-TS19 (bits 0 to 3)

AND

The output PCM 3-TS19 (bits 0 to 3) receivesthe contents of the input MUX 1-TS 29 (bits 4 to 7)

Ex: 10: Channels at 32 kbit/s (Insert register)

Command Register

0 1 1 0 0 0 0 0

R CM CH SS DS

Source Register

0 1 0 0 0 0 0 0

Insert Register A

Destination Register

0 0 1 0 1 1 0 1

MUX 1

TS 13

(or MUX 1 B2 of GCI 3)

Simple switching (BID=0)

The output MUX 1-TS AND 13 (bits4 to 7) receives the contents of the Insert Register A (bits 4 to 7).

(BID=1)

Bidirectional switching

The output MUX 1-TS 13 (bits 4 to 7) receivesthe contents of the Insert Register A bits (4 to 7)

AND

the Extract Register A bits (4 to 7) receives the contents of the input MUX 1-TS 13 bits (4 to7).

R Read; CM Command Memory; CH Chan nel; SS Source Subchan nel;DS Destination Su bchannel

51/54

STLC5460

INTERRUPT EXAMPLE

Figure 10: InterruptGeneratedby RX Monitor Channel.

No

Interrupt

Yes

Read Interrupt Register

MONR=1

Read Receive MON Status Registe r

to know the number of the channel

w hich has generated the Interrupt

and the Status Bits associated.

No

Byte=1

Yes

Read Auxiliary Memory w ith

RX MON channel number into

Destination Re gister

The byte received is into

Source Register

END

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STLC5460

PLCC44 PACKAGE MECHANICAL DATA

mm

inch

TYP.

DIM.

MIN.

17.4

16.51

3.65

4.2

TYP.

MAX.

17.65

16.65

3.7

MIN.

0.685

0.650

0.144

0.165

0.102

MAX.

0.695

0.656

0.146

0.180

0.108

A

B

C

D

4.57

2.74

d1

d2

E

2.59

0.68

0.027

14.99

16

0.590

0.630

e

1.27

12.7

0.46

0.71

0.050

0.500

0.018

0.028

e3

F

F1

G

0.101

0.004

M

M1

1.16

1.14

0.046

0.045

53/54

STLC5460

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the

consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No

license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned

in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.

SGS-THOMSON Microelectronics products are not authorized for use as criticalcomponentsin life support devices or systems without express

written approval of SGS-THOMSON Microelectronics.

SGS-THOMSON Microelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands -

Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.

54/54


型号：	STLC5460
厂家：	ST
描述：	LINE CARD INTERFACE CONTROLLER 线路卡接口控制器控制器
文件：	总54页 (文件大小：375K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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