STS15N4LLF5 [STMICROELECTRONICS]

15A, 40V, 0.0083ohm, N-CHANNEL, Si, POWER, MOSFET, 6 X 5 MM, ROHS COMPLIANT, POWERFLAT-8;


型号：	STS15N4LLF5
厂家：	ST
描述：	15A, 40V, 0.0083ohm, N-CHANNEL, Si, POWER, MOSFET, 6 X 5 MM, ROHS COMPLIANT, POWERFLAT-8 开关脉冲光电二极管晶体管
文件：	总12页 (文件大小：571K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

STS15N4LLF5

N-channel 40 V, 0.00625 Ω, 15 A, SO-8

STripFET™ Power MOSFET

Features

Type

V_DSS

R_DS(on)max.

I_D

STS15N4LLF5

40 V

< 0.0076 Ω

15 A

■ Optimal R

x Q trade-off @ 4.5 V

DS(on)

■ Conduction losses reduced

■ Switching losses reduced

SO-8

Applications

■ Switching application

Description

Figure 1.

Internal schematic diagram

This STripFET™V Power MOSFET technology is

among the latest improvements, which have been

especially tailored to achieve very low on-state

resistance providing also one of the best-in-class

figure of merit (FOM).

Table 1.

Order code

STS15N4LLF5

Device summary

Marking

Package

SO-8

Packaging

15C4L

Tape and reel

April 2010

Doc ID 17339 Rev 1

1/12

www.st.com

Contents

STS15N4LLF5

Contents

Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.1

Electrical characteristics (curves)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2/12

Doc ID 17339 Rev 1

STS15N4LLF5

Electrical ratings

Table 2.

Symbol

Absolute maximim ratings

Parameter

Value

Unit

V_DS

V_GS

Drain-source voltage (V_GS= 0)

Gate-source voltage

(1)

V_GS

Gate- source voltage

I_D

Drain current (continuous) at T_C= 25 °C

Drain current (continuous) at T_C= 100 °C

Drain current (pulsed)

(2)

I_DM

63.6

P_TOT

Total dissipation at T_C= 25 °C

Single pulse avalanche energy

(3)

E_AS

1090

1. Guaranteed for test time < 15ms

2. Pulse width limited by Tjmax

3. Starting T_j= 25 °C, I_D= 7.5 A, V_DD= 25 V

Table 3.

Symbol

Thermal resistance

Parameter

Value

Unit

(1)

R_thj-pcb

T_l

Thermal resistance junction-pcb max

Maximum lead temperature for soldering

°C/W

°C

-55 to 150

T_stg

Storage temperature

°C

1. When mounted of FR-4 board with 1 inch pad, 2oz of Cu and t < 10 sec

Doc ID 17339 Rev 1

3/12

Electrical characteristics

STS15N4LLF5

Electrical characteristics

(T = 25 °C unless otherwise specified)

Table 4.

Symbol

On/off states

Parameter

Test conditions

Min.

Typ.

Max. Unit

Drain-source breakdown

voltage

V_(BR)DSS

I_D= 250 µA, V_GS= 0

V_DS= max rating,

µA

Zero gate voltage drain

current (V_GS= 0)

I_DSS

V_DS=max rating @125°C

100

Gate body leakage

Current (V_DS= 0)

I_GSS

V_GS= 16 V

±200

V_GS(th)

R_DS(on)

Gate threshold voltage

V_DS= V_GS, I_D= 250 µA

V_GS= 10 V, I_D= 7.5 A

V_GS= 4.5 V, I_D= 7.5 A

0.00625 0.0067

0.0076 0.0083

Ω

Static drain-source on

resistance

Table 5.

Symbol

Dynamic

Parameter

Test conditions

Min.

Typ. Max. Unit

Input capacitance

Output capacitance

C_iss

C_oss

C_rss

1570

257

V_DS= 25 V, f=1 MHz,

V_GS= 0

Reverse transfer

capacitance

Q_g

Q_gs

Q_gd

Total gate charge

Gate-source charge

Gate-drain charge

V_DD= 15 V, I_D= 18 A

V_GS= 4.5 V

12.9

3.9

(see Figure 14)

5.3

f=1 MHz Gate DC Bias = 0

Test signal level = 20 mV

open drain

R_G

Gate input resistance

1.5

Ω

Table 6.

Symbol

Switching times

Parameter

Test conditions

Min.

Typ. Max. Unit

t_d(on)

t_r

t_d(off)

t_f

Turn-on delay time

Rise time

V_DD= 15 V, I_D= 9 A,

R_G= 4.7 Ω, V_GS= 10 V

(see Figure 16)

Turn-off delay time

Fall time

5.2

4/12

Doc ID 17339 Rev 1

STS15N4LLF5

Electrical characteristics

Min. Typ. Max. Unit

Table 7.

Source drain diode

Parameter

Symbol

Test conditions

I_SD

Source-drain current

(1)

I_SDM

Source-drain current (pulsed)

(2)

V_SD

Forward on voltage

I_SD= 18 A, V_GS= 0

1.2

I_SD= 18 A, V_DD= 25 V,

di/dt = 100 A/µs,

t_rr

Reverse recovery time

Reverse recovery charge

Reverse recovery current

27.2

24.5

1.8

Q_rr

Tj = 150 °C

(see Figure 15)

I_RRM

1. Pulse width limited by safe operating area

2. Pulsed: pulse duration = 300µs, duty cycle 1.5%

Doc ID 17339 Rev 1

5/12

Electrical characteristics

STS15N4LLF5

2.1

Electrical characteristics (curves)

Figure 2.

Safe operating area

Figure 3.

Thermal impedance

!-ꢁꢈꢉꢊꢊVꢀ

ꢃ!ꢄ

4Jꢅꢀꢆꢁ #

4Cꢅꢇꢆ #

ꢀꢁꢁ

ꢀꢁ

3INGLE PULSE

ꢀꢁMS

ꢀꢁꢁMS

ꢀS

ꢀ

ꢁꢂꢀ

ꢀꢁ

6$3ꢃ6ꢄ

ꢁꢂꢀ

ꢀ

Figure 4.

Output characterisics

Figure 5.

Transfer characteristics

!-ꢁꢈꢆꢁꢁVꢀ

!-ꢁꢈꢆꢁꢀVꢀ

)$ꢃ!ꢄ

ꢀꢈꢁ

)$ꢃ!ꢄ

6$3ꢅꢇ6

6'3ꢅꢀꢁ6

ꢉ6

ꢉꢁ

ꢀꢉꢁ

ꢀꢇꢁ

ꢌꢆ

ꢌꢁ

ꢇꢆ

ꢇꢁ

ꢀꢁꢁ

ꢋꢁ

ꢀꢆ

ꢀꢁ

ꢈꢁ

ꢌ6

ꢉꢁ

ꢇꢁ

ꢁ

ꢆ

ꢁ

ꢆ

ꢇ

ꢇꢁ

ꢇꢆ 6$3ꢃ6ꢄ

ꢋ

ꢀꢁ 6^'3ꢃ6ꢄ

ꢁ

ꢀꢁ

ꢀꢆ

ꢉ

ꢈ

Figure 6.

Normalized B

vs temperature Figure 7.

Static drain-source on resistance

VDSS

!-ꢁꢎꢁꢁꢀVꢀ

!-ꢁꢎꢁꢁꢇVꢀ

"6$33

ꢃNORMꢄ

2$3ꢃONꢄ

ꢃM/HMꢄ

6'3ꢅꢀꢁ6

ꢊꢂꢎ

ꢊꢂꢈ

ꢊꢂꢆ

ꢀꢂꢀ

ꢀꢂꢁ

ꢁꢂꢊ

ꢁꢂꢋ

ꢊꢂꢉ

ꢊꢂꢌ

ꢍꢎꢆ

ꢍꢇꢆ

ꢇꢆ

ꢎꢆ

4^*ꢃ #ꢄ

ꢇ

ꢌ

ꢌꢂꢆ

)$ꢃ!ꢄ

ꢀꢇꢆ

ꢀꢎꢆ

ꢇꢂꢆ

ꢉ

ꢉꢂꢆ

ꢆ

6/12

Doc ID 17339 Rev 1

STS15N4LLF5

Electrical characteristics

Figure 8.

Gate charge vs gate-source voltage Figure 9.

Capacitance variations

!-ꢁꢎꢁꢁꢌVꢀ

!-ꢁꢎꢁꢁꢉVꢀ

6'3

ꢃ6ꢄ

ꢃP&ꢄ

6$$ꢅꢀꢆ6

)$ꢅꢀꢋ!

ꢀꢇ

ꢀꢁ

ꢋ

#ISS

ꢀꢁꢁꢁ

#OSS

#RSS

ꢈ

ꢀꢁꢁ

ꢀꢁ

ꢉ

ꢇ

ꢁ

ꢀꢁ

ꢇꢁ

ꢁꢂꢀ

ꢇꢆ

1^GꢃN#ꢄ

6$3ꢃ6ꢄ

ꢁ

ꢆ

ꢀꢆ

ꢀ

ꢀꢁ

Figure 10. Normalized gate threshold voltage Figure 11. Normalized on resistance vs

vs temperature temperature

!-ꢁꢎꢁꢁꢆVꢀ

!-ꢁꢎꢁꢁꢈVꢀ

6'3ꢃTHꢄ

ꢃNORMꢄ

2$3ꢃONꢄ

ꢃNORMꢄ

ꢀꢂꢇ

ꢀꢂꢁ

ꢇꢂꢁ

ꢀꢂꢋ

ꢀꢂꢈ

ꢀꢂꢉ

ꢁꢂꢋ

ꢀꢂꢇ

ꢀꢂꢁ

ꢁꢂꢋ

ꢁꢂꢈ

ꢁꢂꢉ

ꢁꢂꢈ

ꢁꢂꢉ

ꢍꢎꢆ

ꢍꢇꢆ

ꢇꢆ

ꢎꢆ

ꢀꢎꢆ 4^*ꢃ #ꢄ

ꢍꢇꢆ

ꢇꢆ

ꢎꢆ

4^*ꢃ #ꢄ

ꢀꢎꢆ

ꢀꢇꢆ

Figure 12. Source-drain diode forward

characteristics

!-ꢁꢎꢁꢁꢎVꢀ

63$ꢃ6ꢄ

4*ꢅꢍꢆꢆ #

ꢁꢂꢊ

ꢁꢂꢋ

ꢁꢂꢎ

ꢁꢂꢈ

ꢁꢂꢆ

4*ꢅꢇꢆ #

4*ꢅꢀꢎꢆ #

ꢁꢂꢉ

ꢁꢂꢌ

ꢁꢂꢇ

ꢁꢂꢀ

ꢁ

ꢆ

ꢀꢁ

ꢀꢆ

)3$ꢃ!ꢄ

Doc ID 17339 Rev 1

7/12

Test circuits

STS15N4LLF5

Test circuits

Figure 13. Switching times test circuit for

resistive load

Figure 14. Gate charge test circuit

VDD

12V

47kΩ

100nF

1kΩ

2200

3.3

µF

IG=CONST

V^DD

100Ω

Vⁱ=20V=VGMAX

D.U.T.

VGS

2200

µF

D.U.T.

V^G

2.7kΩ

47kΩ

1kΩ

AM01468v1

AM01469v1

Figure 15. Test circuit for inductive load

switching and diode recovery times

Figure 16. Unclamped inductive load test

circuit

FAST

DIODE

L=100µH

2200

µF

D.U.T.

3.3

µF

VDD

3.3

µF

1000

µF

V^DD

Ω

R^G

D.U.T.

AM01470v1

AM01471v1

Figure 17. Unclamped inductive waveform

Figure 18. Switching time waveform

ton

toff

tdoff

V(BR)DSS

tdon

90%

10%

90%

IDM

10%

VDS

VDD

90%

V^GS

10%

AM01472v1

AM01473v1

8/12

Doc ID 17339 Rev 1

STS15N4LLF5

Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK

specifications, grade definitions and product status are available at: www.st.com. ECOPACK

is an ST trademark.

Doc ID 17339 Rev 1

9/12

Package mechanical data

STS15N4LLF5

Table 1. SO-8 mechanical data

mm.

inch

Typ

Dim.

Min

Typ

Max

Min

Max

1.35

1.75

0.053

0.069

0.10

1.10

0.33

0.19

4.80

3.80

0.25

1.65

0.51

0.25

5.00

4.00

0.004

0.043

0.013

0.007

0.189

0.15

0.010

0.065

0.020

0.010

0.197

0.157

(1)

1.27

0.050

5.80

0.25

0.40

6.20

0.50

1.27

0.228

0.010

0.016

0.244

0.020

0.050

0° (min.), 8° (max.)

0.10

ddd

0.004

1. Dimensions D does not include mold flash, protru-sions or gate burrs. Mold flash, potrusions or gate burrs

shall not exceed 0.15mm (.006inch) in total (both side).

Figure 19. Package dimensions

10/12

Doc ID 17339 Rev 1

STS15N4LLF5

Revision history

Table 8.

Date

Revision history

Revision

Changes

07-Apr-2010

First release

Doc ID 17339 Rev 1

11/12

STS15N4LLF5

Please Read Carefully:

Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the

right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any

time, without notice.

All ST products are sold pursuant to ST’s terms and conditions of sale.

Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no

liability whatsoever relating to the choice, selection or use of the ST products and services described herein.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this

document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products

or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such

third party products or services or any intellectual property contained therein.

UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED

WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED

WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS

OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT

RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING

APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,

DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE

GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.

Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void

any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any

liability of ST.

ST and the ST logo are trademarks or registered trademarks of ST in various countries.

Information in this document supersedes and replaces all information previously supplied.

The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.

STMicroelectronics group of companies

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -

Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America

www.st.com

12/12

Doc ID 17339 Rev 1

STS15N4LLF5 [STMICROELECTRONICS]

相关型号：

STS17NF3LL

STS17NF3LL_06

STS17NH3LL

STS17NH3LL_07

STS17NH3LL_0710

STS1979

STS1979N

STS1979N

STS1980

STS1980N

STS1A2B1MTAGER

STS1A2B1MTAGEV